SM9103M
DVDRAM Head Amplifier LSI
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
PINOUT
The SM9103M is a photodiode photoelectric current-to-voltage conversion head amplifier LSI for
optical disk pickups in DVDRAM/DVDROM equipment. It sums the photodiode current data signals and
then converts the signals to a differential signal for
output. The output tracking servo and focusing servo
signals are derived from built-in sum and difference
circuits, and the gain for these servo signals can be
adjusted using serial interface controls. Each of the
signals from the photodiodes, used to generate DPD
(Differential Phase Detection) tracking servo signal,
is current-to-voltage converted and then also output.
It operates from a single 5 V supply, and is available
in 36-pin plastic SSOP packages.
36-pin SSOP
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RAM/ROM gain switching, low-noise RF signal
generator (differential output)
ROM tracking DPD signal output
Variable-gain RAM tracking push-pull signal output
Address signal, high-speed push-pull signal output
Variable-gain focus error signal output
Tracking PD sum signal output
Focus PD sum signal output
Offset correction timing output (logic)
Temperature monitor function
Serial interface to control internal parameter settings
Sleep-mode function
Single 5 V supply
36-pin plastic SSOP
MODE
1
36
SCLK
WRITE
2
35
SDATA
DGND
3
34
SENB
DVCC
4
33
CALREQ
TEMPO
5
32
TADD
TEMPI
6
31
TADDB
T1
7
30
CAPAP
T2
8
29
CAPAN
T3
9
28
TSUB
T4
10
27
TSUBB
F1
11
26
DATAP
F2
12
25
DATAN
AGND
13
24
DPDA
SM9103M
NPC
FEATURES
(Top view)
VREF
14
23
DPDB
FSUBB
15
22
DPDC
FSUB
16
21
DPDD
FADDB
17
20
AVCC
FADD
18
19
AGND
TYPICAL APPLICATIONS
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Double-speed DVDROM equipment
Double-speed DVDRAM equipment
ORDERING INFORMATION
Device
Package
SM9103M
36-pin SSOP
NIPPON PRECISION CIRCUITS—1
SM9103M
PACKAGE DIMENSIONS
(Unit: mm)
15.20 to 15.40
0 to 8°
0.85
0.51 ± 0.20 45°
10.11 to 10.51
7°
7.40 to 7.60
R0.63 to 0.89
0.51 to 1.01
7°
0.63 ± 0.10
0.23 to 0.32
0.10 to 0.30
2.44 to 2.64
0.80
0.29 to 0.39
BLOCK DIAGRAM
AVCC
VREF
AGND
DVCC
DGND
SCLK
SENB
SDATA
MODE
WRITE
+5V
Serial interface
to each block
T1
T2
T3
T4
A+B+C+D
Gain switching
amplifier
(RAM read/write,
ROM read)
Differential
output buffer
DATAP
DATAN
Amplifier
TADDB
TADD
(A+B)-(C+D)
Analog
Signal
processor
A
B
C
D
Differential
output buffer
Gain switch
(2dB step)
CAPAP
CAPAN
TSUBB
TSUB
Offset canceller
TEMPI
TEMPO
Buffer
DPDA
Buffer
DPDB
Buffer
DPDC
Buffer
Gain switch
(2dB step)
DPDD
CALREQ
FSUB
FSUBB
Amplifier
FADDB
FADD
+5V
Thermal sensor
Canceller control
Offset canceller
F1
F2
Gain switching
amplifier
Analog
Signal
processor
NIPPON PRECISION CIRCUITS—2
SM9103M
PIN DESCRIPTION
Number
Name
I/O1
1
MODE
Ipd
Mode switching/offset correction control input 1
2
WRITE
Ipd
Mode switching/offset correction control input 2
3
DGND
–
Logic circuit ground. Connect to the analog ground if there is no dedicated pickup or logic ground.
4
DVCC
–
Logic circuit supply. Connect to the analog supply if there is no dedicated pickup or logic supply.
5
TEMPO
O
Thermal sensor test output. Leave open for normal operation
6
TEMPI
I
Thermal sensor test input. Leave open for normal operation
7
T1
I
Tracking PD input A
8
T2
I
Tracking PD input B
9
T3
I
Tracking PD input C
10
T4
I
Tracking PD input D
11
F1
I
Focus PD input E
12
F2
I
Focus PD input F
13
AGND
–
Analog circuit ground
14
VREF
I
2.0 V reference voltage input
15
FSUBB
I
Focus error signal feedback input
16
FSUB
O
Focus error signal output
17
FADDB
I
Focus sum signal feedback input
18
FADD
O
Focus sum signal output
19
AGND
–
Analog circuit ground
20
AVCC
–
Analog circuit supply
21
DPDD
O
Buffered tracking signal output D for DPD servo
22
DPDC
O
Buffered tracking signal output C for DPD servo
23
DPDB
O
Buffered tracking signal output B for DPD servo
24
DPDA
O
Buffered tracking signal output A for DPD servo
25
DATAN
O
Phase-modulated data signal differential inverting output
26
DATAP
O
Phase-modulated data signal differential non-inverting output
27
TSUBB
I
Tracking push-pull signal feedback input
28
TSUB
O
Tracking push-pull signal output
29
CAPAN
O
ID data signal differential inverting output
30
CAPAP
O
ID data signal differential non-inverting output
31
TADDB
I
Tracking PD sum signal feedback input
32
TADD
O
Tracking PD sum signal output
33
CALREQ
O
Offset correction status/request output
34
SENB
I
Serial interface enable input
35
SDATA
I/O
36
SCLK
I
Function
Serial interface data input/acknowledge output
Serial interface clock input
1. I = input, Ipd = Input with built-in pull-down resistor, I/O = input/output, O = output
NIPPON PRECISION CIRCUITS—3
SM9103M
SPECIFICATIONS
Absolute Maximum Ratings
GND = 0 V
Parameter
Symbol
Condition
Rating
Unit
Supply voltage range
V CC
−0.5 to 7.0
V
Input voltage range
V IN
− 0.5 to V CC + 0.5
V
Input current range
IIN
− 3.0 to +3.0
mA
Operating temperature range
Topr
0 to 70
°C
Storage temperature range
Tstg
−40 to 125
°C
Power dissipation
PD
250
mW
Soldering temperature
Tsld
260
°C
Soldering time
tsld
10
s
Rating
Unit
Recommended Operating Conditions
GND = 0 V
Parameter
Symbol
Condition
Specs-guaranteed supply voltage
range
V CC
4.75 to 5.25
V
Operating supply voltage range
V CC
4.5 to 5.5
V
Reference voltage input
V REF
1.89 to 2.11
V
Operating temperature range
Topr
0 to 70
°C
NIPPON PRECISION CIRCUITS—4
SM9103M
DC Electrical Characteristics
VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C
Rating
Parameter
Symbol
Current consumption1
Condition
Unit
min
typ
max
ICC1
Operating mode
–
24
30
ICC2
Sleep mode
–
–
1
mA
MODE, WRITE, SENB, SDATA, SCLK HIGH-level
input voltage
V IH
0.8VCC
–
–
V
MODE, WRITE, SENB, SDATA, SCLK LOW-level
input voltage
V IL
–
–
0.2VCC
V
MODE, WRITE HIGH-level input current
IIH1
V IN = V CC
50
100
200
µA
SENB, SDATA, SCLK HIGH-level input current
IIH2
V IN = V CC
–
–
3
µA
MODE, WRITE, SENB, SDATA, SCLK LOW-level
input current
IIL
V IN = 0 V
−3
–
–
µA
V CC − 0.2
–
–
V
CALREQ HIGH-level output voltage
VOH
IOH = −0.2 mA
CALREQ LOW-level output voltage
VOL1
IOL = 0.8 mA
–
–
0.4
V
SDATA LOW-level output voltage
VOL2
IOL = 7 mA
–
–
1.0
V
VREF input current
IREF
V REF = 2.0 V
–
–
250
µA
1. 18 kΩ resistor connected between TSUB and TSUBB
47 kΩ resistor connected between TADD and TADDB
22 kΩ resistor connected between FSUB and FSUBB
27 kΩ resistor connected between FADD and FADDB
SENB, SDATA, SCLK connected to GND; All other pins (excluding supply and ground pins) open circuit.
Tracking PD Input Characteristics (T1, T2, T3, T4)
VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C
Rating
Parameter
Input impedance
Input conversion noise current
Pin voltage
Condition
Unit
No signal
typ
max
–
–
250
RAM
read1
–
0.035
–
ROM
read1
–
0.27
–
–
–
1.5
100 kHz to 10 MHz
No signal
min
Ω
µA rms
V
1. DATAP − DATAN output difference operation when 10 pF capacitors are connected to T1, T2, T3, T4
NIPPON PRECISION CIRCUITS—5
SM9103M
Data Signal Processor Characteristics
VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C
Rating
Parameter
Condition
DATAP −DATAN current-to-voltage
converter coefficient1
CAPAP −CAPAN current-to-voltage
converter coefficient2
Unit
min
typ
max
RAM read
10.0
12.5
15.0
ROM read
2.50
3.12
3.74
RAM read
11.3
14.1
16.9
kΩ
–
–
100
Ω
DATAP, DATAN, CAPAP, CAPAN output
impedance
kΩ
DATAP, DATAN, CAPAP, CAPAN output
center voltage3
No signal
0.9VREF
–
1.1VREF
V
CAPAP, CAPAN output center voltage
difference3
No signal
–
–
±50
mV
DATAP, DATAN, CAPAP, CAPAN output
operating output voltage
10 kΩ load, output center voltage reference
−0.7
–
+0.7
V
Variable coefficient switching time
RAM ↔ ROM read
–
–
10
ms
Saturation output reset time4
RAM write → RAM read
–
–
500
ns
DATAP, DATAN signal bandwidth5
f = 100 kHz −3 dB frequency
19
–
–
MHz
CAPAP, CAPAN signal bandwidth5
f = 100 kHz −3 dB frequency
20
–
–
MHz
DATAP −DATAN, CAPAP −CAPAN gain
peaking5
f = 100 kHz −3 dB frequency
−3
–
+0.5
dB
DATAP −DATAN, CAPAP −CAPAN group
delay time5
f = 1 to 10 MHz
–
–
±1.0
ns
1.
2.
3.
4.
5.
[DATAP − DATAN] = K × [IT1 + IT2 + IT3 + IT4]
[CAPAP − CAPAN] = K × {[IT1 + IT2] − [IT3 + IT4]}
5 kΩ load connected to ground to prevent abnormal operation
Converging to within final value ± 10%
10 pF input load capacitors connected to T1, T2, T3, T4. DATAP, DATAN, CAPAP, CAPAN output load conditions shown below.
0.01µF
0.01µF
DATAP
CAPAP
5pF
5pF
10pF
5pF
10kΩ
10kΩ
0.01µF
0.01µF
CAPAN
DATAN
5pF
5pF
10pF
5pF
NIPPON PRECISION CIRCUITS—6
SM9103M
Tracking Signal Processor Characteristics
VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C
Rating
Parameter
Condition
typ
max
10.64
11.95
13.26
2.67
2.99
9.92
RAM write
1.78
1.99
2.20
RAM read
27.82
31.25
34.68
6.95
7.80
8.65
RAM write
4.63
5.20
5.77
RAM read
40.0
50.0
60.0
ROM read
10.0
12.5
15.0
–
–
±2
%
–
–
100
Ω
RAM read
TSUB current-to-voltage converter
coefficient1
TADD current-to-voltage converter
coefficient2
DPDA, DPDB, DPDC, DPDD
current-to-voltage converter coefficient3
T1, T2, T3, T4 converter coefficient
relative error
Unit
min
ROM read
ROM read
R f = 18 kΩ,
VOUT = V REF ± 0.8 V
R f = 47 kΩ
kΩ
kΩ
kΩ
TSUB output, RAM/ROM read
TSUB, TADD, DPDA, DPDB, DPDC,
DPDD output impedance
TSUB operating output voltage
10 kΩ load connected to VREF
1
–
3
V
TADD, DPDA, DPDB, DPDC, DPDD
operating output voltage
10 kΩ load connected to VREF
V REF
–
3
V
RAM read ↔ ROM read
–
–
10
ms
Converter coefficient switching time
RAM write ↔ RAM read
–
–
3
µs
TSUB, TADD signal bandwidth4
DC to −3 dB frequency
1
–
–
MHz
DPDA, DPDB, DPDC, DPDD signal
bandwidth4
f = 100 kHz to −3 dB frequency
5
–
–
MHz
TSUB, TADD gain peaking4
f = 10 kHz to −3 dB frequency
−3
–
+0.5
dB
DPDA, DPDB, DPDC, DPDD gain
peaking4
f = 100 kHz to −3 dB frequency
−3
–
+4.0
dB
TSUB phase response4
@ f = 100 kHz
–
–
10
°
f = 1 to 5 MHz group delay differential
absolute value
–
–
5
Relative error between 4 pins
–
–
1.0
RAM read/write max
gain
–
–
±10.0
RAM read, min to max
gain
–
–
±26
RAM read/write
differential gain max.
–
–
±4
ROM read,
gain min/max
–
–
±100
RAM read
–
–
±30
ROM read
–
–
±300
−550
–
+50
mV
–
–
±0.4
mV/°C
−16
–
+14
dB
–
2
–
dB
DPDA, DPDB, DPDC, DPDD group
delay4
TSUB offset voltage
TADD offset voltage
No input signal,
V REF reference,
post-correction,
Ta = 25°C,
R f = 18 kΩ
No input signal,
V REF reference
DPDA, DPDB, DPDC, DPDD offset
voltage
No input signal,
V REF reference
TSUB offset voltage temperature
coefficient
R f = 18 kΩ
TSUB variable gain range
TSUB variable gain step width
ns
mV
mV
RAM/ROM read
NIPPON PRECISION CIRCUITS—7
SM9103M
Rating
Parameter
TSUB gain switching absolute accuracy
1.
2.
3.
4.
Condition
VOUT = V REF ±
0.8 V
Unit
min
typ
max
−16 to +8 dB
–
–
±0.5
+10 to +14 dB
–
–
±1.0
dB
TSUB = K × {[IT1 + IT2] − [IT3 + IT4]}, gain = 0 dB
TADD = K × [IT1 + IT2 + IT3 + IT4]
DPDA = K × IT1, DPDB = K × IT2, DPDC = K × IT3, DPDD = K × IT4
T1, T2, T3, T4: 10 pF input load capacitance
TSUB, TADD, DPDA, DPDB, DPDC, DPDD: 10 pF output load capacitance
TSUB, TADD: 10 kΩ load resistance
DPDA, DPDB, DPDC, DPDD: 100 kΩ load resistance
Focus PD Input Characteristics (F1, F2)
VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C
Rating
Parameter
Input impedance
Condition
Unit
No signal
Input conversion noise current
Pin voltage
DC to 10 kHz
min
typ
max
–
–
250
RAM
read1
–
–
24
ROM
read1
–
–
96
RAM
write1
–
–
150
–
–
±50
No signal, V REF reference
Ω
nArms
mV
1. Conversion from FSUB output noise value when 14 pF capacitors connected to F1 and F2
Focus Signal Processor Characteristics
VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C
Rating
Parameter
Condition
typ
max
370
415
460
94
105
116
RAM write
58
65
72
RAM read
223
250
277
56.1
63
69.9
35.6
40
44.1
–
–
±2
%
–
–
100
Ω
RAM read
FSUB current-to-voltage converter
coefficient1
FADD current-to-voltage converter
coefficient2
ROM read
ROM read
R f = 22 kΩ,
VOUT = V REF ± 0.35 V
R f = 27 kΩ
RAM write
F1, F2 converter coefficient relative error
Unit
min
FSUB output, RAM/ROM read
FSUB, FADD output impedance
kΩ
kΩ
FSUB operating output voltage
10 kΩ load connected to VREF
1
–
3
V
FADD operating output voltage
10 kΩ load connected to VREF
V REF
–
3
V
RAM read ↔ ROM read
–
–
10
ms
RAM write ↔ RAM read
–
–
3
µs
DC to −3 dB frequency
200
–
–
kHz
f = 10 kHz to −3 dB frequency
−3
–
+0.5
dB
@ f = 10 kHz
–
–
5
°
Converter coefficient switching time
FSUB, FADD signal bandwidth3
FSUB, FADD gain
peaking3
FSUB, FADD phase
response3
NIPPON PRECISION CIRCUITS—8
SM9103M
Rating
Parameter
Condition
No input signal,
V REF reference,
post-correction,
Ta = 25°C
FSUB offset voltage
Unit
min
typ
max
RAM read/write, ROM
read max gain
–
–
±7.0
RAM read, min to max
gain
–
–
±21
RAM read/write
differential gain max.
–
–
±4
–
–
±50
mV
–
–
±0.22
mV/°C
−16
–
+14
dB
–
2
–
dB
−16 to +8 dB
–
–
±0.5
+10 to +14 dB
–
–
±1.0
No input signal, VREF reference
FADD offset voltage
FSUB offset voltage temperature
coefficient
FSUB variable gain range
FSUB variable gain step width
FSUB gain switching absolute accuracy
VOUT = V REF ±
0.35 V
mV
dB
1. FSUB = K × [IF1 − IF2], gain = 0 dB
2. FADD = K × [IF1 + IF2]
3. F1, F2: 14 pF input load capacitance
FSUB, FADD: 10 pF output load capacitance, 10 kΩ load resistance
Mode Control Logic
Control input
Operating mode
WRITE
MODE
LOW or open
LOW or open
RAM read
LOW or open
HIGH
ROM read
HIGH
LOW or open
HIGH
HIGH
Offset correction
Active
RAM write
Inactive
Offset Correction Characteristics
VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C
Rating
Parameter
Symbol
Condition
Unit
min
typ
max
TSUB offset residual
V REF reference, Ta = 25 °C
–
–
±8.5
mV
FSUB offset residual
V REF reference, Ta = 25 °C
–
–
±5.5
mV
Supply voltage droop detect level
V1
1.9
2.8
3.7
V
Correction circuit startup supply voltage
V2
3.2
3.8
4.4
V
V2 − V1
0.7
1.0
1.3
V
Correction thermal sensor detect
temperature
15
20
25
°C
Offset correction time
–
–
150
ms
V 1 and V 2 difference
NIPPON PRECISION CIRCUITS—9
SM9103M
Serial Interface Characteristics
VCC = 5 V ± 5%, GND = 0 V, Ta = 0 to 70 °C
Rating
Parameter
Symbol
Condition
Unit
min
typ
max
SCLK pulse cycle
tcySCK
100
–
–
ns
SCLK HIGH-level pulsewidth
twhSCK
40
–
–
ns
SCLK LOW-level pulsewidth
twlSCK
40
–
–
ns
SENB setup time
tsSEN
20
–
–
ns
SENB hold time
thSEN
40
–
–
ns
SDATA setup time
tsSDA
15
–
–
ns
SDATA hold time
thSDA
15
–
–
ns
ACK setup time1
tsACK
0
–
20
ns
ACK hold time1
thACK
–
–
50
ns
SENB interval
tinSEN
100
–
–
ns
1. ACK is the acknowledge output (n-channel open-drain). LOW-level output when the data received is valid.
SDATA load capacitance is 15 pF.
tinSEN
SENB
tsSEN twhSCK twlSCK
thSEN
tcySCK
SCLOCK
thACK
tsSDA thSDA
SDATA
Controller
SDATA
Port
bit 0
LSB
tsACK
bit 1
bit 15
MSB
ACK
High Impedance
NIPPON PRECISION CIRCUITS—10
SM9103M
FUNCTIONAL DESCRIPTION
Serial Interface
The SM9103M uses a serial interface comprising 2
ports to control and set TSUB/FSUB output gain
switching, sleep mode to reduce current consump-
tion, and TSUB/FSUB offset correction. The address
and bit configuration of each port is shown in table 1.
Table 1. Port address and bit configuration1
Bit number
15
14
13
12
11
10
9
8
7
6
5
Data
4
3
2
1
0
Address
MSB
LSB
TG3
TG2
TG1
TG0
FG3
FG2
FG1
FG0
×
LOW
LOW
LOW
LOW
LOW
×
×
SL1
CS1
–
–
–
–
–
–
×
LOW
LOW
LOW
LOW
HIGH
×
×
1. × = don’t care, – = unassigned
TG3 to TG0: TSUB gain set bits. Default = 0111 (0 dB)
FG3 to FG0: FSUB gain set bits. Default = 0111 (0 dB)
SL1: sleep mode set bit. Sleep mode when 1, normal operation when 0. Default = 0.
CS1: offset correction control. Offset correction when 1, normal operation when 0. Default = 0.
Serial data is input on SDATA with the LSB first in
sync with the falling edge of the SCLK clock. After
the 16th SCLK falling edge and 16 bits of valid data
has been input, the SDATA n-channel open-drain
output goes LOW to perform the function of an
acknowledge signal.
If the number of SCLK cycles which occur when
SENB (serial interface enable) is HIGH is less than
16, the received data is ignored and the internal port
is not updated. If the number of SCLK cycles is
greater than 16, the data is still considered value up
to the 16th SCLK falling edge, the data is latched
into the internal port, and the acknowledge signal is
output. The acknowledge signal is held until SENB
goes LOW again.
Data Signal Processor
This stage creates the data signal and ID signal for
output. The weak current from the tracking PD cells
(T1, T2, T3, T4) are input to the front-end amplifier
where the signals are current-to-voltage converted at
fixed gain.
The gain setting is controlled by pins WRITE and
MODE. WRITE switches between read/write, and
MODE switches the gain between values corresponding to high-reflectivity and low-reflectivity
discs. These signals control the settings for RAM
(low-reflectivity disc) read/write and ROM
(high-reflectivity disc) read.
The front-end amplifier outputs are processed by the
signal processor block to generate intermediate signals. The data signal, (A + B + C + D), is converted
to a difference signal by a differential output buffer
and output on DATAP and DATAN. The ID signal,
generated from the difference between 2 signals, (A
+ B) and (C + D), is converted to a difference signal
by a differential output buffer and output on CAPAP
and CAPAN. The data signal (DATAP, DATAN) and
ID signal (CAPAP, CAPAN) DC components are
removed using output stage capacitive networks.
T1, T2, T3 and T4 have a hold function to provide
the appropriate reverse bias required by the tracking
PD to ensure the data read bandwidth.
NIPPON PRECISION CIRCUITS—11
SM9103M
Tracking Signal Processor
The tracking stage generates the push-pull tracking
error signal and output signal for DPD servo, as well
as a push-pull sum signal used as an auxiliary signal.
The [(A + B) − (C + D)] signal from the common-data front-end amplifier and signal processor
block is sent to the gain switching block. The gain
switching block amplifies the difference signal using
one of 16 preset gain settings in 2 dB steps to form a
push-pull signal output on TSUB. A feedback resistor connected to TSUBB is used to ensure gain setting stability. The gain of the gain switching block is
controlled by serial interface control bits as shown in
table 2.
Each signal from T1, T2, T3, T4 is buffered and then
output on DPDA, DPDB, DPDC, DPDD, respectively, for DPD servos.
The auxiliary signal is generated from the push-pull
sum signal (A + B + C + D). This signal is buffered
(TAB) and output on TADD. A feedback resistor
connected to TADDB is used to ensure gain setting
stability.
Table 2. TSUB gain setting
TG3
TG2
TG1
TG0
Gain (dB)1
0
0
0
0
+14
0
0
0
1
+12
0
0
1
0
+10
0
0
1
1
+8
0
1
0
0
+6
0
1
0
1
+4
0
1
1
0
+2
0
1
1
1
0
1
0
0
0
−2
1
0
0
1
−4
1
0
1
0
−6
1
0
1
1
−8
1
1
0
0
−10
1
1
0
1
−12
1
1
1
0
−14
1
1
1
1
−16
1. Default is 0 dB
Focus Signal Processor
The focus stage generates the focus error signal from
the focus PD, and a sum signal. The weak focus PD
current signals (F1, F2) are input to the front-end
amplifier and then current-to-voltage converted at
fixed gain.
The front-end amplifier output is sent to the signal
processor block where the focus error signal (F1 −
F2) and the sum signal (F1 + F2) are generated.
The focus error signal is sent to the gain switching
block. The gain switching block amplifies the difference signal using one of 16 preset gain settings in 2
dB steps with output on FSUB. A feedback resistor
connected to FSUBB is used to ensure gain setting
stability. The gain of the gain switching block is controlled by serial interface control bits as shown in
table 3.
The sum is buffered and output on FADD. A feedback resistor connected to FADDB is used to ensure
gain setting stability.
Table 3. FSUB gain setting
FG3
FG2
FG1
FG0
Gain (dB)1
0
0
0
0
+14
0
0
0
1
+12
0
0
1
0
+10
0
0
1
1
+8
0
1
0
0
+6
0
1
0
1
+4
0
1
1
0
+2
0
1
1
1
0
1
0
0
0
−2
1
0
0
1
−4
1
0
1
0
−6
1
0
1
1
−8
1
1
0
0
−10
1
1
0
1
−12
1
1
1
0
−14
1
1
1
1
−16
1. Default is 0 dB
NIPPON PRECISION CIRCUITS—12
SM9103M
Offset Correction
The SM9103M has built-in offset correction circuits
for tracking and focus. During offset correction, the
internal the device operates in RAM read mode, and
FSUB and TSUB operate at maximum gain
(+14 dB). The outputs on FSUB, FADD and TSUB
are indeterminate. Also, inputs T1, T2, T3, T4 and
F1, F2 may be ignored. After correction is complete,
the FSUB and TSUB gain settings return to their
default values (0 dB).
Offset correction is performed under the following
conditions:
■
■
■
■
When power is applied.
When the supply drops below 2.8 ± 0.9 V and then
rises to above 3.8 ± 0.6 V.
When sleep mode operation is cancelled.
When the serial interface bit CS1 is 1. Note that if
SL1 is also 1, then SL1 has priority.
Table 4. Offset correction setting
CS1
Offset correction1
0
No correction
1
Correction
1. Default is No correction
If the voltage falls below 2.8 ± 0.9 V during offset
correction, then correction stops and does not restart
until the supply recovers to above 3.8 ± 0.6 V.
During offset correction, the CALREQ output is held
HIGH. CALREQ goes LOW after correction stops.
The SM9103M also incorporates a temperature
detect function which detects temperature changes of
20 ± 5 °C from the time the initial correction is performed. If a temperature change is detected, CALREQ goes HIGH and the device waits for an offset
correction instruction.
Note that when both WRITE and MODE are HIGH,
offset correction is inactive and the output appears
uncorrected. However, if a correction start condition
occurs when correction is inactive, such as the correction flag CS1 set to 1, then correction operation is
initiated internally but does not appear at the output
unless correction is activated prior to correction
operation finishing.
Once correction has been made inactive, the output
remains uncorrected even if correction is subsequently reactivated. In this case, the output remains
uncorrected until a valid correction start condition is
detected.
Sleep Mode
The SM9103M features a sleep mode which can be
used when the device is not operating to significantly
reduce current consumption. The sleep mode is controlled by serial interface bit SL1.
Table 5. Sleep mode settings
SL1
Sleep mode1
Mode description
LOW
OFF
Normal operation
HIGH
ON
Sleep condition
1. Default is OFF
Preset Function
When power is applied or after offset correction, all
serial interface flags are reset to their default values.
Flags TG3 to TG0 and FG3 to FG0 are also set to
their default values in sleep mode.
NIPPON PRECISION CIRCUITS—13
SM9103M
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9806AE
1998.12
NIPPON PRECISION CIRCUITS—14