SM8750AV
Data Jitter Measurement IC
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
The SM8750AV is a data jitter measurement CMOS LSI for adaptive control.
FEATURES
■
■
■
■
1
16
DATA
CALMON
RDCLK
LIMIT
SENB
RDUTY
RDATAF
RDATAR
SDATA
Optical disc equipment
• CD-R
• CD-RW
• DVD-RAM
• Others
Control/governing equipment
GND
PACKAGE DIMENSIONS
ORDERING INFORMATION
D e vice
P ackag e
S M 8 7 5 0 AV
16-pin V S O P
Unit: mm
+ 0.10
0.15 − 0.
05
4.4 ± 0.2
■
RCP
9
8
0.275typ
5.1 ± 0.2
0.65
1.15 ± 0.1
■
VREF2
SCLK
APPLICATIONS
VDD
TVOUT
875 0 A V
■
START
0.5 ± 0.2
■
Top view
6.4 ± 0.2
■
RDCLK and DATA signal phase difference to
voltage converter (75mV/ns (typ) coefficient)
RDCLK duty auto-adjust function (rising edge
reference)
DATA signal delay auto-adjust function (independently adjusted on rising and falling edges)
Offset auto-calibration function
3-wire serial interface mode control
Sleep function
Single 5V supply
16-pin VSOP
0.10 ± 0.05
■
PINOUT
0 to 10
0.10
+ 0.1
0.22 − 0.05
0.12 M
NIPPON PRECISION CIRCUITS—1
SM8750AV
BLOCK DIAGRAM
DATA START VDD TVOUT
VDD
47k
CALMON
Phase comparator
Charge pump
output buffer
(phase difference to
voltage converter)
Automatic regulation
controller
Duty correction
VREF2
RCP
33k
RDUTY
22k
RDCLK
to each block
LIMIT
SENB
Delay correction
RDATAF
Serial interface
39k
SCLK SDATA GND
RDATAR
39k
PIN DESCRIPTION
Number
Name
I/O
Description
1
S TA R T
I
Measurement star t control. Phase difference to voltage conversion starts on the falling edge.
2
D ATA
I
Tw o-valued signal input
3
CALMON
O
Internal calibration state signal monitor output. N-channel open drain. Active when calibrated.
4
RDCLK
I
PLL clock input
5
LIMIT
I
T VOUT output voltage-limit control voltage input
6
SENB
I
Serial interface: enable signal input
7
SCLK
I
Serial interface: clock signal input
8
S D ATA
I/O
9
GND
–
Ground
10
R D ATA R
O
D ATA rising edge: delay adjust circuit reference-current setting resistor connection
11
R D ATA F
O
D ATA falling edge: delay adjust circuit reference-current setting resistor connection
12
RDUTY
O
RDCLK duty adjust circuit reference-current setting resistor connection
13
RCP
O
Phase difference to voltage converter coefficient reference-current setting resistor connection
14
VREF2
I
2V reference voltage input
15
T VO U T
O
Phase difference to voltage converter output
16
VDD
–
5V supply
Serial interface: data signal input/acknowledge signal output. N-channel open drain.
NIPPON PRECISION CIRCUITS—2
SM8750AV
SPECIFICATIONS
Absolute Maximum Ratings
GND = 0V
P arameter
Symbol
Rating
Unit
Supply voltage range
VDD
−0.5 to 7.0
V
Input voltage range
V IN
−0.5 to V D D + 0.5
V
Storage temperature range
T stg
−40 to 125
°C
Pow er dissipation
PD
250
mW
Symbol
Rating
Unit
Supply voltage (specifications guaranteed)
VDD
4.75 to 5.25
V
Supply voltage (operation guaranteed)
VDD
4.5 to 5.5
V
VREF2
1.89 to 2.11
V
T opr
0 to 70
°C
Recommended Operating Conditions
GND = 0V
P arameter
Reference voltage input
Operating temperature range
DC Electrical Characteristics
VDD = 5V ± 5%, GND = 0V, Ta = 0 to 70°C
Rating
P arameter
Current consumption 1
Symbol
Condition
Unit
min
typ
max
ID D 1
Nor mal operating mode
–
9.0
13.0
ID D 2
Sleep mode
–
0.5
0.7
mA
HIGH-level logic input voltage 2
V IH
2.4
–
–
V
L O W -level logic input
voltage 2
V IL
–
–
0.6
V
HIGH-level logic input
current 2
IIH
V IN = V D D
–
–
3
µA
L O W -level logic input
current 2
IIL
V IN = G N D
−3
–
–
µA
S D ATA, CALMON logic output voltage
VOL
IO L = 10mA
–
–
1.0
V
VREF2 input current
IR E F
VRFE2 = 2V
–
50
100
µA
1. 39k Ω resistor connected betwe e n R DATA R a n d G N D
39k Ω resistor connected betwe e n R DATA F a n d G N D
22k Ω resistor connected betwe e n R D U T Y a n d G N D
33k Ω resistor connected betwe e n R C P a n d G N D
60MHz RDCLK input frequency
7.5MHz DATA input frequency
200kHz STA R T input frequency
0ns DATA and RDCLK phase difference
Serial interface not operating.
2. Pins STA R T, DATA , R D C L K , S E N B, SCLK, SDATA.
NIPPON PRECISION CIRCUITS—3
SM8750AV
Phase Difference to Voltage Converter Characteristics
VDD = 5V ± 5%, GND = 0V, Ta = 0 to 70°C
Rating
P arameter
Condition
Unit
min
typ
max
F C G = L OW
–
58.38
70
FCG = HIGH
–
29.19
35
Nor mal operation, FCG = L O W
50
75
100
C o n verter coefficient measurement mode,
FCG = LOW
25
37.5
50
Nor mal operation, FCG = H I G H
25
37.5
50
12.5
18.75
25
mV/ns
RDCLK input frequency
Phase difference to voltage converter
coefficient 1
Phase difference to voltage converter
coefficient 2
MHz
mV/ns
mV/ns
Phase difference to voltage converter
coefficient 3
C o n verter coefficient measurement mode,
FCG = HIGH
C o n verter coefficient relative accuracy
See note.1
–
–
±5
%
C o n verter coefficient relative accuracy
See
note.2
–
–
±5
%
Output offset voltage
After VREF2 reference calibration
–
–
±25
mV
C o n verter voltage settling time
Time from measurement object DATA
edge to final set value ± 0.5%
–
–
0.75
µs
C o n verter voltage reset time
Time from STA R T signal rising edge to
final reset value ± 1mV
–
–
3
µs
Output load regulation
IL = 0.5mA
–
–
20
mV
HIGH-level output voltage range
LIMIT pin voltage reference
+0.15
–
+0.45
V
0.8
–
–
V
–
–
1
mV/µs
1T
–
–
ns
L O W -level output voltage range
Output voltage droop
S TA R T-DATA setup time 3
S TA R T signal rising edge to DATA signal
edge
1. {[(converter coefficient 2) × 2 / (converter coefficient 1)] − 1} × 100
2. {[(converter coefficient 3) × 2 / (converter coefficient 2)] − 1} × 100
3. T = RDCLK cycle time
Auto-adjust Characteristics
VDD = 5V ± 5%, GND = 0V, Ta = 0 to 70°C
Rating
P arameter
Condition
Unit
min
typ
max
M a x i m u m DATA edge delay adjust range
–
29
–
ns
Minimu m DATA edge delay adjust range
–
12.5
–
ns
–
15
–
ns
–
3
–
ns
–
28
–
ns
–
4
–
ns
M a x i m um RDCLK pulsewidth adjust range
F C G = L OW
Minimum RDCLK pulsewidth adjust range
M a x i m um RDCLK pulsewidth adjust range
FCG = HIGH
Minimum RDCLK pulsewidth adjust range
A uto-adjustment time
After CS = HIGH, until settling
–
5
8
ms
R C P voltage
C o n verter coefficients set
–
1
–
V
HIGH-level RDATA R / R DATAF voltage
Minimu m DATA delay
–
1.92
–
V
L O W -level RDATA R / R DATAF voltage
M a x i m u m DATA delay
–
0.69
–
V
HIGH-level RDUTY voltage
Minimum RDCLK pulsewidth
–
1.88
–
V
L O W -level RDUTY voltage
M a x i m um RDCLK pulsewidth
–
0.24
–
V
NIPPON PRECISION CIRCUITS—4
SM8750AV
Serial Interface Characteristics
Rating
P arameter
Symbol
Unit
min
typ
max
SCLK pulse cycle time
tc y S C K
100
–
–
ns
SCLK HIGH-level pulsewidth
tw h S C K
40
–
–
ns
S C L K L OW -level pulsewidth
tw l S C K
40
–
–
ns
SENB setup time
ts S E N
20
–
–
ns
SENB hold time
th S E N
40
–
–
ns
S D ATA setup time
ts S DA
15
–
–
ns
S D ATA hold time
th S D A
15
–
–
ns
time 1
ts AC K
0
–
20
ns
th AC K
–
–
50
ns
ti n S E N
100
–
–
ns
A CK setup
A CK hold
time 1
SENB inter val
1. S D ATA output signal (ACK) acknowledge output (N-channel open drain), receive data is valid, LOW -level output, 15pF SDATA load capacitance.
tinSEN
SENB
tsSEN
twhSCK
twlSCK
tcySCK
thSEN
SCLOCK
tsSDA
SDATA
Controller
SDATA port
bit0
LSB
thSDA
tsACK
bit1
bit15
MSB
thACK
ACK
High impedance
NIPPON PRECISION CIRCUITS—5
SM8750AV
FUNCTIONAL DESCRIPTION
Serial Interface
The SM8750AV has a dedicated serial interface port
over which data can be written and the various operating modes can be controlled. The port address and
bit configuration are shown in table 1, and the data
bits are described in table 2.
Table 1. Port address and bit configuration
Bit nu m b e r
15
(msb)
14
13
12
11
10
9
8
7
6
5
Data
TEST1 TEST0 CSDIS
CS
3
2
1
0
(lsb)
HIGH
HIGH
HIGH
×
4
Address
SP
POLAR GMES
FCG
×
LOW
HIGH
HIGH
×: Don’t care.
Table 2. Data bit description
Bit
Description
Default
TEST[1:0]
Test mode setting
L OW:LOW
CSDIS
A uto-adjust disable
LOW
(enabled)
CS
A uto-adjust start
LOW
(wait)
SP
Sleep mode settings
LOW
(normal operation)
POLAR
D ATA edge settings for phase measurement
Polarity setting for converter coefficient measurement
LOW
(falling edge)
(1T discharge)
GMES
C o n verter coefficient measurement mode setting
LOW
(normal operation)
RDCLK pulsewidth auto-adjust mode
Phase difference to voltage converter coefficient switching
LOW
(minimum pulsewidth)
(maximum converter coefficient)
FCG
(normal operation)
Table 3. GMES and POLAR operating modes
GMES
POLAR
Operating mode
LOW
LOW
D ATA signal falling edge and RDCLK rising edge phase difference conversion
LOW
HIGH
D ATA signal rising edge and RDCLK rising edge phase difference conversion
HIGH
LOW
Output converter voltage for phase difference equivalent to −0.5T
HIGH
HIGH
Output converter voltage for phase difference equivalent to +0.5T
Serial data comprising 16 bits is input with the LSB
first. Valid data is read in on the 16th rising edge of
the SCLK input. On the next SCLK falling edge, the
SDATA N-channel open drain is turned ON and
SDATA goes LOW, performing the function of an
acknowledge signal.
If 15 or less SCLK rising edge pulses occur during
the interval when SENB is HIGH, the data received
up to the point when SENB goes LOW is ignored
and the internal port data is not updated. If 17 or
more SCLK rising edge pulses occur, the received
data is latched in the internal port on the 16th rising
edge and the acknowledge signal is output on the
next falling edge. The acknowledge signal is held
constant until SENB goes LOW again.
NIPPON PRECISION CIRCUITS—6
SM8750AV
Phase Difference to Voltage Converter
The phase difference to voltage converter circuit
takes the converts the phase difference between the
RDCLK rising edge and the DATA signal to a voltage. When START goes LOW, the phase difference
between the first active DATA signal edge, where the
active edge polarity is determined by the serial interface bit POLAR, and the next RDCLK rising edge is
converted to a voltage signal. The converted voltage
signal is output on TVOUT while START is LOW,
and is reset to the VREF2 reference level when
START goes HIGH again.
The START signal must go LOW for a minimum
interval of 1 RDCLK cycle before any DATA signal
edge to be converted, regardless of the number of
DATA signal edges. If the START interval is shorter
than 1 cycle, there is a possibility that the next edge
might be misinterpreted as the conversion object.
START
RDCLK
Phase difference
DATA
START−DATA set up time
Internal charge signal
Internal discharge signal
TVOUT output
Conversion voltage
Reset
VREF2
VREF2
Figure 1. Converter operation timing (POLAR = LOW, DATA leading phase)
START
RDCLK
Phase difference
DATA
START−DATA set up time
Internal charge signal
Internal discharge signal
VREF2
TVOUT output
Reset
Conversion voltage
VREF2
Figure 2. Converter operation timing (POLAR = LOW, DATA lagging phase)
NIPPON PRECISION CIRCUITS—7
SM8750AV
Converter Coefficient Measurement Mode
When the serial interface bit GMES is set HIGH,
converter coefficient measurement mode is invoked.
In this mode, a voltage equivalent to a phase difference of ±0.5T, determined by the POLAR input bit,
is output on TVOUT. Internally, the difference in
pulsewidth between the charge/discharge signals is
±1T, where the charge pump circuit capacitance is
double the capacitance during normal operation in
order to generate outputs equivalent to phase differences of ±0.5T.
START
RDCLK
Internal charge signal
Internal discharge signal
Reset
TVOUT output
VREF2
Conversion voltage
(corresponds to −0.5T)
VREF2
Figure 3. Converter coefficient measurement mode timing (POLAR = LOW)
START
RDCLK
Internal charge signal
Internal discharge signal
Conversion voltage
(corresponds to +0.5T)
TVOUT output
VREF2
Reset
VREF2
Figure 4. Converter coefficient measurement mode timing (POLAR = HIGH)
NIPPON PRECISION CIRCUITS—8
SM8750AV
Auto-adjust Function
When the serial interface bit CS is set HIGH, the
auto-adjust function starts and operates on the
objects in the sequence described below. In the autoadjust sequence cycle, the RDCLK pulsewidth and
DATA delay are set to approximately the center of
the adjustment range.
4. DATA falling edge delay
The phase difference between the RDCLK rising
edge and DATA falling edge is converted to a
voltage, and the RDCLK rising edge delay is
adjusted to recover a TVOUT output voltage of
VREF2.
1. Charge pump circuit and output buffer offset
cancellation
An identical 0.5T signal is added to the
charge/discharge signals and the output on
TVOUT is calibrated to an output voltage of
VREF2.
2. RDCLK pulsewidth
Signals equivalent to the RDCLK HIGH-level
pulsewidth and LOW-level pulsewidth are added
to the internal charge/discharge signals, and the
RDCLK pulsewidths are adjusted to recover a
TVOUT output voltage of VREF2.
3. DATA rising edge delay
The phase difference between the RDCLK rising
edge and DATA rising edge is converted to a
voltage, and the RDCLK rising edge delay is
adjusted to recover a TVOUT output voltage of
VREF2.
The CALMON calibration monitor output is high
impedance during the auto-adjust sequence interval.
When auto-adjustment is completed, the CALMON
N-channel open drain turns ON and CALMON goes
LOW, and the CS bit is cleared to LOW.
When the serial interface bit CSDIS is set HIGH, the
auto-adjustment result is disabled, and the external
inputs on RDCLK and DATA are input to the phase
comparator without adjustment. If CS and CSDIS
are both simultaneously set HIGH, the auto-adjust
sequence still takes place but that the result is disabled as soon as the sequence is completed.
When power is switched ON, the auto-adjust
sequence is enabled, and the adjusted values are
approximately in the center of the corresponding
adjustment range.
Sleep Mode
When the serial interface bit SP is set HIGH, sleep
mode is invoked. In this mode, all circuits other than
the power-ON detection circuit and serial interface
circuit are shutdown to reduce current consumption.
When operation transfers from sleep mode to normal
operating mode, the auto-adjust settings from the
most recent auto-adjust cycle are restored.
Power-ON Reset
When power is switched ON, a built-in power-ON
reset circuit sets all serial interface bit settings to
LOW (factory preset default), and the auto-adjust
circuit settings are set to the middle of the corresponding adjustment range.
Test Mode
When the serial interface bit TEST1 or TEST0 is set
HIGH, a test mode is invoked. In these modes, the
phase comparator input signals and internal
charge/discharge signals are output on CALMON
and TVOUT.
Table 4. Test modes
TEST1
TEST0
CALMON
T VO U T
LOW
LOW
Nor mal operation
Nor mal operation
LOW
HIGH
Internal charge signal
Internal discharge signal
HIGH
LOW
Phase comparator RDCLK signal
Phase comparator DATA signal
NIPPON PRECISION CIRCUITS—9
SM8750AV
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9916AE
2000.07
NIPPON PRECISION CIRCUITS—10