NTE1167 Integrated Circuit Phase Lock Loop (PLL) Frequency Synthesizer Description: The NTE1167 consists of a crystal oscillator, 10 bit divider, phase comparator, and a programmable divide–by–N 9–bit counter in a single CMOS 16–Lead DIP type integrated circuit. This device is designed for use in frequency synthesizers and phase locked loop applications for CB transceivers since it includes a reference frequency selector pin. Absolute Maximum Ratings: (TA = +25°C unless otherwise specified) Supply Voltage, VDD – VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS ≤ VIN ≤ VDD Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mW Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +125°C Lead Temperature (During Soldering, 5sec Max), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Electrical Characteristics: (VDD – VSS = 6V, –30° ≤ TA ≤ +70°C, fin Qin = 10.24MHz unless otherwise specified) Parameter Input Voltage (All Inputs) Low Level High Level Pull–Up Resistance Pull–Down Resistance Supply Current Output Voltage High Level Low Level Output Current High Level Low Level Output Voltage Max Input Frequency Max Free Running Frequency Operating Voltage Symbol VIL VIH Test Conditions Typ Max Unit – 5.5 – – 0.5 – V V RUP FS – 2.0 0 MΩ RDN P0 – P8 15 75 – kΩ – 5.0 9.0 mA IOH = 0.1mA IOL = 0.1mA 5.5 0 – – – 0.5 V V ISAT H DO ISAT L DO VO = 0V VO = 0V 400 400 – – – – µA µA VIF Fin VDD = 5V 1.7 2.2 2.8 V VIF FS 5.5 – – V VIF P0 – P8 – – 0.5 V fIN Max Qin 11 – – MHz fIN Max Fin 3.3 – – MHz fFR Max FIN 3.5 – – MHz VDD 5.0 – 6.5 V IDD VOH LD VOL LD Note 1 Min VDD = 5.5V, Vin Fin = 1VP–P, Exclude sink current of preset pin Note 1. All inputs refers to pins P0 to P8, FS, Fin, and Qin. This parameter defins their input levels at DC coupling. Pin Connection Diagram VDD 1 16 VSS PIN 2 15 P0 RIN 3 14 P1 N.C. 4 13 P2 DO 5 12 P3 LD 6 11 P4 P8 7 10 P5 P7 8 9 16 P6 9 .260 (6.6) Max 1 8 .300 (7.62) .785 (19.9) Max .200 (5.08) Max .245 (6.22) Min .100 (2.54) .700 (17.7)