NTE NTE1199

NTE1199
Integrated Circuit
CMOS Frequency Divider
Description:
The NTE1199 is an LSI CMOS circuit in a 24–Lead DIP type package designed for use in frequency
divider applications in CB transceivers. This device contains a prescaler, divider, and binary input
programmable circuitry.
Absolute Maximum Ratings: (TA = +25°C unless otherwise specified)
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +6.0V
Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +6.0V
Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +6.0V
Output Current, IO
Pins 17, 21, 22, 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mA
Pins 13, 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30° to +60°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +125°C
Electrical Characteristics: (VDD = +5V, TA = –30° to +60°C unless otherwise specified)
Parameter
Input Voltage
High Level
Low Level
Output Voltage (Pins 17, 21, 22, 24)
High Level
Low Level
Output Voltage (Pins 13, 19)
High Level
Low Level
Total Current
Symbol
Test Conditions
Min
Typ
Max
Unit
VIH
All Inputs
4.0
–
+VDD
V
VIL
All Inputs
–0.3
–
1.25
V
VOH
IO = –300µA
2.4
–
+VDD
V
VOL
IO = 300µA
–0.3
–
0.4
V
VOH
IO = –4.8mA
2.4
–
+VDD
V
VOL
IO = 4.8mA
–0.3
–
0.4
V
IDD
f=0
–
10
–
mA
See Pulse Definition (Fig. 1)
–
–
5
µs
–
–
5
µs
Count Pulse Rise Time
tr
Count Pulse Fall Time
tf
Input Capacitance (Pins 14, 16, 18)
CI
VI = 0
–
–
10
pF
Frequency Response
fs
Prescaler
10
–
–
MHz
fd
Divider
7
–
–
MHz
fp
Programmable Divider
(Apply Program Table, Fig. 2)
5
–
–
MHz
Pin Connection Diagram
P1 1
P2 2
P3 3
P4 4
P5 5
24
23
22
21
20
Fig. 1 Pulse Definition
D6
GND
D7
D8
VIH
VIH (Min)
M
19 DO
18 DI
17 SO
16 SI
15 C
14 PI
13 PO
P6 6
P7 7
P8 8
P9 9
P10 10
P11 11
VDD 12
VIL (Min)
VIL
tr
tf
Fig. 2 Program Table
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
Pat. 1
1
0
0
1
1
0
0
1
1
1
1
Pat. 2
0
1
1
0
0
1
1
0
0
0
0
Pat. 3
1
1
0
0
0
0
0
0
0
0
0
24
13
1
12
1.300 (33.02)
Max
.520
(13.2)
.225
(5.73)
Max
.100 (2.54)
1.100 (27.94)
.126
(3.22)
Min
.600
(15.24)