SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS041B – DECEMBER 1982 – REVISED MAY 1997 SN54HC595 . . . J OR W PACKAGE SN74HC595 . . . D OR N PACKAGE (TOP VIEW) QB QC QD QE QF QG QH GND description Both the shift register clock (RCLK) and storage register clock (SRCLK) are positive-edge triggered. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. The SN54HC595 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HC595 is characterized for operation from –40°C to 85°C. 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER OE RCLK SRCLK SRCLR QH′ QC QB NC VCC QA SN54HC595 . . . FK PACKAGE (TOP VIEW) QD QE NC QF QG 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QH The ’HC595 contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. 1 SER OE NC RCLK SRCLK SRCLR D D 8-Bit Serial-In, Parallel-Out Shift High-Current 3-State Outputs Can Drive up to 15 LSTTL Loads Shift Register Has Direct Clear Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs GND NC Q H′ D D NC – No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS041B – DECEMBER 1982 – REVISED MAY 1997 logic symbol† 13 OE RCLK 12 10 SRCLR SRCLK SER 11 EN3 C2 SRG8 R C1/ 14 15 1D 2D 3 1 2 3 4 5 6 2D 3 7 9 QA QB QC QD QE QF QG QH QH′ † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS041B – DECEMBER 1982 – REVISED MAY 1997 logic diagram (positive logic) OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D C1 R 3R C3 3S 15 2S 2R C2 R 3R C3 3S 1 2S 2R C2 R 3R C3 3S 2 2S 2R C2 R 3R C3 3S 3 2S 2R C2 R 3R C3 3S 4 2S 2R C2 R 3R C3 3S 5 2S 2R C2 R 3R C3 3S 6 2S 2R C2 R 3R C3 3S 7 9 QA QB QC QD QE QF QG QH QH′ Pin numbers shown are for the D, J, N, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS041B – DECEMBER 1982 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions SN54HC595 VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL Low-level input voltage VI VO Input voltage Output voltage tt‡ Input transition (rise and fall) time SN74HC595 MIN NOM MAX MIN NOM MAX 2 5 6 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 V V 0 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC 0 VCC VCC VCC = 2 V VCC = 4.5 V 0 1000 0 1000 0 500 0 500 VCC = 6 V 0 400 0 400 VCC = 4.5 V VCC = 6 V UNIT V V V ns TA Operating free-air temperature –55 125 –40 85 °C ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS041B – DECEMBER 1982 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –20 µA VOH VI = VIH or VIL QH′, IOH = –4 mA QA–QH, IOH = –6 mA QH′, IOH = –5.2 mA QA–QH, IOH = –7.8 mA IOL = 20 µA VOL VI = VIH or VIL QH′, IOL = 4 mA QA–QH, IOL = 6 mA QH′, IOL = 5.2 mA QA–QH, IOL = 7.8 mA II IOZ VI = VCC or 0 VO = VCC or 0 ICC VI = VCC or 0, Ci IO = 0 VCC MIN TA = 25°C TYP MAX SN54HC595 MIN MAX SN74HC595 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 3.98 4.3 3.7 3.84 3.98 4.3 3.7 3.84 5.48 5.8 5.2 5.34 45V 4.5 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 0.17 0.26 0.4 0.33 0.15 0.26 0.4 0.33 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 6V ±0.01 ±0.5 ±10 ±5 µA 8 160 80 µA 10 10 10 pF 45V 4.5 6V 6V 2V to 6 V POST OFFICE BOX 655303 3 • DALLAS, TEXAS 75265 V 5 SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS041B – DECEMBER 1982 – REVISED MAY 1997 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency SRCLK or RCLK high or low tw Pulse duration SRCLR low SER before SRCLK↑ ↑ SRCLK↑ ↑ before RCLK↑ ↑† tsu Setup time SRCLR low before RCLK↑ ↑ SRCLR high (inactive) before SRCLK↑ ↑ th Hold time, SER after SRCLK↑ ↑ TA = 25°C MIN MAX SN54HC595 SN74HC595 MIN MAX MIN MAX 2V 0 6 0 4.2 0 5 4.5 V 0 31 0 21 0 25 6V 0 36 0 25 0 29 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 75 113 94 4.5 V 15 23 19 6V 13 19 16 2V 50 75 65 4.5 V 10 15 13 6V 9 13 11 2V 50 75 60 4.5 V 10 15 12 6V 9 13 11 2V 0 0 0 4.5 V 0 0 0 UNIT MHz ns ns ns 6V 0 0 0 † This setup time ensures the output register sees stable data from the shift-register outputs. The clocks may be tied together, in which case the output register is one clock pulse behind the shift register. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS041B – DECEMBER 1982 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax SRCLK QH′ tpd d RCLK tPHL ten SRCLR OE tdis OE QA–QH QH′ QA–QH QA–QH QA–QH tt QH′ VCC MIN TA = 25°C TYP MAX SN54HC595 MIN MAX SN74HC595 MIN 2V 6 26 4.2 5 4.5 V 31 38 21 25 6V 36 42 25 29 MAX UNIT MHz 2V 50 160 240 200 4.5 V 17 32 48 40 6V 14 27 41 34 2V 50 150 225 187 4.5 V 17 30 45 37 6V 14 26 38 32 2V 51 175 261 219 4.5 V 18 35 52 44 6V 15 30 44 37 2V 40 150 225 187 4.5 V 15 30 45 37 6V 13 26 38 32 2V 42 200 300 250 4.5 V 23 40 60 50 6V 20 34 51 43 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 2V 28 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 ns ns ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd ten FROM (INPUT) RCLK OE tt TO (OUTPUT) QA–QH QA–QH QA–QH VCC MIN TA = 25°C TYP MAX SN54HC595 MIN MAX SN74HC595 MIN MAX 2V 60 200 300 250 4.5 V 22 40 60 50 6V 19 34 51 43 2V 70 200 298 250 4.5 V 23 40 60 50 6V 19 34 51 43 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 UNIT ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TEST CONDITIONS TYP UNIT No load 400 pF 7 SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS041B – DECEMBER 1982 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test CL (see Note A) PARAMETER S1 Test Point tPZH ten RL 1 kΩ tPZL tPHZ tdis S2 RL 1 kΩ Data Input VCC 50% 10% 50% 50% 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% tf Closed Closed Open Open Open VCC th 90% 90% VCC 50% 10% 0 V tf 50% 10% Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL VOH 50% 10% V OL tf Output Waveform 1 (See Note B) tPLZ ≈ VCC ≈ VCC 50% 10% VOL tPZH tPLH 50% 10% Open VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VCC tPLH Open tr VOLTAGE WAVEFORMS PULSE DURATIONS 50% Closed 0V 0V Input Closed tsu 0V 50% Open 50% 50% tw Low-Level Pulse 50 pF or 150 pF 50 pF or 150 pF –– Reference Input VCC S2 50 pF LOAD CIRCUIT 50% S1 tPLZ tpd or tt High-Level Pulse CL 90% VOH VOL Output Waveform 2 (See Note B) tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% 90% VOH ≈0V tPHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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