SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS SCLS117B – DECEMBER 1982 – REVISED MAY 1997 description The ’HC166 parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift / load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero. SN54HC166 . . . J OR W PACKAGE SN74HC166 . . . D OR N PACKAGE (TOP VIEW) SER A B C D CLK INH CLK GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC SH/LD H QH G F E CLR SN54HC166 . . . FK PACKAGE (TOP VIEW) A SER NC VCC SH/LD Synchronous Load Direct Overriding Clear Parallel-to-Serial Conversion Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs B C NC D CLK INH 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 H QH NC G F CLK GND NC CLR E D D D D NC – No internal connection The SN54HC166 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HC166 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS SCLS117B – DECEMBER 1982 – REVISED MAY 1997 FUNCTION TABLE OUTPUTS INPUTS INTERNAL CLR SH/LD CLK INH CLK SER PARALLEL A...H QA QB L X X X X X L L L H X L L X X QA0 QB0 QH0 H L L ↑ X a...h a b h H H L ↑ H X H QAn QGn H H L ↑ L X L QAn QGn H X H ↑ X X QA0 QB0 QH0 logic symbol† CLR 9 R 15 SH/LD CLK INH CLK SER A B C D E F G H 6 SRG8 M1 [Shift] M2 [Load] ≥1 7 1 C3/1 1, 3D 2 2, 3D 3 2, 3D 4 5 10 11 12 14 13 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages. 2 QH POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QH SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS SCLS117B – DECEMBER 1982 – REVISED MAY 1997 logic diagram (positive logic) A SH/LD SER B 2 15 C D 3 4 1D C1 R 1D C1 R E F G H 5 10 11 12 14 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1 CLK INH CLK CLR 1D C1 R 6 7 9 13 QH Pin numbers shown are for the D, J, N, and W packages. typical clear, shift, load, inhibit, and shift sequence CLK CLK INH CLR SER SH/LD Parallel Inputs A H B L C H D L E H F L G H H H QH Serial Shift Clear H Inhibit H L H L H L H Serial Shift Load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS SCLS117B – DECEMBER 1982 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions SN54HC166 VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL Low-level input voltage VI VO Input voltage Output voltage tt‡ Input transition (rise and fall) time SN74HC166 MIN NOM MAX MIN NOM MAX 2 5 6 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 V V 0 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC 0 VCC VCC VCC = 2 V VCC = 4.5 V 0 1000 0 1000 0 500 0 500 VCC = 6 V 0 400 0 400 VCC = 4.5 V VCC = 6 V UNIT V V V ns TA Operating free-air temperature –55 125 –40 85 °C ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS SCLS117B – DECEMBER 1982 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –20 µA VOH VI = VIH or VIL IOH = –4 mA IOH = –5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 VCC MIN TA = 25°C TYP MAX SN54HC166 MIN MAX SN74HC166 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 3 10 10 10 pF 6V 2 V to 6 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 5 SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS SCLS117B – DECEMBER 1982 – REVISED MAY 1997 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CLR low tw Pulse duration CLK high or low SH/LD high before CLK↑ ↑ SER before CLK↑ ↑ tsu Setup time CLK INH low before CLK↑ ↑ Data before CLK↑ ↑ CLR inactive before CLK↑ ↑ SH/LD high after CLK↑ ↑ SER after CLK↑ ↑ th Hold time CLK INH high after CLK↑ ↑ Data after CLK↑ ↑ 6 POST OFFICE BOX 655303 TA = 25°C MIN MAX SN54HC166 SN74HC166 MIN MAX MIN MAX 2V 0 6 0 4.2 0 5 4.5 V 0 31 0 21 0 25 6V 0 36 0 25 0 29 2V 100 150 125 4.5 V 20 30 25 6V 17 26 21 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 145 220 180 4.5 V 29 44 36 6V 25 38 31 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 100 150 125 4.5 V 20 30 25 6V 17 26 21 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 40 60 50 4.5 V 8 12 10 6V 7 10 9 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 • DALLAS, TEXAS 75265 UNIT MHz ns ns ns SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS SCLS117B – DECEMBER 1982 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPHL tpd CLR CLK tt QH QH Any VCC MIN TA = 25°C TYP MAX SN54HC166 MIN MAX SN74HC166 MIN 2V 6 11 4.2 5 4.5 V 31 36 21 25 6V 36 45 25 29 MAX UNIT MHz 2V 62 120 180 150 4.5 V 18 24 36 30 6V 13 20 31 26 2V 75 150 225 190 4.5 V 15 30 45 38 6V 13 26 38 32 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 50 UNIT pF 7 SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS SCLS117B – DECEMBER 1982 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated