NTE937M Integrated Circuit JFET Input Operational Amplifier Description: The NTE937M is a monolithic JFET input operational amplifier in an 8–Lead DIP type package incorporating well–matched, high voltage JFET’s on the same chip with standard bi–polar transistors. This amplifier features low input bias and offset currents, low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common–mode rejection. It is also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner. Advantages: D Replaces Expensive Hybrid and Module FET OP Amps D Rugged JFET’s Allow Blow–Out Free Handling Compared with MOSFET Input Device D Excellent for Low Noise Applications using either High or Low Source Impedance – Very Low 1/f Corner D Offset Adjust does not Degrade Drift or Common–Mode Rejection as in Most Monolithic Amplifiers D New Output Stage Allows use of Large Capacitive Loads (10,000pF) without Stability Problems D Internal Compensation and Large Differential Input Voltage Capability Applications: D Precision High Speed Integrators D Fast D/A and A/D Converters D High Impedance Buffers D Wideband, Low Noise, Low Drift Amplifiers D Logarithmic Amplifiers D Photocell Amplifiers D Sample and Hold Circuits Absolute Maximum Ratings: Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V Maximum Power Dissipation (at +25°C, Note 1), Pd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30V Input Voltage Range (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16V Output Short–Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Maximum Operating Junction Temperature (Note 1), TJmax . . . . . . . . . . . . . . . . . . . . . . . . . . +100°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C Thermal Resistance, Junction–to–Ambient (Note 1), RthJC . . . . . . . . . . . . . . . . . . . . . . . . . +155°C/W Note 1. The maximum power dissipation for this device must be derated at elevated temperatures and is dictated by TJmax, RthJC, and the ambient temperature, TA. The maximum available power dissipation at any temperature is Pd = (TJmax – TA)/RthJC or the +25°C Pdmax, whichever is less. Note 2. Unless otherwise specified, the absolute maximum negative input voltage is equal to the negative power supply voltage. DC Electrical Characteristics: (TA = +25C, VS = ±15V unless otherwise specified) Parameter Supply Current Symbol Test Conditions ICC Min Typ Max Unit – 5 10 mA DC Electrical Characteristics: (VS = ±15V, 0° ≤ TA ≤ +70°C, THIGH = +70°C unles otherwise specified) Parameter Min Typ Max Unit RS = 50Ω, TA = +25°C – 3 10 mV Over Temperature – – 13 mV RS = 50Ω – 5 – µV/°C – 0.5 – µV/°C TJ = +25°C, Note 4 – 3 50 pA TJ ≤ THIGH – – 2 nA TJ = +25°C, Note 4 – 30 200 pA TJ ≤ THIGH – – 8 nA TJ = +25°C – 1012 – Ω TA = +25°C, VO = ±10V, RL = 2k 25 200 – V/mV Over Temperature 15 – – V/mV RL = 10k ±12 ±13 – V RL = 2k ±10 ±12 – V VCM ±10 +15.1 –12 – V Common–Mode Rejection Ratio CMRR – 80 100 dB Supply Voltage Rejection Ratio PSRR – 80 100 dB Input Offset Voltage Symbol VOS Test Conditions Average TC of Input Offset Voltage ∆VOS/∆T Change in Average TC with VOS Adjust ∆TC/∆VOS RS = 50Ω, Note 3 Input Offset Current Input Bias Current Input Resistance Large Signal Voltage Gain Output Voltage Swing Input Common–Mode Voltage Range IOS IB RIN AVOL VO Note 5 Note 3. The temperature coeficient of the adjust input offset voltage changes only a small amount (0.5µV/°C typically) for each mV of adjustment from its original unadjusted value. Common– mode rejection and open loop voltage gain are also unaffected by offset adjustment. Note 4. The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature, TJ. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ = TA + RthJC Pd where RthJC is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 5. Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice. AC Electrical Characteristics: (TA = +25C, VS = ±15V unless otherwise specified) Parameter Symbol Slew Rate SR Gain Bandwidth Product Test Conditions Min Typ Max Unit 30 50 – V/µs – 20 – MHz – 1.5 – µs f = 100Hz – 15 – nV/√Hz f = 1000Hz – 12 – nV/√Hz f = 100Hz – 0.01 – pA/√Hz f = 1000Hz – 0.01 – pA/√Hz – 3 – pF AV = 5 GBW Settling Time to 0.01% ts Note 6 Equivalent Input Noise Voltage eN RS = 100Ω Equivalent Input Current Noise iN Input Capacitance CIN Note 6. AV = –5, the feedback resistor from output to input is 2kΩ and the output step is 10V. Pin Connection Diagram Offset Null 1 8 Inverting Input 2 N.C. 7 VCC Non–Inverting Input 3 6 Output VEE 4 5 Offset Null 8 5 .260 (6.6) 1 4 .390 (9.9) Max .300 (7.62) .155 (3.93) .100 (2.54) .145 (3.68) .300 (7.62)