Pr E2G1057-29-41 el im y 4-Bank ¥ 524,288-Word ¥ 32-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MD56V62320 is a 4-bank ¥ 524,288-word ¥ 32-bit synchronous dynamic RAM, fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES • • • • • • • Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 4-bank ¥ 524,288-word ¥ 32-bit configuration 3.3 V power supply, ±0.3 V tolerance Input : LVTTL compatible Output : LVTTL compatible Refresh : 4096 cycles/64 ms Programmable data transfer mode – CAS latency (2, 3) – Burst length (2, 4, 8) – Data scramble (sequential, interleave) • CBR auto-refresh, Self-refresh capability • Package: 86-pin 400 mil plastic TSOP (Type II) (TSOPII86-P-400-0.50-K) (Product : MD56V62320-xxTA) xx indicates speed rank. PRODUCT FAMILY Family MD56V62320-10 Max. Frequency 100 MHz Access Time (Max.) tAC2 tAC3 9 ns 9 ns ar This version: Apr. 1999 MD56V62320 in ¡ Semiconductor MD56V62320 ¡ Semiconductor 1/29 ¡ Semiconductor MD56V62320 PIN CONFIGURATION (TOP VIEW) VCC DQ1 VCCQ DQ2 DQ3 VSSQ DQ4 DQ5 VCCQ DQ6 DQ7 VSSQ DQ8 NC VCC DQM0 WE CAS RAS CS NC BA0 BA1 A10 A0 A1 A2 DQM2 VCC NC DQ17 VSSQ DQ18 DQ19 VCCQ DQ20 DQ21 VSSQ DQ22 DQ23 VCCQ DQ24 VCC 1 86 VSS 2 85 DQ16 3 84 VSSQ 4 83 DQ15 5 82 DQ14 6 81 VCCQ 7 80 DQ13 8 79 DQ12 9 78 VSSQ 10 77 DQ11 11 76 DQ10 12 75 VCCQ 13 74 DQ9 14 73 NC 15 72 VSS 16 71 DQM1 17 70 NC 18 69 NC 19 68 CLK 20 67 CKE 21 66 A9 22 65 A8 23 64 A7 24 63 A6 25 62 A5 26 61 A4 27 60 A3 28 59 DQM3 29 58 VSS 30 57 NC 31 56 DQ32 32 55 VCCQ 33 54 DQ31 34 53 DQ30 35 52 VSSQ 36 51 DQ29 37 50 DQ28 38 49 VCCQ 39 48 DQ27 40 47 DQ26 41 46 VSSQ 42 45 DQ25 43 44 VSS 86-Pin Plastic TSOP (II) (K Type) Pin Name Note: Function Pin Name Function CLK System Clock DQM0 - 3 Data Input/Output Mask CS Chip Select DQi Data Input/Output CKE Clock Enable VCC Power Supply (3.3 V) A0 - A10 Address VSS Ground (0 V) BA0, BA1 Bank Select Address VCCQ Data Output Power Supply (3.3 V) RAS Row Address Strobe VSSQ Data Output Ground (0 V) CAS Column Address Strobe NC No Connection WE Write Enable The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/29 ¡ Semiconductor MD56V62320 PIN DESCRIPTION CLK Fetches all inputs at the "H" edge. CS Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQM0 - 3. CKE Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address: RA0 - RA10 Column address: CA0 - CA7 BA0, BA1 Bank Access pins. These pins are dedicated to select one of 4 banks. RAS CAS Functionality depends on the combination. For details, see the function truth table. WE DQM0 - 3 DQM0 controls DQ1 - 8. DQM1 controls DQ9 - 16. DQM2 controls DQ17 - 24. DQM3 controls DQ25 - 32. DQi Data inputs/outputs are multiplexed on the same pin. 3/29 ¡ Semiconductor MD56V62320 BLOCK DIAGRAM CKE CS RAS CAS WE DQM0 - DQM3 A0 - A10 BA0, BA1 CLOCK BUFFER Row Address Latches & Refresh Counter Command Decoding Logic Command Buffers Address Buffers Row Decoders Control Logic Mode Register Word Drivers Column Address Latches & Counter Latency & Burst controller Column Decoders Sense Amplifiers CLK Memory Cells BANK A BANK B BANK C BANK D Input Buffers Input Data Register Output Buffers Output Data Register DQ1 - DQ32 4/29 ¡ Semiconductor MD56V62320 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (Voltages referenced to VSS) Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT –0.5 to VCC + 0.5 V VCC Supply Voltage VCC, VCCQ –0.5 to 4.6 V Storage Temperature Tstg –55 to 150 °C Power Dissipation PD* 1 W Short Circuit Current IOS 50 mA Operating Temperature Topr 0 to 70 °C *: Ta = 25°C Recommended Operating Conditions (Voltages referenced to VSS = 0 V) Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage VCC, VCCQ 3.0 3.3 3.6 V Input High Voltage VIH 2.0 — VCC + 0.3 V Input Low Voltage VIL –0.3 — 0.8 V Capacitance (VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) Parameter Input Capacitance (ADDR) Input Capacitance (CLK, CKE, CS, RAS, CAS, WE, DQM0 - 3) Input/Output Capacitance (DQ1 - DQ32) Symbol Min. Max. Unit CIN1 2 5 pF CIN2 2 5 pF COUT 2 7 pF 5/29 ¡ Semiconductor MD56V62320 DC Characteristics Condition Parameter Symbol CKE Others Output High Voltage VOH — Output Low Voltage VOL Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) ICC1 Power Supply Current (Stand by) ICC2 Version -10 Unit Note IOH = –2 mA Min. 2.4 Max. — V — IOL = 2 mA — 0.4 V ILI — — –10 10 mA ILO — — –10 10 mA CKE ≥ VIH tCC = min tRC = min No Burst — 170 mA 1, 2 CKE ≥ VIH tCC = min CS ≥ VIH — 40 mA 3 Average Power ICC3S Supply Current (Clock Suspension) CKE £ VIL tCC = min — 6 mA 2 Average Power Supply Current (Active Stand by) ICC3 CKE ≥ VIH tCC = min CS ≥ VIH — 100 mA 3 Power Supply Current (Burst) ICC4 CKE ≥ VIH tCC = min — 290 mA 1, 2 Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) ICC5 CKE ≥ VIH tCC = min tRC = min — 190 mA — 2 mA Average Power Supply Current (Power down) ICC7 — 2 mA Notes: ICC6 CKE £ VIL CKE £ VIL 2 tCC = min tCC = min 1. Measured with outputs open. 2. The address and data can be changed once or left unchanged during one cycle. 3. The address and data can be changed once or left unchanged during two cycles. 6/29 ¡ Semiconductor MD56V62320 Mode Set Address Keys CAS Latency Burst Type Burst Length A6 A5 A4 CL A3 BT A2 A1 A0 0 0 0 Reserved 0 Sequential 0 0 0 0 0 1 Reserved 1 Interleave 0 0 1 2 2 0 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Reserved Reserved Note: BT = 0 BT = 1 Reserved Reserved A7, A8, A9, A10, BA1 and BA0 should stay "L" during mode set cycle. POWER ON SEQUENCE 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 ms or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. 7/29 ¡ Semiconductor MD56V62320 AC Characteristics Note 1, 2 Parameter Clock Cycles Time Access Time from Clock Symbol CL = 3 CL = 2 CL = 3 CL = 2 tCC tAC MD56V62320-10 Unit Note Min. Max. 10 — ns 15 — ns — 9 ns 3, 4 3, 4 — 9 ns Clock "H" Pulse Time tCH 3 — ns Clock "L" Pulse Time tCL 3 — ns Input Setup Time tSI 3 — ns Input Hold Time tHI 1 — ns Output Low Impedance Time from Clock tOLZ 3 — ns Output High Impedance Time from Clock tOHZ — 8 ns Output Hold from Clock tOH 3 — ns RAS Cycle Time tRC 90 — ns RAS Precharge Time tRP 30 — ns RAS Active Time tRAS 60 105 ns RAS to CAS Delay Time tRCD 30 — ns Write Recovery Time tWR 15 — ns Write Command Input Time from Output lOWD 2 — Cycle RAS to RAS Bank Active Delay Time tRRD 20 — ns Refresh Time tREF — 64 ms Power-down Exit Set-up Time tPDE tSI + 1 CLK — ns tT — Input Level Transition Time 3 3 ns CAS to CAS Delay Time (Min.) lCCD 1 Cycle Clock Disable Time from CKE lCKE 1 Cycle Data Output High Impedance Time from DQM lDOZ 2 Cycle Data Input Mask Time from DQM lDOD 0 Cycle Data Input Time from Write Command lDWD 0 Cycle Data Output High Impedance Time from Precharge Command lROH 2 Cycle Active Command Input Time from Mode Register Set Command Input (Min.) lMRD 3 Cycle 8/29 ¡ Semiconductor MD56V62320 Notes : 1. AC measurements assume that tT = 1 ns. 2. The reference level for timing of input signals is 1.4 V. 3. Output load. 1.4 V Z = 50 W 50 W Output 50 pF 4. The access time is defined at 1.4 V. 5. If tT is longer than 1 ns, then the reference level for timing of input signals is VIH and VIL. 9/29 , ,,, , ¡ Semiconductor MD56V62320 TIMING WAVEFORM Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tRC CKE CS tRP RAS tRCD CAS ADDR Ra Ca0 Rb Cb0 BA0 BA1 A10 Ra Rb tOH DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 tOHZ tAC Db2 Db3 tWR WE DQM0 - 3 Row Active Read Command Row Active Write Command Precharge Command Precharge Command 10/29 ¡ Semiconductor MD56V62320 Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 2, Burst Length = 4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK , ,, ,, tCC tCL High CKE CS tSI tHI RAS lCCD tHI tSI CAS tSI ADDR tSI tSI Ra Ca Cb tHI Cc tHI BA0 BA1 A10 Ra tAC DQ Qa tHI Db tOLZ Qc tSI tOH tHI tOHZ lOWD WE tSI DQM0 - 3 Row Active Write Command Read Command Precharge Command Read Command 11/29 ¡ Semiconductor *Notes: MD56V62320 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE, DQM0 - 3 are invalid. 2. When issuing an active, read or write command, the bank is selected by BA0 and BA1. BA1 BA0 Active, read or write 0 0 Bank A 0 1 Bank B 1 0 Bank C 1 1 Bank D 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 BA1 BA0 0 0 0 After the end of burst, bank A holds the idle status. Operation 1 0 0 After the end of burst, bank A is precharged automatically. 0 0 1 After the end of burst, bank B holds the idle status. 1 0 1 After the end of burst, bank B is precharged automatically. 0 1 0 After the end of burst, bank C holds the idle status. 1 1 0 After the end of burst, bank C is precharged automatically. 0 1 1 After the end of burst, bank D holds the idle status. 1 1 1 After the end of burst, bank D is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10, BA1 and BA0 inputs. A10 BA1 BA0 0 0 0 Bank A is precharged. 0 0 1 Bank B is precharged. 0 1 0 Bank C is precharged. 0 1 1 Bank D is precharged. 1 X X All banks are precharged. Operation 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1 CLK + tOHZ) after DQM0 - 3 entry. 12/29 ¡ Semiconductor MD56V62320 ,, , , ,,, , , , , ,, Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS Bank A Active RAS CAS lCCD ADDR Ca0 Cb0 Cc0 Cd0 BA0 BA1 A10 DQ Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 lOWD Dd0 tWR *Note2 WE *Note1 DQM0 - 3 Read Command Read Command Write Command Write Command Precharge Command *Notes: 1. To write data before a burst read ends, DQM0 - 3 should be asserted three cycles prior to the write command, to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 13/29 , , ,, , , , ¡ Semiconductor MD56V62320 Read & Write Cycle with Auto Precharge @ Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS tRRD CAS ADDR RAa RDb CAa RAa RDb CDb BA0 BA1 A10 WE CAS Latency = 2 DQ QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 A-Bank Precharge Start DQM0 - 3 CAS Latency = 3 DQ QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 A-Bank Precharge Start tWR DQM0 - 3 Row Active (A-Bank) A Bank Read with Auto Precharge D Bank Write with Auto Precharge D Bank Precharge Start Point Row Active (D-Bank) 14/29 , , , , , ,, ¡ Semiconductor MD56V62320 Bank Interleave Random Row Read Cycle @ CAS Latency = 2, Burst Length = 4 0 CLK CKE CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 High tRC RAS CAS ADDR BA0 BA1 A10 DQ WE tRRD RAa CAa RAa RCb CCb RAc RCb CAc RAc QAa0 QAa1 QAa2 QAa3 QCb0 QCb1 QCb2 QCb3 QAc0 QAc1 QAc2 QAc3 DQM0 - 3 Row Active (A-Bank) Read Command (A-Bank) Read Command (C-Bank) Row Active (C-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Precharge Command (C-Bank) Row Active (A-Bank) 15/29 ¡ Semiconductor MD56V62320 Bank Interleave Random Row Write Cycle @ CAS Latency = 2, Burst Length = 4 , ,,,, , , ,, 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc BA0 BA1 A10 RAa DQ RBb RAc DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 WE DQM0 - 3 Row Active (A-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Row Active (B-Bank) Row Active (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 16/29 ,, ,, , , ¡ Semiconductor MD56V62320 Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE *Note1 CS RAS CAS ADDR RAa CAa RCb CCb CAc CCd CAe BA0 BA1 A10 RAa RCa DQ QAa0 QAa1 QAa2 QAa3 QCb0 QCb1 QCb2 QCb3 QAc0 QAc1 QCd0 QCd1 QAe0 QAe1 lROH WE DQM0 - 3 Row Active (A-Bank) Row Active (C-Bank) Read Command (A-Bank) *Note: Read Command (C-Bank) Read Command (C-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Read Command (A-Bank) 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 17/29 ,,, , , , , ,, , ¡ Semiconductor MD56V62320 Bank Interleave Page Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RBa CBa RDb CDb CBc CDd BA0 BA1 A10 RBa DQ RDb DBa0 DBa1 DBa2 DBa3 DDb0 DDb1 DDb2 DDb3 DBc0 DBc1 DDd0 WE DQM0 - 3 Row Active (B-Bank) Row Active (D-Bank) Write Command (B-Bank) Write Command (D-Bank) Write Command (D-Bank) Write Command (B-Bank) Precharge Command (All Banks) 18/29 ¡ Semiconductor MD56V62320 , , , , , Bank Interleave Random Row Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RCb CCb RAc CAc BA0 BA1 A10 RAa RCb DQ QAa0 QAa1 QAa2 QAa3 RAc DCb0 DCb1 DCb2 DCb3 QAc0 QAc1 QAc2 QAc3 WE DQM0 - 3 Row Active (A-Bank) Row Active (C-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Write Command (C-Bank) Read Command (A-Bank) Row Active (A-Bank) 19/29 ¡ Semiconductor MD56V62320 Bank Interleave Page Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR BA0 BA1 A10 DQ WE , ,, , ,, , High CAa0 CDb0 QAa0 QAa1 QAa2 QAa3 CAc0 DDb0 DDb1 DDb2 DDb3 QAc0 QAc1 QAc2 QAc3 DQM0 - 3 Read Command (A-Bank) Write Command (D-Bank) Read Command (A-Bank) 20/29 ¡ Semiconductor MD56V62320 , , , , , , , , , , , , Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4 CKE CS RAS CAS ADDR BA0 BA1 A10 Ra 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ¨ 1 ¨ 0 CLK *Note1 *Note1 Ca Cb 19 Cc Ra *Note4 DQ1 - 8 Qa1 Qa2 Qa3 Qb0 Qb1 Dc1 Dc2 Dc3 Dc2 Dc3 *Note3 DQ9 - 16 Qa0 Qa2 Qa3 Qb0 Qb1 Dc0 Qa3 Qb0 Qb1 Dc0 Dc1 Qb0 Qb1 Dc0 Dc1 tOHZ DQ17 - 24 Qa0 Qa1 Dc3 *Note2 DQ25 - 32 WE Qa0 Qa1 Qa2 Dc2 *Note4 DQM0 DQM1 DQM2 DQM3 Read DQM Row Active Read DQM Read Command *Notes: 1. 2. 3. 4. CLOCK Suspension Read Command Write DQM Write CLOCK Command Suspension When CKE is deactivated, the next clock will be ignored. When DQM0 - 3 are asserted, the read data after two clock cycles will be masked. When DQM0 - 3 are asserted, the write data in the same clock cycles will be masked. When DQM0 is set High, the input/output data of DQ1 - DQ8 will be masked. When DQM1 is set High, the input/output data of DQ9 - DQ16 will be masked. When DQM2 is set High, the input/output data of DQ17 - DQ24 will be masked. When DQM3 is set High, the input/output data of DQ25 - DQ32 will be masked. 21/29 ¡ Semiconductor MD56V62320 Read Interruption by Precharge Command @ Burst Length = 8 , , ,,, , ,, , ,, 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR Ra Ca BA0 BA1 A10 Ra WE CAS Latency = 2 *Note1 DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 DQM0 - 3 CAS Latency = 3 *Note1 DQ Qa0 Qa1 Qa2 Qa3 Qa4 DQM0 - 3 Row Active *Note: Read Command Precharge Command 1. If row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. 22/29 , , , , , ¡ Semiconductor MD56V62320 Power Down Mode @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI *Note1 tPDE *Note2 tSI tSI CKE CS RAS CAS Ra ADDR Ca BA0 BA1 Ra A10 DQ Qa0 Qa1 Qa2 WE DQM0 - 3 Row Active Power-down Entry *Notes: Power-down Exit Clock Suspention Entry Clock Suspention Exit Read Command Precharge Command 1. When all banks are in precharge state, and if CKE is set low, then the MD56V62320 enters power-down mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than tPDE (tSI + 1 CLK). 23/29 , ,,,, ,, , ¡ Semiconductor MD56V62320 Self Refresh Cycle 0 CLK 1 2 tRC CKE tSI CS RAS CAS ADDR BA0 BA1 A10 DQ WE Ra BS BS Ra Hi - Z Hi - Z DQM0 - 3 Self Refresh Entry Self Refresh Exit Row Active 24/29 ¡ Semiconductor MD56V62320 Auto Refresh Cycle Mode Register Set Cycle 0 CLK CKE CS 1 2 3 4 5 6 0 1 2 3 CAS ADDR DQ WE DQM0 - 3 5 6 7 8 9 10 11 12 ,, ,,,, High High tRC lMRD RAS 4 key Ra Hi - Z MRS New Command Hi - Z Auto Refresh Auto Refresh 25/29 ¡ Semiconductor MD56V62320 FUNCTION TRUTH TABLE (Table 1) (1/2) Current State1 CS RAS CAS WE BA Idle Row Active Read Write Action ADDR H X X X X X NOP L H H H X X NOP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA Row Active L L H L BA A10 NOP 4 L L L H X X Auto-Refresh or Self-Refresh 5 L L L L L OP Code H X X X X X Mode Register Write NOP L H H X X X NOP L H L H BA CA, A10 Read L H L L BA CA, A10 Write L L H H BA RA ILLEGAL 2 L L H L BA A10 Precharge L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L BA X Reserved L H L H BA CA, A10 Term Burst, start new Burst Read L H L L BA CA, A10 Term Burst, start new Burst Write L L H H BA RA ILLEGAL 2 L L H L BA A10 Term Burst, execute Row Precharge L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L BA X Reserved (Term Burst) --> Row Active L H L H BA CA, A10 Term Burst, start new Burst Read L H L L BA CA, A10 Term Burst, start new Burst Write L L H H BA RA ILLEGAL 2 L L H L BA A10 Term Burst, execute Row Precharge L L L X X X ILLEGAL Read with H X X X X X NOP (Continue Burst to End and enter Row Precharge) Auto Precharge L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 L H L H BA CA, A10 ILLEGAL 2 L H L L X X L L H X BA RA, A10 L L L X X X ILLEGAL ILLEGAL ILLEGAL 2 Write with H X X X X X NOP (Continue Burst to End and enter Row Precharge) Auto Precharge L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 L H L H BA CA, A10 ILLEGAL 2 L H L L X X L L H X BA RA, A10 L L L X X X ILLEGAL ILLEGAL 2 ILLEGAL 26/29 ¡ Semiconductor MD56V62320 FUNCTION TRUTH TABLE (Table 1) (2/2) Current State1 CS RAS CAS WE BA Precharge Write Recovery Row Active Refresh Action ADDR H X X X X X NOP --> Idle after tRP L H H H X X NOP --> Idle after tRP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 NOP 4 L L L X X X ILLEGAL H X X X X X NOP L H H H X X NOP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Row Active after tRCD L H H H X X NOP --> Row Active after tRCD L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Idle after tRC L H H X X X NOP --> Idle after tRC L H L X X X ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL Mode Register H X X X X X NOP Access L H H H X X NOP L H H L X X ILLEGAL L H L X X X ILLEGAL L L X X X X ILLEGAL ABBREVIATIONS RA = Row Address CA = Column Address Notes: BA = Bank Address AP = Auto Precharge NOP = No OPeration command 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of lCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 27/29 ¡ Semiconductor MD56V62320 FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 Self Refresh Power Down CKEn CS RAS CAS WE H X X X X L H H X L H L H L H L H H L H L H L L H L L X L L X X X ADDR Action X X INVALID X X X Exit Self Refresh --> ABI H H X Exit Self Refresh --> ABI L X ILLEGAL X X ILLEGAL X X ILLEGAL X X NOP (Maintain Self Refresh) H X X X X X X INVALID L H H X X X X Exit Power Down --> ABI L H L H H H X Exit Power Down --> ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL 6 L L X X X X X NOP (Continue power down mode) H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H L X ILLEGAL H L L L L H X Enter Self Refresh H L L L L L X ILLEGAL L L X X X X X NOP Any State Other H H X X X X X Refer to Operations in Table 1 than Listed Above H L X X X X X Begin Clock Suspend Next Cycle L H X X X X X Enable Clock of Next Cycle L L X X X X X Continue Clock Suspension All Banks Idle 6 (ABI) Note: 6. Power-down and self refresh can be entered only when all the banks are in an idle state. 28/29 ¡ Semiconductor MD56V62320 PACKAGE DIMENSIONS (Unit : mm) TSOPII86-P-400-0.50-K Preliminary Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 29/29 E2Y0002-29-11 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan