FEDS82V16520A-01 OKI Semiconductor MS82V16520A Issue Date:Jun. 25, 2002 262,144-Word × 32-Bit × 2-Bank SGRAM GENERAL DESCRIPTION The MS82V16520A is a 16-Mbit system clock synchronous dynamic random access memory. FEATURES • • • • • • • • • 262,144 words × 32 bits × 2 banks memory (1,024 rows × 256 columns × 32 bits × 2 banks) Single 3.3 V ±0.3 V power supply LVTTL compatible inputs and outputs Programmable burst length (1, 2, 4, 8 and full page) Programmable CAS latency (2, 3) Power Down operation and Clock Suspend operation 2,048 refresh cycles/32 ms Auto refresh and self refresh capability Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK4) (MS82V16520A-xGA) x indicates speed rank. PRODUCT FAMILY Max. Operating Frequency Access Time MS82V16520A-7 Family 143 MHz 6 ns MS82V16520A-8 125 MHz 6.5 ns Package 100-pin Plastic QFP 1/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A 81 82 83 84 85 87 86 88 89 90 91 92 93 94 95 96 97 98 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 53 29 52 30 51 DQ28 VccQ DQ27 DQ26 VssQ DQ25 DQ24 VccQ DQ15 DQ14 VssQ DQ13 DQ12 VccQ Vss Vcc DQ11 DQ10 VssQ DQ9 DQ8 VccQ NC DQM3 DQM1 CLK CKE NC NC A9 A0 A1 A2 A3 Vcc NC NC NC NC NC NC NC NC NC NC Vss A4 A5 A6 A7 50 54 28 49 55 27 48 56 26 47 57 25 46 58 24 45 59 23 44 60 22 43 61 21 42 62 20 41 63 19 40 64 18 39 65 17 38 66 16 37 67 15 36 68 14 35 13 34 69 33 70 12 31 11 32 DQ3 VccQ DQ4 DQ5 VssQ DQ6 DQ7 VccQ DQ16 DQ17 VssQ DQ18 DQ19 VccQ Vcc Vss DQ20 DQ21 VssQ DQ22 DQ23 VccQ DQM0 DQM2 WE CAS RAS CS BA(A10) A8 99 100 DQ2 VssQ DQ1 DQ0 Vcc NC NC NC NC NC NC NC NC NC NC Vss DQ31 DQ30 VssQ DQ29 PIN CONFIGURATION (TOP VIEW) 100-Pin Plastic QFP Pin Name Function A0 to A9 Row Address Inputs A0 to A7 Column Address Inputs BA (A10) Bank Address CLK System Clock Input CKE Clock Enable CS Pin Name WE DQM0 to DQM3 DQ0 to DQ31 VCC VSS Function Write Enable DQ Mask Enable Data Inputs/outputs Supply Voltage Ground Chip Select VCCQ Supply Voltage for DQ RAS Row Address Strobe VSSQ Ground for DQ CAS Column Address Strobe NC No Connection Note: The same power supply voltage level must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A BLOCK DIAGRAM CKE CLK CS RAS CAS WE DQM0 to DQM3 I/O Controller Timing Register Bank Controller BA Internal Col. Address Counter Input Data Register A0 to A9 BA Input Buffers 32 88 Column Address Buffers Sense Amplifiers Internal Row Address Counter 10 32 Column Decoders Row Decoders Word Drivers 8Mb Memory Cells Bank A Row Decoders Word Drivers 8Mb Memory Cells Bank B 32 Read 32 Data Register Output Buffers 32 DQ0 to DQ31 Row Address Buffers Sense Amplifiers 8 Column Decoders 3/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A PIN DESCRIPTION CLK Fetches all inputs at the "H" edge. CS Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQM0, DQM1, DQM2 and DQM3. CKE Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address: RA0 to RA9, BA Selects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. BA = “L”: Bank A BA = “H”: Bank B RAS CAS WE Functionality depends on the combination. For details, see the function truth table. DQM0 to DQM3 Masks the read data of two clocks later when DQM0 to DQM3 are set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQM0 to DQM3 are set "H" at the "H" edge of the clock signal. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and DQM3 controls DQ24 to DQ31. DQ0 to DQ31 Data inputs/outputs are multiplexed on the same pin. Column address: CA0 to CA7 *Notes: 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, DQM0, DQM1, DQM2, and DQM3 are invalid. 2. When issuing an active, read or write command, the bank is selected by BA. BA Active, read or write 0 Bank A 1 Bank B 3. The auto precharge function is enabled or disabled by the A9 input when the read or write command is issued. A9 BA Operation 0 0 After the end of burst, bank A holds the active status. 1 0 After the end of burst, bank A is prechaged automatically. 0 1 After the end of burst, bank B holds the active status. 1 1 After the end of burst, bank B is prechaged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A9 and BA inputs. A9 BA Operation 0 0 Bank A is precharged. 0 1 Bank B is precharged. 1 × Both banks are precharged. 4/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A COMMAND OPERATION Mode Register Set Command (CS, RAS, CAS, WE = “Low”) The MS82V16520A has the mode register that defines the operation mode “CAS Latency, Burst Length, Burst Sequence”. The Mode Register Set command should be executed just after the MS82V16520A is powered on. Before entering this command, all banks must be precharged. Next command can be issued after tRSC. Auto Refresh Command (CS, RAS, CAS = “Low”, WE, CKE = “High”) The Auto Refresh command performs refresh automatically by the address counter. The refresh operation must be performed 2,048 times within 32 ms and the next command can be issued after tRC from last Auto Refresh command. Before entering this command, all banks must be precharged. Self Refresh Entry/Exit Command (CS, RAS, CAS, CKE = “Low”, WE = “High”) The self refresh operation continues after the Self Refresh Entry command is entered, with CKE level left “low”. This operation terminates by making CKE level “high”. The self refresh operation is performed automatically by the internal address counter on the MS82V16520A chip. In self refresh mode, no external refresh control is required. Before entering self refresh mode, all banks must be precharged. Next command can be issued after tRC. Single Bank Precharge Command (CS, RAS, WE, A9 = “Low”, CAS = “High”) The Single Bank Precharge command triggers bank precharge operation. Precharge bank is selected by BA. All Bank Precharge Command (CS, RAS, WE = “Low”, CAS, A9 = “High”) The All Bank Precharge command triggers precharge of both Bank A and Bank B. Bank Active Command (CS, RAS = “Low”, CAS, WE = ”High”) The Bank Active command activates the bank selected by BA. The Bank Active command corresponds to conventional DRAM's RAS falling operation. Row addresses “A0 to A9 and BA” are strobed. Write Command (CS, CAS, WE, A9 = “Low”, RAS = “High”) The Write command is required to begin burst write operation. Then burst access initial bit column address is strobed. Write with Auto Precharge Command (CS, CAS, WE = “Low”, RAS, A9 = “High”) The Write with Auto Precharge command is required to begin burst write operation with automatic precharge after the burst write. Any command that interrupts this operation cannot be issued. Read Command (CS, CAS, A9 = “Low”, RAS, WE = “High”) The Read command is required to begin burst read operation. Then burst access initial bit column address is strobed. 5/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Read with Auto Precharge Command (CS, CAS = “Low”, RAS, WE, A9 = “High”) The Read with Auto Precharge command is required to begin burst read operation with automatic precharge after the burst read. Any command that interrupts this operation cannot be issued. No Operation Command (CS = “Low”, RAS, CAS, WE = “High”) The No Operation command does not trigger any operation. Device Deselect Command (CS = “High”) The Device Deselect command disables the RAS, CAS, WE and Address input. This command does not trigger any operation. Data Write/Output Enable Command (DQMi = “Low”) The Data Write/Output Enable command enables DQ0 to DQ31 in read or write. The each DQM0, 1, 2 and 3 corresponds to DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23 and DQ24 to DQ31 respectively. Data Mask/Output Disable Command (DQMi = “High”) The Data Mask/Output Disable command disables DQ0 to DQ31 in read or write. In read cycle output buffers are disabled after 2 clocks . In write cycle input buffers are disabled at the same clock. The each DQM0, 1, 2 and 3 corresponds to DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23 and DQ24 to DQ31 respectively. Burst Stop Command (CS, WE = “Low”, RAS, CAS = “High”) The Burst Stop command stops burst access when the access is in full page. After the Burst Stop command is entered, the output buffer goes into high impedance state. 6/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A TRUTH TABLE Command Truth Table Address CS RAS CAS WE BA A9 A8 to A0 Device Deselect H × × × × × × No Operation L H H H × × × Function Mode Register Set L L L L Auto Refresh L L L H × OP. CODE Bank Activate L L H H BA Read L H L H BA L CA (A7 to A0) Read with Auto Precharge L H L H BA H CA (A7 to A0) Write L H L L BA L CA (A7 to A0) Write with Auto Precharge L H L L BA H CA (A7 to A0) Precharge Select Bank L L H L BA L × Precharge All Banks L L H L × H × Burst Stop L H H L × × × × × RA DQM Truth Table Function DQMi Data Write/Output Enable L Data Mask/Output Disable H 7/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Function Truth Table (1/2) Note 1 Current State Idle Active (ACT) Read (RD) CS WE BA Address H RAS CAS × × × × × NOP L H H H × × NOP L H H L BA × ILLEGAL 2 L H L × BA CA, A9 ILLEGAL 2 L L H H BA L L L L L L L H L BA RA Action Note Row Active Op-Code Mode Register Write A9 NOP 4 5 L L L H × × Auto Refresh/Self refresh H × × × × × NOP L H H × × × NOP L H L H BA CA, A9 Read L H L L BA CA, A9 Write L L H H BA RA ILLEGAL L L H L BA A9 Precharge L L L × × × ILLEGAL H × × × × × NOP (Continue Row Active after Burst ends) L H H H × × NOP (Continue Row Active after Burst ends) L H H L × × 1,2,4,8 Burst Length : ILLEGAL 2 Full Page Burst : Burst Stop → Row Active Write (WT) L H L L H L L L H L L H L L L H × × H BA CA, A9 Term Burst, new Read L BA CA, A9 H BA RA L BA A9 × × × ILLEGAL × × × NOP (Continue Row Active after Burst ends) 3 Term Burst, start Write 3 ILLEGAL 2 Term Burst, execute Precharge L H H H × × NOP (Continue Row Active after Burst ends) L H H L × × 1,2,4,8 Burst Length : ILLEGAL L H L H BA CA, A9 Term Burst, start Read 3 L H L L BA CA, A9 Term Burst, new Write 3 L L H H BA RA ILLEGAL 2 L L H L BA A9 Term Burst, execute Precharge 3 L L L × × × Full Page Burst : Burst Stop → Row Active ILLEGAL 8/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Function Truth Table (2/2) Note 1 Current State CS WE BA Address Action Read with Auto H RAS CAS × × × × × NOP (Continue Burst to End and enter Row Precharge) Precharge L H H H × × NOP (Continue Burst to End and enter Row Precharge) (RAP) L H H L × × ILLEGAL L H L H BA CA, A9 ILLEGAL L H L L BA CA, A9 ILLEGAL Note L L H H BA RA ILLEGAL 2 L L H L BA A9 ILLEGAL 2 L L L × × × ILLEGAL Write with Auto H × × × × × NOP (Continue Burst to End and enter Row Precharge) Precharge L H H H × × NOP (Continue Burst to End and enter Row Precharge) (WAP) L H H L × × ILLEGAL L H L H BA CA, A9 ILLEGAL L H L L BA CA, A9 ILLEGAL L L H H BA RA ILLEGAL 2 L L H L BA A9 ILLEGAL 2 Precharging (PRE) Refreshing (REF) L L L × × × ILLEGAL H × × × × × NOP → Idle after tRP L H H H × × NOP → Idle after tRP L H H L BA × ILLEGAL 2 L H L × BA CA, A9 ILLEGAL 2 L L H H BA A9 ILLEGAL 2 L L H L BA × NOP 4 H × × × × × NOP → Idle after tRC L H H H × × NOP → Idle after tRC L H H L × × ILLEGAL L H L × BA CA, A9 ILLEGAL L L H H BA RA ILLEGAL L L H L BA A9 ILLEGAL L L L × × × ILLEGAL ABBREVIATIONS BA = Bank Address NOP = No Operation command RA = Row Address CA = Column Address Notes: 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. To avoid bus contention, satisfy tCCD and tDPL. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A9. 5. Illegal if any bank is not idle. 9/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Function Truth Table for CKE Current State (n) Self Refresh (SREF) CKEn-1 CKEn CS RAS CAS WE Address Action H × × × × × × INVALID L H H × × × × Exit Self Refresh → ABI L H L H H H × Exit Self Refresh → ABI L H L H H L × ILLEGAL L H L H L × × ILLEGAL L H L L × × × ILLEGAL L L × × × × × NOP (Maintain Self Refresh) Power Down H × × × × × × INVALID (PD) L H H × × × × Exit Self Refresh → ABI L H L H H H × Exit Self Refresh → ABI All Banks Idle (ABI) Any State Other than Listed Above Note: L H L H H L × ILLEGAL L H L H L × × ILLEGAL L H L L × × × ILLEGAL Note L L × × × × × NOP (Continue power down mode) H H × × × × × Refer to Truth Table 6 H L H × × × × Enter Power Down 6 H L L H H H × Enter Power Down 6 H L L H H L × ILLEGAL 6 H L L H L × × ILLEGAL 6 H L L L H L × ILLEGAL 6 H L L L L H × Enter Self Refresh 6 H L L L L L × ILLEGAL 6 L L × × × × × NOP 6 H H × × × × × Refer to Truth Table H L × × × × × Begin Clock Suspend Next Cycle L H × × × × × Enable Clock of Next Cycle L L × × × × × Continue Clock Suspension 6. Power-down and self refresh can be entered only when all the banks are in an idle state. 10/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Mode Set Address Keys CAS Latency Operation Code A8 A7 0 TM A6 A5 A4 0 Mode Setting 0 0 1 0 0 1 1 Vender Use Only 0 1 0 Write Burst Length Burst Type Burst Length CL A3 BT BT = 0 BT = 1 0 Reserved 0 Sequential 0 0 0 1 Reserved 0 1 Reserved 1 Interleave 0 0 1 2 Reserved 1 0 2 0 1 0 4 4 1 1 3 0 1 1 8 8 0 A2 A1 A0 1 0 0 Reserved 1 0 0 Reserved Reserved A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved 0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved POWER ON SEQUENCE 1. With CKE = "H", DQM = "H" and the other inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 µs or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply an Auto-refresh 2 or more times. 5. Enter the mode register command. 11/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Burst Length and Sequence BL = 2 Starting Address (column address A0, binary) Sequential Type Interleave Type 0 0, 1 Not supported 1 1, 0 Not supported Starting Address (column address A1, A0, binary) Sequential Type Interleave Type 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 Starting Address (column address A2 to A0, binary) Sequential Type Interleave Type 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 BL = 4 BL = 8 BL = Full: Sequential only 12/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A READ/WRITE COMMAND INTERVAL Read to Read Command Interval BL = 4, CL = 2 0 1 2 3 4 5 6 7 8 CLK RD-A RD-B QA1 DQ QB1 QB2 QB3 Hi-Z QB4 1cycle Write to Write Command Interval BL = 4, CL = 2 0 1 2 3 4 5 6 7 8 CLK WT-A WT-B DB1 DA1 DQ DB3 DB2 Hi-Z DB4 1cycle Write to Read Command Interval BL = 4 0 1 2 3 4 5 6 7 8 CLK CL = 2 DQ CL = 3 DQ WT-A RD-B DA1 Hi-Z QB1 QB2 QB3 QB4 QB1 QB2 QB3 WT-A RD-B DA1 Hi-Z QB4 1cycle 13/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Read to Write Command Interval BL = 4, CL = 2, 3 0 1 2 3 4 5 6 5 6 7 8 CLK CL = 2, 3 RD-A WT-B DQM DQ Hi-Z DB1 DB2 DB3 DB4 1cycle BL = 4, CL = 2, 3 0 1 2 3 4 7 8 CLK CL = 2 WT-B RD-A DQM DQ CL = 3 Hi-Z QA1 QA2 QA3 DB1 DB2 Hi-Z is necessary WT-B QA1 QA2 RD-A DQM DQ Hi-Z DB1 DB2 Hi-Z is necessary 14/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A BURST TERMINATION Burst Read Termination by Precharging in READ Cycle BL = 2, 4, 8, Full 0 1 2 3 4 5 6 7 8 CLK tRP RD CL = 2 PRE Q1 DQ Q2 Q3 ACT Hi-Z Q4 tRP RD CL = 3 PRE Q1 DQ Q2 ACT Q3 Hi-Z Q4 Burst Write Termination by Precharging in WRITE Cycle BL = 2, 4, 8, Full 0 1 2 3 4 5 6 7 8 CLK tRP tDPL CL = 2 WT DQ D1 PRE D2 D3 D4 D5 ACT Hi-Z DQM tRP tDPL CL = 3 WT DQ D1 PRE D2 D3 D4 D5 ACT Hi-Z DQM Note: The burst write operation is unfinished, the input data must be masked by means of DQM for assurance of the CLK by tDPL. 15/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Read Burst Stop Command BL = Full 0 1 2 3 4 5 6 7 8 CLK RD BST CL = 2 DQ Q1 CL = 3 DQ Q2 Q3 Q4 Q1 Q2 Q3 Hi-Z Hi-Z Q4 Write Burst Stop Command BL = Full 0 1 2 3 4 5 6 7 8 CLK WT CL = 2, 3 DQ D1 BST D2 D3 D4 Hi-Z 16/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A AUTO PRECHARGE Read with Auto Precharge BL = 4 0 1 2 3 4 5 6 7 8 CLK Auto Precharge Starts RAP CL = 2 Q1 DQ Q2 Q3 Hi-Z Q4 Auto Precharge Starts RAP CL = 3 Q1 DQ Q2 Q3 Hi-Z Q4 (tRAS is satisfied.) Write with Auto Precharge BL = 4 0 1 2 3 4 5 6 7 8 CLK Auto Precharge Starts CL = 2 DQ WAP Q1 Q2 Q3 Hi-Z Q4 Auto Precharge Starts CL = 3 DQ WAP Q1 Q2 Q3 Q4 Hi-Z (tRAS is satisfied.) 17/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Voltage on Power Supply Pin Relative to GND Rating Unit VCC –0.5 to 4.6 V VIN, VOUT –0.5 to VCC + 0.5 ≤ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Voltage on Input Pin Relative to GND *: Ta = 25 °C Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Ratings conditions for extended periods may affect device reliability. Recommended Operating Conditions (Ta = 0 to 70°C) Parameter Power Supply Voltage Symbol Min. Typ. Max. Unit VCC 3.0 3.3 3.6 V VSS 0 0 0 V Input High Voltage VIH 2.0 — VCC + 0.3 V Input Low Voltage VIL –0.3 — 0.8 V Capacitance (VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) Parameter Symbol Min. Max. Unit Input Capacitance (A0 to A9, BA) CIN1 * — 5 pF Input Capacitance (CLK, CKE, CS, RAS, CAS, WE DQM0 to DQM3) CIN2* — 5 pF Output Capacitance (DQ0 to DQ31) COUT * — 6 pF *: This parameter is sampled and not 100% tested. 18/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A DC Characteristics Parameter Symbol Test Condition MS82V16520A-7 MS82V16520A-8 CKE Other Min. Max. Min. Max. 2.4 — 2.4 — Output High Voltage VOH — IOH= –2.0 mA Output Low Voltage Unit Note V VOL — IOL= 2.0 mA — 0.4 — 0.4 V Input Leakage Current ILI — — –10 10 –10 10 µA Output Leakage Current ILO — — –10 10 –10 10 µA Operating Current (1 Bank) ICC1 CKE ≥ VIH tCK = min. tRC = min. No Burst — 190 — 170 mA 1, 2 ICC2P CKE ≤ VIL tCK = min. — 2 — 2 mA 3 ICC2PS CKE ≤ VIL CLK ≤ VIL tCK = ∞ — 2 — 2 mA 2 ICC2N CKE ≥ VIH CS ≥ VIH tCK = min. — 40 — 40 mA 2 ICC2NS CKE ≥ VIH CLK ≤ VIL tCK = ∞ — 20 — 20 mA ICC3P CKE ≤ VIL tCK = min. — 3 — 3 mA 3 ICC3PS CKE ≤ VIL CLK ≤ VIL tCK = ∞ — 3 — 3 mA 3 ICC3N CKE ≥ VIH CS ≥ VIH tCK = min. — 50 — 50 mA 3 ICC3NS CKE ≥ VIH CLK ≤ VIL tCK = ∞ — 30 — 30 mA 3 Operating Current (Burst Mode) ICC4 CKE ≥ VIH tCK = min. — 240 — 200 mA 1, 2 Refresh Current ICC5 CKE ≥ VIH tRC ≥ min. — 170 — 150 mA Self Refresh Current ICC6 CKE ≤ 0.2V — — 3 — 3 mA Precharge Standby Current in Power Down Mode Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode Notes 1. The maximum value of power supply current is obtained with the output open. 2. Address and data are changed only one time during one cycle. 3. Address and data are changed only one time during two cycles. 19/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A AC Characteristics Test conditions • AC measurements assume tT = 1 ns. • Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. • If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX). • An access time is measured at 1.4 V. • Input levels at the AC testing are 2.4 V/0.4 V. tCK tCH tCL 2.4 V CLK 1.4 V 0.4 V tSetup tHold 2.4 V Input 1.4 V 0.4 V tAC tOH Output 1.4 V 1.4 V 20/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Synchronous Characteristics Parameter Clock Cycle Time Access Time from CLK Symbol MS82V16520A-7 MS82V16520A-8 Min. Max. Min. Max. — CAS Latency = 3 tCK3 7 — 8 Unit Note ns CAS Latency = 2 tCK2 10 — 12 — ns CAS Latency = 3 tAC3 — 6 — 6.5 ns 1 CAS Latency = 2 tAC2 — 8 — 9 ns 1 CLK High Level Width tCH 2.5 — 3 — ns CLK Low Level Width tCL 2.5 — 3 — ns Data-out Hold Time tOH 2 — 2 — ns Data-out Low-impedance Time tLZ 0 — 0 — ns Data-out High-impedance Time tHZ — 5 — 6 ns Data-in Setup Time tDS 2 — 2.5 — ns Data-in Hold Time tDH 1 — 1 — ns Address Setup Time tAS 2 — 2.5 — ns Address Hold Time tAH 1 — 1 — ns CKE Setup Time tCKS 2 — 2.5 — ns CKE Hold Time tCKH 1 — 1 — ns Command (CS, RAS, CAS, WE, DQM) Setup Time tCMS 2 — 2.5 — ns Command (CS, RAS, CAS, WE, DQM) Hold Time tCMH 1 — 1 — ns Note 1. Output load. 1.4 V Z = 50Ω 50Ω Output 30 pF 21/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Asynchronous Characteristics Parameter Symbol MS82V16520A-7 MS82V16520A-8 Min. Max. Min. Max. Unit REF to REF/ACT Command Period tRC 63 — 72 — ns ACT to PRE Command Period tRAS 42 120k 48 120k ns PRE to ACT Command Period tRP 21 — 24 — ns Delay Time ACT to READ/WRITE Command tRCD 21 — 24 — ns ACT (A) to ACT (B) Command Period tRRD 14 — 16 — ns READ/WRITE to READ/WRITE Command Period tCCD 7 — 8 — ns Data-in to PRE Command Period tDPL 14 — 16 — ns Data Output to WRITE Command Input Time tOWD 14 — 16 — ns Mode Register Set Cycle Time tRSC 14 — 16 — ns tT 1 30 1 30 ns tREF — 32 — 32 ms Transition Time Refresh Time Note 22/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A TIMING WAVEFORM READ/WRITE Cycle (BL = 2, CL = 3) 0 CLK 1 2 tCK tCKS tCH 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tCKH tCL CKE tCMS tCMH CS RAS CAS WE tAS tAH BA A9 RAa ADD RAa RBa CAa tCMS DQM 0-3 DQ CAb tAC tOH Hi-Z tHZ tDS tDH DAb1 DAb2 QAa1 QAa2 tRCD RBa tCMH tLZ tOWD tDPL tRAS tRP tRC ACT-A RD-A WT-A PRE-A ACT-B 23/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Mode Register Set 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE H CS RAS CAS WE BA A9 ADD DQM 0-3 DQ Hi-Z MRA PRE-ALL tRP ACT tRSC 24/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Auto Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE H CS RAS CAS WE BA A9 ADD DQM 0-3 L DQ Hi-Z REF PRE-ALL tRP REF tRC ACT tRC 25/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Self Refresh (Entry and Exit) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE H CS RAS CAS WE BA A9 ADD DQM 0-3 DQ L Hi-Z PRE-ALL tRP SELF Entry SELF Exit tRC SELF Entry SELF Exit ACT tRC 26/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Burst Termination by Precharging (BL = 8, CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE H CS RAS CAS WE BA A9 RAa ADD RAa DQM 0-3 DQ RAb CAa RAb CAb L tDPL Hi-Z ACT-A DAa1 WT-A QAb1 QAb2 QAb3 QAb4 PRE-A ACT-A PRE Command Termination RD-A PRE-A PRE Command Termination 27/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Auto Precharge (BL = 4, CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE H CS RAS CAS WE BA A9 RAa RBa ADD RAa CAa RBa DQM 0-3 L DQ Hi-Z ACT-A CBa QAa1 QAa2 QAa3 QAa4 RAP-A ACT-B AP-A QBa1 QBa2 QBa3 QBa4 WAP-B AP-B 28/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Power Down Mode and Clock Suspension (BL = 4, CL = 2) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tCKS CKE CS RAS CAS WE BA A9 RAa ADD RAa DQM 0-3 DQ CAa L Hi-Z QAa1 QAa2 ACT-A QAa3 PRE-A RD-A PD Entry PD Exit ACTIVE STANDBY QAa4 Clock Mask Start Clock Mask End PD Entry PD Exit PRECHARGE STANDBY 29/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A CLOCK Suspend Exit & Power Down Exit 1) Clock Suspend (= Active Power Down) Exit 2) Power Down (= Precharge Power Down) Exit CLK CLK CKE CKE Note 3 Internal CLK Command tCKS Internal CLK Note 1 RD tCKS Note 2 Command NOP ACT Notes: 1. Active power down: one or both bank active state. 2. Precharge power down: both bank precharge state. 3. NOP should be issued. And new command can be issued after 1 Clock. 30/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Byte Read/Write Operation (by DQM) (BL = 4, CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE H CS RAS CAS WE BA A9 RBa ADD RBa CBa CBb DQM0 DQM1 DQ 0-7 QBa1 QBa2 QBa3 DQ 8 - 15 QBa2 QBa3 QBa4 ACT-B RD-B Byte of DQ8-15 not Read DBb2 DBb3 DBb1 DBb2 DBb4 WT-B Byte of Byte of DQ8-15 DQ0-7 not Write not Write Byte of Byte of DQ0-7 DQ0-7 not Read not Write 31/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Burst Read and Single Write (BL = 4, CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE H CS RAS CAS WE BA A9 RAa ADD RAa DQM 0-3 L DQ Hi-Z ACT-B CAa QAa1 QAa2 QAa3 QAa4 RD-B CBb CBb DBb DBc Single WT Single WT PRE-B 32/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Random Column Read (Continuous Read of Same Bank) (BL = 4, CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE H CS RAS CAS WE BA A9 RAa ADD RAa DQM 0-3 RAi CAa CAb CAc RAi L DQ QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 ACT-A RD-A RD-A RD-A PRE-A ACT-A 33/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Random Column Write (Continuous Write of Same Bank) (BL = 4, CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE H CS RAS CAS WE BA A9 RBa ADD RBa DQM 0-3 RBi CBa CBb CBc RBi L DQ DBa1 DBa2 DBa3 DBa4 DBb1 DBb2 DBc1 DBc2 DBc3 DBc4 ACT-B WT-B WT-B WT-B PRE-B ACT-B 34/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Interleaved Column Read (BL = 4, CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE H CS RAS CAS WE BA A9 RAa RBa ADD RAa CAa RBa DQM 0-3 CBa CBb CAb L DQ QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBb1 QBc2 QAb1 QAb2 QAb3 QAb4 ACT-A RD-A ACT-B RD-B RD-B RD-A PRE-B PRE-A tRCD tRRD 35/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A Interleaved Column Write (BL = 4, CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE H CS RAS CAS WE BA A9 RAa RBa ADD RAa CAa RBa DQM 0-3 CBa CBb CAb L DQ DAa1 DAa2 DAa3 DAa4 DBa1 DBa2 DBb1 DBb2 DAb1 DAb2 DAb3 DAb4 ACT-A WT-A ACT-B WT-B WT-B WT-A PRE-B PRE-A tRCD tRRD 36/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A PACKAGE DIMENSIONS (Unit: mm) QFP100-P-1420-0.65-BK4 Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 1.54 TYP. 4/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 37/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A REVISION HISTORY Document No. Date PEDS82V16520A-01 Nov. 2001 Page Previous Current Edition Edition – – Preliminary first edition 1 1 Changed the subtitle from “2262,144-Word × 32-Bit × 2-Bank SDRAM” to “262,144-Word × 32-Bit × 2-Bank SGRAM”. 4 4 Apr. 26, 2002 Changed the table in “PRODUCT FAMILY” Changed Note 3 to Note 4 and added Note 3. 5 Added symbol “CKE” in headers “Auto Refresh Command” and “Self Refresh Entry/Exit Command”. Added Section “Write with Auto Precharge Command (CS, CAS, WE = “Low”, RAS, A9 = “High”). 6 6 Added Sections “Read with Auto Precharge Command (CS, CAS = “Low”, RAS, WE, A9 = “High”) and “Burst Stop Command (CS, WE = “Low”, RAS, CAS = “High”). 7 7 Added the contents of Functions “Read with Auto Precharge” and “Write with Auto Precharge”. 8 8 Partially changed the contents of Column “Address”. 8 9 Current State “Precharging (PRE)” has been moved to page 9 and changed partially. 5 PEDS82V16520A-02 Description Added Current States “Read with Auto Precharge (RAP)” and “Write with Auto Precharge (WAP)”. 9 9 11 11 Partially changed the content of POWER ON SEQUENCE 4. 15 15 Changed the heading from “Burst Read Termination ---“ to “Burst Write Termination ---“ and partially changed the timing diagram. Changed the content of Note. 16 16 Changed “BL = 2, 4, 8, Full” to “BL = Full” in two diagrams. – 17 Added Section “AUTO PRECHARGE”. 18 Added Sentences shown with “Caution” in the Absolute Maximum Ratings section. Added asterisks “*” in the symbol column in the table of the Capacitance section and added the sentence shown with asterisk “*”. 17 Partially changed the content of Column “Address” in Current State “Refreshing (REF)”. 38/40 FEDS82V16520A-01 OKI Semiconductor Document No. MS82V16520A Date Page Previou Current s Edition Edition Description Changed a family device name from MS82V 16520A-10 to MS82V16520A-7 shown in the table and added related values. 18 19 Partially changed Max. values of MS82V 16520A-75 and MS82V16520A-8. Partially changed Test Condition “Other” of Symbols ICC2N, ICC3P, and ICC3N. Added 1 in Column “Note” of Symbol ICC4. PEDS82V16520A-02 Apr. 26, 2002 20 21 Changed a family device name from MS82V 16520A-10 to MS82V16520A-7 shown in the table and added related values. Partially changed Max. and Min. values of MS82V16520A-75 and MS82V16520A-8. 21 22 Changed a family device name from MS82V 16520A-10 to MS82V16520A-7 shown in the table and added related values. Change the Min. values of Symbol tDPL. FEDS82V16520A-01 Jun. 25, 2002 26 27 Changed timings of DQM and DQ between CLK pulses 4 and 6. – 28 Added Section “Auto Prechaged (BL = 4, CL = 3)”. – – First edition 1 1 19,21,22 19,21,22 Partially changed the table of “PRODUCT FAMILY” Partially changed the content of “Package” in the FEATURES section. Partially changed the tables of “DC Characteristics”, “Synchronous Characteristics”, and “Asynchronous Characteristics”. 39/40 FEDS82V16520A-01 OKI Semiconductor MS82V16520A NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 40/40