FEDD5118165F-01 1Semiconductor MSM5118165F This version: June. 2000 Previous version : 1,048,576-Word × 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM5118165F is a 1,048,576-word × 16-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM51V18165F achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5118165F is available in a 42-pin plastic SOJ or 50/44-pin plastic TSOP. FEATURES · 1,048,576-word × 16-bit configuration · Single 5V power supply, ±10% tolerance · Input : TTL compatible, low input capacitance · Output : TTL compatible, 3-state · Refresh : 1024 cycles/16ms · Fast page mode with EDO, read modify write capability · CAS before RAS refresh, hidden refresh, RAS-only refresh capability · Packages (SOJ42-P-400-1.27) 42-pin 400mil plastic SOJ (Product : MSM5118165F-xxJS) 50/44-pin 400mil plastic TSOP (TSOPII50/44-P-400-0.80-K) (Product : MSM5118165F-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Access Time (Max.) Family MSM5118165F tRAC tAA tCAC tOEA Cycle Time (Min.) 50ns 60ns 70ns 25ns 30ns 35ns 13ns 15ns 20ns 13ns 15ns 20ns 84ns 104ns 124ns Power Dissipation Operating (Max.) 743mW 688mW 633mW Standby (Max.) 5.5mW 1/15 FEDD5118165F-01 1Semiconductor MSM5118165F PIN CONFIGURATION (TOP VIEW) VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 NC 12 WE 13 RAS 14 NC 15 NC 16 A0 17 A1 18 A2 19 A3 20 VCC 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 42-Pin Plastic SOJ VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 50 49 48 47 46 45 44 43 42 41 40 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC NC 15 NC 16 WE 17 RAS 18 NC 19 NC 20 A0 21 A1 22 A2 23 A3 24 VCC 25 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS 50/44-Pin Plastic TSOP (K Type) Pin Name Function A0–A9 Address Input RAS Row Address Strobe LCAS Lower Byte Column Address Strobe UCAS Upper Byte Column Address Strobe DQ1–DQ16 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (5V) VSS Ground (0V) NC No Connection Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/15 FEDD5118165F-01 1Semiconductor MSM5118165F BLOCK DIAGRAM WE OE Timing Generator RAS I/O Controller LCAS UCAS I/O Controller 10 10 Row Address Buffers Output Buffers 8 Input Buffers 8 8 Input Buffers 8 8 Output Buffers 8 DQ1-DQ8 Column Address Buffers 10 Internal Address Counter A0-A9 8 Refresh Control Clock 10 Row Decoders Column Decoders Sense Amplifiers Word Memory Drivers Cells 16 I/O Selector 16 DQ9-DQ16 8 VCC On Chip VBB Generator On Chip IVCC Generator VSS FUNCTION TABLE Input Pin DQ Pin Function Mode RAS LCAS UCAS WE OE DQ1-DQ8 DQ9-DQ16 H * * * * High-Z High-Z Standby L H H * * High-Z High-Z Refresh L L H H L DOUT High-Z Lower Byte Read L H L H L High-Z DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L H L H DIN Don’t Care Lower Byte Write L H L L H Don’t Care DIN Upper Byte Write L L L L H DIN DIN Word Write L L L H H High-Z High-Z * : “H” or “L” 3/15 FEDD5118165F-01 1Semiconductor MSM5118165F ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on Any Pin Relative to VSS VIN, VOUT –0.5 to VCC+ 0.5 V Voltage VCC Supply relative to VSS VCC –0.5 to 7 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C *: Ta = 25°C RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70°C) Parameter Power Supply Voltage Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 VCC + 0.5 Input Low Voltage VIL − 0.5*2 0.8 *1 V V Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS − 2.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied). PIN CAPACITANCE (Vcc = 5V ± 10%, Ta = 25°C, f = 1 MHz) Parameter Symbol Min. Typ. Min. Unit CIN1 — — 5 pF (RAS, LCAS, UCAS, WE, OE) CIN2 — — 7 pF Output Capacitance (DQ1 - DQ16) CI/O — — 7 pF Input Capacitance (A0 - A9) Input Capacitance 4/15 FEDD5118165F-01 1Semiconductor MSM5118165F DC CHARACTERISTICS (VCC = 5V ± 10%, Ta = 0 to 70°C) Parameter Symbol Condition Min. Max. Min. Max. 2.4 VCC 2.4 VCC 2.4 VCC V 0 0.4 0 0.4 0 0.4 V All other pins not under test = 0V − 10 10 − 10 10 − 10 10 µA DQ disable − 10 10 − 10 10 − 10 10 µA 135 125 115 mA 1,2 RAS, CAS = VIH 2 2 2 RAS, CAS ≥ VCC − 0.2V 1 1 mA 1 1 135 125 115 mA 1,2 5 5 5 mA 1 135 125 115 mA 1,2 120 110 100 mA 1,3 IOH = −5.0mA Output Low Voltage VOL IOL = 4.2mA 0V ≤ VI ≤ 6.5V; Input Leakage Current ILI Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) ICC2 (Standby) ICC3 (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) RAS, CAS cycling, tRC = Min. CAS = VIH, tRC = Min. RAS = VIH, ICC5 (Standby) Average Power Supply Current 0V ≤ VO ≤ VCC RAS cycling, (RAS-only Refresh) Power Supply Current MSM5118165 F-70 Unit Note Max. VOH Average Power Supply Current MSM5118165 F-60 Min. Output High Voltage Power Supply Current MSM5118165 F-50 CAS = VIL, DQ = enable ICC6 RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min. Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 5/15 FEDD5118165F-01 1Semiconductor MSM5118165F AC CHARACTERISTICS (1/2) (VCC = 5V ± 10%, Ta = 0 to 70°C) Note1,2,3 MSM5118165 F-50 MSM5118165 F-60 MSM5118165 F-70 Min. Max. Min. Max. Min. Max. tRC 84 104 124 ns Read Modify Write Cycle Time tRWC 110 135 160 ns Fast Page Mode Cycle Time tHPC 20 25 30 ns Fast Page Mode Read Modify Write tHPRWC Cycle Time 58 68 78 ns Access Time from RAS tRAC 50 60 70 ns 4, 5, 6 Access Time from CAS tCAC 13 15 20 ns 4,5 Access Time from Column Address tAA 25 30 35 ns 4,6 Access Time from CAS Precharge tCPA 30 35 40 ns 4,13 Access Time from OE tOEA 13 15 20 ns 4 Output Low Impedance Time from CAS tCLZ 0 0 0 ns 4 Data Output Hold After CAS Low tDOH 5 5 5 ns CAS to Data Output Buffer Turnoff Delay Time tCEZ 0 13 0 15 0 20 ns 7,8 RAS to Data Output Buffer Turnoff Delay Time tREZ 0 13 0 15 0 20 ns 7,8 OE to Data Output Buffer Turn-off Delay Time tOEZ 0 13 0 15 0 20 ns 7 WE to Data Output Buffer Turnoff Delay Time tWEZ 0 13 0 15 0 20 ns 7 Transition Time tT 1 50 1 50 1 50 ns 3 Refresh Period tREF 16 16 16 ms RAS Precharge Time tRP 30 40 50 ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode with EDO) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time tRSH 7 10 13 ns RAS Hold Time referenced to OE tROH 7 10 13 ns CAS Precharge Time (Fast Page Mode with EDO) tCP 7 10 10 ns CAS Pulse Width tCAS 7 10,000 10 10,000 13 10,000 ns CAS Hold Time tCSH 35 40 45 ns CAS to RAS Precharge Time tCRP 5 5 5 ns 13 30 35 40 ns 13 Parameter Random Read or Write Cycle Time Symbol RAS Hold Time from CAS Precharge tRHCP Unit Note 15 6/15 FEDD5118165F-01 1Semiconductor MSM5118165F AC CHARACTERISTICS (2/2) (VCC = 5V ± 10%, Ta = 0 to 70°C) Note1,2,3 Parameter Symbol MSM5118165 F-50 MSM5118165 F-60 MSM5118165 F-70 Min. Max. Min. Max. Min. Max. Unit Note OE Hold Time from CAS (DQ Disable) tCHO 5 5 5 ns RAS to CAS Delay Time tRCD 11 37 14 45 14 50 ns 5 RAS to Column Address Delay Time tRAD 9 25 12 30 12 35 ns 6 Row Address Set-up Time tASR 0 0 0 ns Row Address Hold Time tRAH 7 10 10 ns Column Address Set-up Time tASC 0 0 0 ns 12 Column Address Hold Time tCAH 7 10 13 ns 12 Column Address to RAS Lead Time tRAL 25 30 35 ns Read Command Set-up Time tRCS 0 0 0 ns 12 Read Command Hold Time tRCH 0 0 0 ns 9,12 Read Command Hold Time referenced to RAS tRRH 0 0 0 ns 9 Write Command Set-up Time tWCS 0 0 0 ns 10,12 Write Command Hold Time tWCH 7 10 13 ns 12 Write Command Pulse Width tWP 7 10 10 ns WE Pulse Width (DQ Disable) tWPE 7 10 10 ns OE Command Hold Time tOEH 7 10 13 ns OE Precharge Time tOEP 7 10 10 ns OE Command Hold Time tOCH 7 10 10 ns Write Command to RAS Lead Time tRWL 7 10 13 ns Write Command to CAS Lead Time tCWL 7 10 13 ns 14 Data-in Set-up Time tDS 0 0 0 ns 11,12 Data-in Hold Time tDH 7 10 13 ns 11,12 OE to Data-in Delay Time tOED 13 15 20 ns CAS to WE Delay Time tCWD 30 34 44 ns 10 Column Address to WE Delay Time tAWD 42 49 59 ns 10 RAS to WE Delay Time tRWD 67 79 94 ns 10 tCPWD 47 54 64 ns 10 CAS Active Delay Time from RAS Precharge tRPC 5 5 5 ns 12 RAS to CAS Set-up Time (CAS before RAS) tCSR 5 5 5 ns 12 RAS to CAS Hold Time (CAS before RAS) tCHR 10 10 10 ns 13 CAS Precharge WE Delay Time 7/15 FEDD5118165F-01 1Semiconductor MSM5118165F Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. -50 is measured with a load circuit equivalent to 2 TTL load and 50pF, and -60/-70 is measured with a load circuit equivalent to 2 TTL load and 100pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.), and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. tCEZ, and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 14. tCWL should be satisfied by both UCAS and LCAS. 15. tCP is determined by the time both UCAS and LCAS are high. 8/15 FEDD5118165F-01 1Semiconductor MSM5118165F TIMING CHART Read Cycle RAS tRC tRAS VIH tRP VIL tCSH tCRP CAS tRCD VIH tRAD VIL tRAL tASR Address WE OE tCRP tRSH tCAS VIH tRAH tASC Row VIL tCAH Column tRCS tRRH VIH tAA VIL tRCH tROH VIH VIL tCAC tRAC DQ tREZ tOEA tCEZ tOEZ tCLZ VOH Valid Data-out Open VOL “H” or “L” Write Cycle (Early Write) RAS tRC tRAS VIH tRP VIL tCSH tCRP CAS VIH tRAD VIL tRAL tASR Address VIH VIL tRAH tASC Row OE tCWL VIH tWCH tWP VIL tRWL VIH VIL tDS DQ tCAH Column tWCS WE tCRP tRSH tCAS tRCD VIH VIL tDH Valid Data-in Open “H” or “L” 9/15 FEDD5118165F-01 1Semiconductor MSM5118165F Read Modify Write Cycle tRWC RAS tRAS VIH tRP VIL tCSH tCRP CAS tRAD VIL VIH VIL tCRP tRSH tCAS VIH tASR Address tRCD tRAH Row tASC tCWL tRWL tCAH Column tRCS tCWD tRWD WE OE tWP VIH VIL tAWD tAA tOEH tOEA VIH tOED VIL tDH tCAC tRAC DQ VI/OH VI/OL tOEZ tCLZ Valid Data-out tDS Valid Data-in “H” or “L” 10/15 FEDD5118165F-01 1Semiconductor MSM5118165F Fast Page Mode Read Cycle (part-1) tRASP RAS VIH VIL Address tHPC tCSH tCRP CAS VIH VIL tRAD tASR tASC tRAH Row tRHCP tCP tCP tCAS VIH VIL tRP tRCD tCAS tCAH tASC Column tCAS tASC tCAH Column tCAH Column tRCS WE OE tOCH VIH tAA VIL tCAC tRAC tAA VIH VIL tCAC tOEP tOEA tOEA tOEZ tOEZ tDOH VOH Valid Data-out VOL tCAC tAA tCHO tOEP tCPA tOEA DQ tRRH Valid Data-out Valid * Data-out tREZ Valid * Data-out tCLZ * : Same Data, “H” or “L” Fast Page Mode Read Cycle (part-2) tRP tRASP RAS VIH VIL tCRP tCSH Address VIH VIL tCAS tCAS tASR tRAD tRAH Row tASC tCAH OE tCAH tASC Column Column tRCS WE tCP tCP VIH VIL tCRP tHPC tRCD CAS tRHCP tHPC tCAS tASC tCAH Column tRCS VIH VIL tAA tRAC tRCH tWPE tOEA VIH tAA tCPA tAA tCAC tDOH VIL tCAC tCAC DQ VOH VOL tWEZ Valid Data-out Valid Data-out tCEZ Valid Data-out tCLZ “H” or “L” 11/15 FEDD5118165F-01 1Semiconductor MSM5118165F Fast Page Mode Write Cycle (Early Write) tRP tRASP RAS CAS Address WE OE tCSH VIH VIL tCRP tHPC tRCD tCP VIH VIL tRAD tASR tASC tRAH Row tASC Column tWCS VIH tRSH tCAS tCAS tCAH tASC tCAH Column tWCS tWCH tCAH Column tWCS tWCH tWCH VIL VIH VIL tDS DQ tCP tCAS VIH VIL tHPC VIH tDH tDS Valid Data-in VIL tDH tDS tDH Valid Data-in Valid Data-in “H” or “L” Fast Page Mode Read Modify Write Cycle tRASP RAS CAS VIH VIL tRWD tCRP tRCD tCP VIH VIL VIH VIL tASC tASC tRAD tHPRWC tRAH Row Column VIH VIL Column VIH tAWD tAWD tAA tDS tAA tOED VI/OH tCLZ tDS tWP tOEA VIL VI/OL tWP tOEA tCAC DQ tCWD tRCS tRAC OE tCAH tCPA tCWL tCAH tRCS WE tRWL tCWD tASR Address tCPWD tOED tOEH tOEZ tDH Valid Data-out Valid Data-in tCAC tOEH tOEZ Valid Data-out tDH Valid Data-in tCLZ “H” or “L” 12/15 FEDD5118165F-01 1Semiconductor MSM5118165F RAS-only Refresh Cycle RAS tRC RAS CAS Address tRAS VIH VIL tRP tRPC tCRP VIH VIL tASR VIH tRAH Row VIL tCEZ DQ VOH Open VOL Note: WE, OE = “H” or “L” “H” or “L” CAS before RAS Refresh Cycle tRP RAS CAS tRC tRAS VIH VIL tRPC tCP tRP tCSR tRPC tCHR VIH VIL tCEZ DQ VOH VOL Open 13/15 FEDD5118165F-01 1Semiconductor MSM5118165F Hidden Refresh Read Cycle tRC RAS CAS VIH VIL tCRP tRAS tRCD tRSH VIH tRP tRAD VIL tRAH VIH tASC Row VIL tCAH Column tRCS WE tRP tCHR tASR Address tRC tRAS tCAC VIH VIL tRRH tRAL tREZ tAA tROH OE DQ tCEZ tOEA VIH VIL tRAC tOEZ tCLZ VOH Open VOL Valid Data-out “H” or “L” Hidden Refresh Write Cycle tRC RAS CAS VIH VIL tCRP WE tRCD DQ tRSH VIH VIH VIL tRP tRP tRAD VIL tRAH tASC Row tCAH Column tRAL tRWL tWP VIH VIL tWCS OE tRAS tCHR tASR Address tRC tRAS tWCH VIH VIL VIH tDS tDH Valid Data-in VIL “H” or “L” 14/15 FEDD5118165F-01 1Semiconductor MSM5118165F NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 15/15