OKI MSM54V16283

E2L0027-17-Y1
¡ Semiconductor
MSM54V16283
¡ Semiconductor
This version:
Jan. 1998
MSM54V16283
Previous version: Dec. 1996
262,144-Word ¥ 16-Bit Multiport DRAM
DESCRIPTION
The MSM54V16283 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit
dynamic RAM, and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and
asynchronously.
It supports three types of operations: random access to RAM port, high speed serial access to
SAM port, and bidirectional transfer of data between any selected row in the RAM port and the
SAM port. In addition to the conventional multiport DRAM operating modes, the MSM54V16283
features block write, flash write functions, extended page mode on the RAM port, a split data
transfer capability, and programmable stops on the SAM port. The SAM port requires no refresh
operation because it uses static CMOS flip-flops.
FEATURES
• Single power supply: 3.3 V ±0.3 V
• RAS only refresh
• Full TTL compatibility
• CAS before RAS refresh
• Multiport organization
• CAS before RAS self-refresh
RAM : 256K word ¥ 16 bits
• Hidden refresh
SAM : 512 word ¥ 16 bits
• Serial read/write
• Extended page mode
• 512 tap location
• Write per bit
• Programmable stops
• Persistent write per bit
• Bidirectional data transfer
• Byte write
• Split transfer
• Masked flash write
• Masked write transfer
• Masked block write (8 columns)
• Refresh: 512 cycles/8 ms
• Package options:
64-pin 525 mil plastic SSOP
(SSOP64-P-525-0.80-K) (Product : MSM54V16283-xxGS-K)
70/64-pin 400 mil plastic TSOP (Type II)(TSOPII70/64-P-400-0.65-K)(Product : MSM54V16283-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time
Cycle Time
Power Dissipation
RAM
SAM
RAM
SAM
Operating
Standby
MSM54V16283-60
60 ns
18 ns
120 ns
22 ns
160 mA
8 mA
MSM54V16283-70
70 ns
20 ns
140 ns
22 ns
150 mA
8 mA
1/42
¡ Semiconductor
MSM54V16283
PIN CONFIGURATION (TOP VIEW)
VCC
TRG
VSS
SDQ0
DQ0
SDQ1
DQ1
VCC
SDQ2
DQ2
SDQ3
DQ3
VSS
SDQ4
DQ4
SDQ5
DQ5
VCC
SDQ6
DQ6
SDQ7
DQ7
VSS
WEL
WEU
RAS
A8
A7
A6
A5
A4
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SC
SE
VSS
SDQ15
DQ15
SDQ14
DQ14
VCC
SDQ13
DQ13
SDQ12
DQ12
VSS
SDQ11
DQ11
SDQ10
DQ10
VCC
SDQ9
DQ9
SDQ8
DQ8
VSS
DSF
NC
CAS
QSF
A0
A1
A2
A3
VSS
VCC
TRG
VSS
SDQ0
DQ0
SDQ1
DQ1
VCC
SDQ2
DQ2
SDQ3
DQ3
VSS
SDQ4
DQ4
SDQ5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
SC
SE
VSS
SDQ15
DQ15
SDQ14
DQ14
VCC
SDQ13
DQ13
SDQ12
DQ12
VSS
SDQ11
DQ11
SDQ10
DQ5
VCC
SDQ6
DQ6
SDQ7
DQ7
VSS
WEL
WEU
RAS
A8
A7
A6
A5
A4
VCC
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
DQ10
VCC
SDQ9
DQ9
SDQ8
DQ8
VSS
DSF
NC
CAS
QSF
A0
A1
A2
A3
VSS
70/64-Pin Plastic TSOP (II)
(K Type)
64-Pin Plastic SSOP
Pin Name
A0 - A8
Function
Pin Name
Function
Address Input
SC
Serial Clock
RAM Inputs/Outputs
SE
SAM Port Enable
SDQ0 - SDQ15
SAM Inputs/Outputs
DSF
Special Function Input
RAS
Row Address Strobe
QSF
Special Function Output
DQ0 - DQ15
Note:
CAS
Column Address Strobe
VCC
Power Supply (3.3 V)
WEL
Write Enable Lower
VSS
Ground (0 V)
WEU
Write Enable Upper
NC
No Connection
TRG
Transfer/Output Enable
The same power supply voltage must be provided to every VCC pin, and the same GND
voltage level must be provided to every VSS pin.
2/42
Block Write
Control
Column Mask
Sense Amp.
I/O Control
Color Register
Register
RAM Input
Buffer
Mask Register
A0 - A8
Refresh
Counter
Row Decoder
Row
Address
Buffer
512 ¥ 512 ¥ 16
RAM ARRAY
Gate
Gate
SAM
SAM
Serial Decoder
SAM
Address
Buffer
¡ Semiconductor
Column Decoder
BLOCK DIAGRAM
Column
Address
Buffer
DQ 0 - 15
RAM Output
Buffer
Flash Write
Control
SAM Input
Buffer
RAS
CAS
SDQ 0 - 15
SAM Output
Buffer
Timing
Generator
TRG
WEU / WEL
DSF
SC
SAM Address
Counter
QSF
SE
SE
VCC
VSS
3/42
MSM54V16283
SAM Stop
Control
¡ Semiconductor
MSM54V16283
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Note: 1)
Parameter
Symbol
Condition
Rating
Unit
Input Output Voltage
VT
Ta = 25°C
–0.5 to 4.6
V
Output Current
IOS
Ta = 25°C
50
mA
Power Dissipation
PD
Topr
Ta = 25°C
1
W
Operating Temperature
—
0 to 70
°C
Storage Temperature
Tstg
—
–55 to 150
°C
Recommended Operating Conditions
(Ta = 0°C to 70°C) (Note: 2)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supply Voltage
VCC
3.0
Input High Voltage
VIH
2.0
3.3
3.6
V
—
VCC + 0.3
V
Input Low Voltage
VIL
–0.3
—
0.8
V
Capacitance
(VCC = 3.3 V ±0.3 V, f = 1 MHz, Ta = 25°C)
Parameter
Input Capacitance
Input/Output Capacitance
Output Capacitance
Note:
Symbol
Min.
Max.
Unit
Ci
—
6
pF
Cio
—
7
pF
Co(QSF)
—
7
pF
This parameter is periodically sampled and is not 100% tested.
DC Characteristics 1
Symbol
Condition
Min.
Max.
Output "H" Level Voltage
VOH
IOH = –2 mA
2.4
—
Output "L" Level Voltage
VOL
IOL = 2 mA
—
0.4
Input Leakage Current
ILI
0 £ VIN £ VCC
All other pins not
under test = 0 V
–10
10
0 £ VOUT £ VCC
Output Disable
–10
Parameter
Output Leakage Current
ILO
Unit
V
mA
10
4/42
¡ Semiconductor
MSM54V16283
DC Characteristics 2
(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C)
Item (RAM)
Operating Current
(RAS, CAS Cycling, tRC = tRC min.)
SAM
Symbol
-60
-70
Max.
Max.
Unit Note
Standby
ICC1
120
110
3, 4
Active
ICC1A
160
150
17
Standby Current
Standby
ICC2
8
8
(RAS, CAS = VIH)
Active
ICC2A
55
55
3, 4
Standby
ICC3
120
110
3, 4
Active
ICC3A
160
150
17
Standby
ICC4
120
110
3, 4
Active
ICC4A
160
150
Standby
ICC5
100
90
Active
ICC5A
140
130
3, 4
Standby
ICC6
110
100
3, 4
RAS Only Refresh Current
(RAS Cycling, CAS = VIH, tRC = tRC min.)
Page Mode Current
(RAS = VIL, CAS Cycling, tPC = tPC min.)
CAS before RAS Refresh Current
(RAS Cycling, CAS before RAS, tRC = tRC min.)
Data Transfer Current
(RAS, CAS Cycling, tRC = tRC min.)
Flash Write Current
(RAS, CAS Cycling, tRC = tRC min.)
Block Write Current
(RAS, CAS Cycling, tRC = tRC min.)
CAS before RAS Self-Refresh Current
(RAS, CAS £ 0.2 V)
mA
18
3, 4
Active
ICC6A
150
140
17
Standby
ICC7
110
100
3, 4
Active
ICC7A
150
140
3, 4
Standby
ICC8
110
100
3, 4
Active
ICC8A
150
140
3, 4
Standby
ICC9
1
1
3, 4
5/42
¡ Semiconductor
MSM54V16283
AC Characteristics (1/3)
Parameter
Random Read or Write Cycle Time
Read Modify Write Cycle
Symbol
-60
-70
Unit Note
Min.
Max.
Min.
Max.
tRC
104
—
124
—
ns
tRWC
140
—
170
—
ns
tHPC
25
—
30
—
ns
tPRWC
70
—
74
—
ns
tRAC
—
60
—
70
ns
8, 14
Access Time from Column Address
tAA
—
30
—
35
ns
8, 14
Access Time from CAS
tCAC
—
15
—
20
ns
8, 15
Access Time from CAS Precharge
tCPA
—
35
—
40
ns
8, 15
Output Buffer Turn-off Delay
tOFF
0
15
0
17
ns
10
7
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write Cycle Time
Access Time from RAS
Transition Time (Rise and Fall)
tT
2
35
2
35
ns
RAS Precharge Time
tRP
40
—
50
—
ns
RAS Pulse Width
tRAS
60
10k
70
10k
ns
RAS Pulse Width (Fast Page Mode Only)
tRASP
60
100k
70
100k
ns
RAS Hold Time
tRSH
15
—
20
—
ns
CAS Hold Time
tCSH
45
—
55
—
ns
CAS Pulse Width
tCAS
10
10k
10
10k
ns
RAS to CAS Delay Time
tRCD
15
42
15
50
ns
14
RAS to Column Address Delay Time
tRAD
12
30
12
35
ns
14
Column Address to RAS Lead Time
tRAL
30
—
35
—
ns
CAS to RAS Precharge Time
tCRP
5
—
10
—
ns
CAS Precharge Time (Fast Page Mode)
tCP
10
—
10
—
ns
Row Address Set-up Time
tASR
0
—
0
—
ns
Row Address Hold Time
tRAH
10
—
10
—
ns
Column Address Set-up Time
tASC
0
—
0
—
ns
Column Address Hold Time
tCAH
10
—
10
—
ns
Column Address Hold Time referenced to RAS
tAR
50
—
55
—
ns
Read Command Set-up Time
tRCS
0
—
0
—
ns
Read Command Hold Time
tRCH
0
—
0
—
ns
11
Read Command Hold Time referenced to RAS
tRRH
0
—
0
—
ns
11
CAS "H" to RAS "H" Lead Time
tCRL
0
—
0
—
ns
RAS "H" to CAS "H" Lead Time
tRCL
0
—
0
—
ns
Data Output Hold after CAS Low
tCOH
3
—
3
—
ns
19
Write Command Set-up Time
tWCS
0
—
0
—
ns
13
Write Command Hold Time
tWCH
10
—
10
—
ns
Write Command Hold Time referenced to RAS
tWCR
50
—
55
—
ns
Write Command Pulse Width
tWP
10
—
10
—
ns
Write Command to RAS Lead Time
tRWL
15
—
15
—
ns
Write Command to CAS Lead Time
tCWL
15
—
15
—
ns
6/42
¡ Semiconductor
MSM54V16283
AC Characteristics (2/3)
Parameter
Data Set-up Time
Symbol
tDS
-60
-70
Min.
Max.
Min.
Max.
0
—
0
—
Unit Note
ns
12
12
Data Hold Time
tDH
10
—
12
—
ns
Data Hold Time referenced to RAS
tDHR
50
—
55
—
ns
RAS to WE Delay Time
tRWD
80
—
90
—
ns
13
Column Address to WE Delay Time
tAWD
50
—
55
—
ns
13
CAS to WE Delay Time
tCWD
35
—
40
—
ns
13
Data to CAS Delay Time
tDZC
0
—
0
—
ns
Data to TRG Delay Time
tDZO
0
—
0
—
ns
Access Time from TRG
tOEA
—
15
—
20
ns
Output Buffer Turn-off Delay from TRG
tOEZ
0
15
0
15
ns
TRG Command Hold Time
tOEH
10
—
10
—
ns
RAS Hold Time referenced to TRG
tROH
10
—
15
—
ns
CAS Set-up Time for CAS before RAS Cycle
tCSR
5
—
5
—
ns
CAS Hold Time for CAS before RAS Cycle
tCHR
10
—
10
—
ns
RAS Precharge to CAS Active Time
tRPC
0
—
0
—
ns
Refresh Period
tREF
—
8
—
8
ms
WE Set-up Time
tWSR
0
—
0
—
ns
WE Hold Time
tRWH
10
—
10
—
ns
DSF Set-up Time referenced to RAS
tFSR
0
—
0
—
ns
DSF Hold Time referenced to RAS (1)
tRFH
10
—
10
—
ns
DSF Hold Time referenced to RAS (2)
tFHR
50
—
55
—
ns
DSF Set-up Time referenced to CAS
tFSC
0
—
0
—
ns
DSF Hold Time referenced to CAS
tCFH
10
—
10
—
ns
Write Per Bit Mask Data Set-up Time
tMS
0
—
0
—
ns
Write Per Bit Mask Data Hold Time
tMH
10
—
10
—
ns
RAS Pulse Width (CAS before RAS Self-Refresh)
tRASS
100
—
100
—
ms
RAS Precharge Time (CAS before RAS Self-Refresh)
tRPS
120
—
140
—
ns
CAS Hold Time (CAS before RAS Self-Refresh)
tCHS
0
—
0
—
ns
TRG High Set-up Time
tTHS
0
—
0
—
ns
TRG High Hold Time
tTHH
10
—
10
—
ns
TRG Low Set-up Time
tTLS
0
—
0
—
ns
TRG Low Hold Time
tTLH
10
10k
10
10k
ns
TRG Low Hold Time referenced to RAS
tRTH
50
10k
60
10k
ns
TRG Low Hold Time referenced to Column Address
tATH
20
—
25
—
ns
TRG Low Hold Time referenced to CAS
tCTH
15
—
20
—
ns
7/42
¡ Semiconductor
MSM54V16283
AC Characteristics (3/3)
Parameter
Symbol
-60
-70
Min.
Max.
Min.
Max.
Unit Note
TRG to RAS Precharge Time
tTRP
40
—
50
—
ns
TRG Precharge Time
tTP
20
—
20
—
ns
RAS to First SC Delay Time (Read Transfer)
tRSD
60
—
70
—
ns
Column Address to First SC Delay Time
tASD
30
—
35
—
ns
CAS to First SC Delay Time (Read Transfer)
tCSD
20
—
20
—
ns
Last SC to TRG Lead Time
tTSL
5
—
5
—
ns
TRG to First SC Delay Time (Read Transfer)
tTSD
10
—
10
—
ns
Last SC to RAS Set-up Time (Serial Input)
tSRS
20
—
25
—
ns
Serial Output Buffer Turn-off Delay from RAS
tSDZ
10
30
10
40
ns
SC Cycle Time
tSCC
18
—
20
—
ns
SC Pulse Width (SC High Time)
tSC
5
—
5
—
ns
SC Precharge Time (SC Low Time)
tSCP
5
—
5
—
ns
Access Time from SC
tSCA
—
15
—
17
ns
9
Serial Output Hold Time from SC
tSOH
3
—
5
—
ns
19
Access Time from SE
tSEA
—
15
—
17
ns
9
SE Pulse Width
tSE
10
—
10
—
ns
SE Precharge Time
tSEP
10
—
10
—
ns
Serial Output Buffer Turn-off Delay from SE
tSEZ
0
15
0
15
ns
Split Transfer Set-up Time
tSTS
20
—
25
—
ns
Split Transfer Hold Time
tSTH
20
—
25
—
ns
SC-QSF Delay Time
tSQD
—
20
—
25
ns
TRG-QSF Delay Time
tTQD
—
20
—
25
ns
CAS-QSF Delay Time
tCQD
—
30
—
35
ns
RAS-QSF Delay Time
tRQD
—
70
—
75
ns
RAS to Serial Input Delay Time
tSDD
30
—
40
—
ns
Serial Input Set-up Time
tSDS
0
—
0
—
ns
Serial Input Hold Time
tSDH
10
—
10
—
ns
Serial Input to SE Delay Time
tSZE
0
—
0
—
ns
Serial Input to First SC Delay Time
tSZS
0
—
0
—
ns
Serial Write Enable Set-up Time
tSWS
0
—
0
—
ns
Serial Write Enable Hold Time
tSWH
10
—
10
—
ns
Serial Write Disable Set-up Time
tSWIS
0
—
0
—
ns
Serial Write Disable Hold Time
tSWIH
10
—
10
—
ns
10
10
8/42
¡ Semiconductor
Notes:
MSM54V16283
1. Exposure beyond the "Absolute Maximum Ratings" may cause permanent damage
to the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate.
4. These parameters depend on output loading. Specified values are obtained with the
output open.
5. An initial pause of 200 ms is required after power up followed by any 8 RAS cycles
(TRG = "high") and any 8 SC cycles before proper device operation is achieved.
In the case of using an internal refresh counter, a minimum of 8 CAS before RAS
cycles instead of 8 RAS cycles are required.
6. AC measurements assume tT = 5 ns.
7. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals.
Also, transition times are measured between VIH and VIL.
8. RAM port outputs are measured with a load equivalent to 1 TTL load and 50 pF.
DOUT reference levels : VOH/VOL = 2.0 V/0.8 V.
9. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF.
DOUT reference levels : VOH/VOL = 2.0 V/0.8 V.
10. tOFF (Max.), tOEZ (Max.), tSDZ (Max.) and tSEZ (Max.) define the time at which the
outputs achieve the open circuit condition, and are not referenced to output voltage
levels. This parameter is sampled and not 100% tested.
11. Either tRCH or tRRH must be satisfied for a read cycle.
12. These parameters are referenced to CAS leading edge of early write cycles, and to
WE leading edge in TRG controlled write cycles and read modify write cycles.
13. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters.
They are included in the data sheet as electrical characteristics only.
If tWCS ≥ tWCS (Min.), the cycle is an early write cycle, and the data out pin will
remain open circuit throughout the entire cycle; If tRWD ≥ tRWD (Min.), tCWD ≥ tCWD
(Min.) and tAWD ≥ tAWD (Min.), the cycle is a read modify write cycle, and the data
out will contain data read from the selected cell; If neither of the above sets of
conditions are satisfied, the condition of the data out is indeterminate.
14. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only: If tRCD is greater than the specified
tRCD (Max.) limit, then access time is controlled by tCAC.
15. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD
(Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD
(Max.) limit, then access time is controlled by tAA.
16. Input levels at the AC testing are 3.0 V/0 V.
17. Address (A0 - A8) may be changed two times or less while RAS = VIL.
18. Address (A0 - A8) may be changed once or less while CAS = VIH and RAS = VIL.
19. This is guaranteed by design. (tSOH/tCOH = tSCA/tCAC - output transition time)
This parameter is not 100% tested.
9/42
¡ Semiconductor
MSM54V16283
,,,
,
,
, ,
TIMING WAVEFORM
Read Cycle (Outputs Controlled by RAS)
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tRCD
CAS
tCAS
tCRL
tAR
tRAD
tASR
Address
tRAL
tASC
tRAH
Row
tCAH
Column
tFHR
tFSR
tRFH
tFSC
tCFH
DSF
tRCS
tRCH
WEL
tRRH
WEU
tCAC
tOFF
tAA
Open
DQ0 - 7
Valid Data
tRAC
Open
DQ8 - 15
Valid Data
tROH
tTHS
tTHH
tOEA
tOEZ
TRG
"H" or "L"
10/42
¡ Semiconductor
MSM54V16283
Read Cycle (Outputs Controlled by CAS)
tRC
tRAS
RAS
tRP
,
,,
tCSH
tCRP
CAS
tRSH
tCAS
tRCD
tRCL
tAR
tRAD
tASR
Address
tRAL
tRAH
tASC
Row
tCAH
Column
tFHR
tFSR
DSF
tRFH
tFSC
tCFH
tRCS
WEL
tRRH
tRCH
WEU
tCAC
tOFF
tAA
DQ0 - 7
Open
Valid Data
tRAC
DQ8 - 15
Open
Valid Data
tROH
tTHS
TRG
tTHH
tOEA
tOEZ
"H" or "L"
11/42
¡ Semiconductor
MSM54V16283
,
,,
,
,
,
Extended Page Mode Read Cycle
tRASP
tRP
RAS
tCSH
tCRP
tHPC
tRCD
CAS
tCAS
tCP
tRSH
tCAS
tCP
tAR
tRAD
tASR
Address
tCAS
tRAL
tRAH
tASC
Row
tCAH
tASC
Column
tCAH
tASC
Column
tCAH
Column
tFHR
tFSR
tRFH
tFSC
tCFH
tFSC
tCFH
tFSC
tCFH
DSF
tRCS
tRCS
tRCH
tRCS
tRRH
tRCH
WEL
tRCH
WEU
tCAC
tAA
DQ0 - 7
Open
Open
tTHS
tTHH
tCAC
tCOH
tCOH
Valid Data
tRAC
DQ8 - 15
tCAC
Valid
Data
tAA
tAA
tCPA
tCPA
Valid Data
tOEA
Valid
Data
Valid
Data
tOEZ
Valid
Data
tOFF
Valid Data
Valid Data
tOEA
TRG
"H" or "L"
12/42
¡ Semiconductor
MSM54V16283
Write Cycle Function Table
RAS Falling Edge
Code
A
C
DSF WEL/U
CAS Falling Edge
D
B
E
Function
DQ
DSF
DQ
RWM
0
0
Write Mask
0
Valid Data
BWM
0
0
Write Mask
1
Column Mask
Masked Block Write (New/Old)
FWM
1
0
Write Mask
X
X
Masked Flash Write (New/Old)
RW
0
1
X
0
Valid Data
Masked Write (New/Old)
Normal Write
BW
0
1
X
1
Column Mask
Block Write
LMR
1
1
X
0
Write Mask Data
Load Mask Register
LCR
1
1
X
1
Color Data
Load Color Register
RAS Falling Edge
MODE
NEW MASK
PERSISTENT MASK
NO MASK
WEL
WEU
DQ0 - 7
DQ8 - 15
0
0
Mask
Mask
0
1
Mask
Mask
1
0
Mask
Mask
0
0
—
—
0
1
—
—
1
0
—
—
1
1
—
—
WRITE MASK DATA: "Low" = Mask, "High" = No Mask
Column Mask Data
Lower Byte
Upper Byte
DQ0 - 15
Column Mask Data
DQ0
Column 0 (A0 = 0, A1 = 0, A2 = 0)
DQ1
Column 1 (A0 = 1, A1 = 0, A2 = 0)
DQ2
Column 2 (A0 = 0, A1 = 1, A2 = 0)
DQ3
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Low : Mask
DQ4
Column 4 (A0 = 0, A1 = 0, A2 = 1)
High : No Mask
DQ5
Column 5 (A0 = 1, A1 = 0, A2 = 1)
DQ6
Column 6 (A0 = 0, A1 = 1, A2 = 1)
DQ7
Column 7 (A0 = 1, A1 = 1, A2 = 1)
DQ8
Column 0 (A0 = 0, A1 = 0, A2 = 0)
DQ9
Column 1 (A0 = 1, A1 = 0, A2 = 0)
DQ10
Column 2 (A0 = 0, A1 = 1, A2 = 0)
DQ11
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Low : Mask
DQ12
Column 4 (A0 = 0, A1 = 0, A2 = 1)
High : No Mask
DQ13
Column 5 (A0 = 1, A1 = 0, A2 = 1)
DQ14
Column 6 (A0 = 0, A1 = 1, A2 = 1)
DQ15
Column 7 (A0 = 1, A1 = 1, A2 = 1)
13/42
¡ Semiconductor
MSM54V16283
Early Write Cycle
tRC
tRAS
RAS
tRP
,
,,
,
,,
tCSH
tCRP
CAS
tAR
tRAD
tASR
Address
tRSH
tCAS
tRCD
tRAH
tRAL
tASC
Row
tCAH
Column
tFHR
tFSR
DSF
tRFH
tFSC
A
tCFH
B
tCWL
tWSR
WEL
tRWL
tRWH
tWP
C
tWCR
tWSR
WEU
tRWH
tWCS
tWCH
C
tDHR
tMS
DQ0 - 7
tMH
tDS
D
tDH
E
tDHR
tMS
DQ8 - 15
D
tTHS
TRG
tMH
tDS
tDH
E
tTHH
"H" or "L"
14/42
¡ Semiconductor
MSM54V16283
Late Write Cycle
tRC
tRAS
RAS
tRP
,
,,
,
,,
,,,
tCSH
tCRP
CAS
tAR
tRAD
tRAH
tASR
Address
tRSH
tCAS
tRCD
tRAL
tASC
Row
tCAH
Column
tFHR
tRFH
tFSR
DSF
tFSC
A
tCFH
B
tCWL
tRWH
tWSR
WEL
tRWL
tRCS
tWP
C
tWCR
tRWH
tWSR
WEU
tRCS
C
tDHR
tMH
tMS
DQ0 - 7
tDS
D
tDH
E
tDHR
tMH
tMS
DQ8 - 15
D
tTHS
TRG
tDS
tDH
E
tOEH
"H" or "L"
15/42
¡ Semiconductor
MSM54V16283
Read Modify Write Cycle
tRWC
tRAS
RAS
tRP
,
,,
,,
,
,,,
tCSH
tCRP
CAS
tAR
tRAD
tRAL
tRAH
tASR
Address
tRSH
tCAS
tRCD
tASC
Row
Column
tAWD
tFHR
tRFH
tFSR
DSF
tCAH
tFSC
A
tCFH
B
tCWL
tRWH
tWSR
WEL
tRCS
tCWD
tRWL
tWP
C
tRWD
tRWH
tWSR
WEU
C
tRAC
tDZC
tDS
Valid
Data
D
tMH
tMS
DQ8 - 15
tCAC
tMH
tMS
DQ0 - 7
tRCS
tDH
E
tDS
Valid
Data
D
tDH
E
tDZO
tTHS
TRG
tTHH
tOEA tOEZ
tOEH
"H" or "L"
16/42
¡ Semiconductor
MSM54V16283
Fast Page Mode Early Write Cycle
tRASP
tRP
RAS
tCSH
tCRP
tHPC
tCAS
tRCD
CAS
tCP
tCAS
tRSH
tCP
tCAS
tAR
tRAL
tRAD
,,
,
,
,,,
tASR tRAH
Address
tASC
Row
tCAH
tASC
Column
tCAH
tASC
Column
tCAH
Column
tFHR
tFSR
DSF
tRFH
tFSC tCFH
A
tFSC
B
tCFH
tFSC
B
tCWL
tCFH
B
tCWL
tCWL
tWSR tRWH
tWP
WEL
tWP
tWP
C
tWSR tRWH
WEU
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
C
tMS
DQ0 - 7
tMH
tDS
D
tMS
DQ8 - 15
tDS
E
tMH
D
tTHS
tDH
tDS
tDS
E
tDH
E
tDH
tDS
E
tDH
E
tDH
tDS
tDH
E
tTHH
TRG
"H" or "L"
17/42
¡ Semiconductor
MSM54V16283
Fast Page Mode Read Modify Write Cycle
tRASP
tRP
RAS
tCSH
tCRP
tPRWC
tCAS
tRCD
CAS
tCP
tRSH
tCAS
tCP
tCAS
tAR
tRAL
tRAD
,
,
,
,
tASR
Address
tRAH
tASC
tASC
tCAH
Row
Column
tASC
tCAH
Column
tCAH
Column
tFHR
tFSR
DSF
tRFH
A
B
tWSR
WEL
tFSC
tFSC tCFH
B
tCWL
tAWD
tRWH
tFSC
tCFH
tCFH
B
tCWL
tAWD
tCWL
tAWD
C
tWP
tWSR
WEU
tRWH
tRCS
tWP
tWP
tCWD
tCWD
tCWD
tCAC
tCAC
tCAC
C
DQ0 - 7
tMH
tMS
tDH
tAA
tDS
tDS
Out
In
Out
In
Out
In
Out
In
Out
In
Out
In
tMH
D
tOEZ
tTHS
tDH
tAA
tDS
D
DQ8 - 15
tDH
tAA
tMS
tTHH
tOEA
tOEZ
tOEA
tOEZ
tOEA
TRG
"H" or "L"
18/42
¡ Semiconductor
MSM54V16283
RAS Only Refresh Cycle
tRC
tRAS
RAS
tRP
,
,,,
,
,,,
tCRP
CAS
tASR
Address
WEL/U
DQ0 - 15
tRFH
Open
tTHS
TRG
tRAH
Row
tFSR
DSF
tRPC
tTHH
"H" or "L"
19/42
¡ Semiconductor
MSM54V16283
CAS before RAS Refresh Cycle
tRC
tRP
RAS
tCSR
tCHR
tRAH
A
tRFH
tFSR
DSF
B
tRWH
tWSR
WEL/U
tRPC
Inhibit Falling Transition
tASR
Address
tRP
,,,,
tRPC
CAS
tRAS
C
tOFF
DQ0 - 15
TRG
Open
"H" or "L"
Note:
The type of CBR operations are determined by the logic states of "A", "B" and "C".
CBR Cycle Function Table
Code
RAS Falling Edge
Function
A
B
C
CBRR
X
0
1
CBR Refresh (Reset All Options)
CBRS
STOP Address
1
0
CBR Refresh (Set STOP Address)
CBRN
X
1
1
CBR Refresh (No Reset Options)
20/42
¡ Semiconductor
MSM54V16283
CAS before RAS Self-Refresh Cycle
tRP
tRASS
RAS
tRPS
tRPC
tRPC
tCSR
tCHS
CAS
tOFF
DQ0 - 15
Open
"H" or "L"
Note:
Address, DSF, WEL, WEU, TRG = "H" or "L"
21/42
¡ Semiconductor
MSM54V16283
Hidden Refresh Cycle
tRC
tRAS
RAS
,,
,
,,
tCRP
CAS
tRCD
tRSH
tAR
tRAD
tASR
Address
tRAS
tRP
tRAH
tCHR
tRAL
tASC
Row
tASR
tCAH
Column
tRAH
A
tFHR
tFSR
DSF
tRFH
tFSC
tFSR
tCFH
B
tWSR
tRCS
WEL/U
tRFH
tRWH
C
tRRH
tCAC
tOFF
tAA
DQ0 - 15
Open
Valid Data
tRAC
tTHS
TRG
tTHH
tOEA
tOEZ
"H" or "L"
Note:
The type of CBR operations are determined by the logic states of "A", "B" and "C".
22/42
¡ Semiconductor
MSM54V16283
Read Transfer 1
tRC
tRAS
RAS
tRP
,
,,,
,
tCSH
tRSH
tCAS
tRCD
CAS
tAR
tRAD
Row
tFSR
DSF
tASC
tRAH
tASR
Address
tRAL
tCAH
SAM Start
tRFH
tWSR tRWH
WEL/U
tASD
tCSD
DQ0 - 15
tRSD
Open
tTRP
tTLS
TRG
tTLH
tTP
tSC
tTSD
tSCP
tSRS
SC
tSCA
tSZS
tSIH
tSCA
tSOH
Data Out
Din
tRQD
QSF
tSC
Note 2
tSIS
SDQ0 - 15
tSCC
tCQD
Note 3
tTQD
Note 3
"H" or "L"
Note 1: SE = "L"
Note 2: There must be no rising transitions
Note 3: QSF = "L"-- Lower SAM (0 - 255) is active
QSF = "H"-- Upper SAM (256 - 511) is active
23/42
¡ Semiconductor
MSM54V16283
Read Transfer 2 (Real Time Read Transfer)
tRC
tRAS
RAS
tRP
,
,,,
tCSH
tRSH
tCAS
tRCD
CAS
tAR
tRAD
Address
Row
tFSR
DSF
tASC
tRAH
tASR
tRAL
tCAH
SAM Start
tRFH
tWSR tRWH
WEL/U
tCTH
tATH
DQ0 - 15
Open
tTRP
tTLS
TRG
tTP
tRTH
tSCC
tSCP
SC
tTSL
tSC
tTSD
tSCA
tSOH
SDQ0 - 15
tSCA
tSOH
Data Out
Data Out
Data Out
Data Out
tTQD
QSF
Note 2
Note 2
"H" or "L"
Note 1: SE = "L"
Note 2: QSF = "L"-- Lower SAM (0 - 255) is active
QSF = "H"-- Upper SAM (256 - 511) is active
24/42
¡ Semiconductor
MSM54V16283
Split Read Transfer
tRC
tRAS
RAS
tRP
,
,,,
tCSH
tRSH
tCAS
tRCD
CAS
tAR
tRAD
tASR
Address
tASC
Row
tFSR
DSF
tRAH
tRAL
tCAH
SAM Start Sj
tRFH
tWSR tRWH
WEL/U
tCTH
tATH
DQ0 - 15
tTLS
TRG
Open
tRTH
tTLH
tSCC
tSTS
tSCP
SC
SDQ0 - 15
STOP i
tSCA
tSOH
Data Out
tSC
Si
tSCA
tSOH
Data Out
Data Out
STOP
j-1
STOP j
Data Out
Data Out
tSQD
QSF
Note 2
Sj
Data Out
tSQD
Note 2
Note 2
"H" or "L"
Note 1: SE = "L"
Note 2: QSF = "L"-- Lower SAM (0 - 255) is active
QSF = "H"-- Upper SAM (256 - 511) is active
Note 3: Si is the SAM start address in before SRT
Note 4: STOP i and STOP j are programmable stop addresses
25/42
¡ Semiconductor
MSM54V16283
Masked Write Transfer
tRC
tRAS
RAS
tRP
,
,,,
tCSH
tRSH
tCAS
tRCD
CAS
tAR
tRAD
tASR
Address
tASC
tRAH
Row
tFSR
DSF
tRAL
tCAH
SAM Start
tRFH
tWSR tRWH
WEL/U
tMS
DQ0 - 15
tCSD
tMH
Open
Mask Data
tRSD
tTLS
TRG
tTLH
tSRS
tSCC
tSC
SC
tSCP
tSC
Note 2
tSDZ
tSDS
tSOH
SDQ0 - 15
Dout
Dout
tSDH
tSDS
Data In
tSDD
tSDH
Data In
tCQD
tRQD
QSF
Note 3
Note 3
"H" or "L"
Note 1: SE = "L"
Note 2: There must be no rising transitions
Note 3: QSF = "L"-- Lower SAM (0 - 255) is active
QSF = "H"-- Upper SAM (256 - 511) is active
26/42
¡ Semiconductor
MSM54V16283
Masked Split Write Transfer
tRC
tRAS
RAS
tRP
,
,,,
tCSH
tRSH
tCAS
tRCD
CAS
tAR
tRAD
tASR
Address
tASC
tRAH
Row
tFSR
DSF
tRAL
tCAH
SAM Start Sj
tRFH
tWSR tRWH
WEL/U
tMS
DQ0 - 15
Mask Data
tTLS
TRG
tCTH
tATH
tMH
Open
tRTH
tTLH
tSCC
tSTS
tSCP
SC
STOP i
Si
tSDS
SDQ0 - 15
Data In
tSC
tSDH
Data In
STOP
j-1
tSDS
Note 2
Sj
tSDH
Data In
Data In
tSQD
QSF
STOP j
Data In
Data In
tSQD
Note 2
Note 2
"H" or "L"
Note 1: SE = "L"
Note 2: QSF = "L"-- Lower SAM (0 - 255) is active
QSF = "H"-- Upper SAM (256 - 511) is active
Note 3: Si is the SAM start address in before SWT
Note 4: STOP i and STOP j are programmable stop addresses
27/42
¡ Semiconductor
MSM54V16283
Serial Read Cycle
tSEP
SE
tSCC
tSC
SC
tSCA
tSCP
tSOH
SDQ0 - 15
tSEA
tSEZ
Data Out
Data
tSCA
tSCA
tSOH
tSOH
Data
Data Out
Data Out
Serial Write Cycle
tSEP
SE
tSCC
tSC
SC
tSWH
Data In
tSWIH
tSWS
tSCP
tSDS
SDQ0 - 15
tSWIS
tSDH
Data In
tSZE
tSDS
tSDH
Data In
Data In
"H" or "L"
28/42
¡ Semiconductor
MSM54V16283
PIN FUNCTIONS
Address Input: A0 - A8
The 18 address bits decode 16 bits of the 4,194,304 locations in the MSM54V16283 memory array.
The address bits are multiplexed to 9 address input pins (A0 - A8) as standard DRAM. 9 row
address bits are latched at the falling edge of RAS. The following 9 column address bits are
latched at the falling edge of CAS.
Row Address Strobe: RAS
RAS is a basic RAM control signal. The RAM port is in standby mode when the RAS level is
"high". As the standard DRAM’s RAS signal function, RAS is the control input that latches the
row address bits, and a random access cycle begins at the falling edge of RAS.
In addition to the conventional RAS signal function, the level of the input signals CAS, TRG,
WEL, WEU and DSF at the falling edge of RAS, determines the MSM54V16283 operation mode.
Column Address Strobe: CAS
As the standard DRAM’s CAS signal function, CAS is the control input signal that latches the
column address input, and the state of the special function input DSF to select in conjunction with
the RAS control, either read/write operations or the special block write feature on the RAM port
when the DSF is held "low" at the falling edge of RAS.
CAS also acts as a RAM port output enable signal.
Data Transfer/Output Enable: TRG
TRG is also a control input signal having multiple functions. As the standard DRAM’s OE signal
function, TRG is used as an output enable control when TRG is "high" at the falling edge of RAS.
In addition to the conventional OE signal function, a data transfer operation is started between
the RAM port and the SAM port when TRG is "low" at the falling edge of RAS.
Write Per Bit/Write Enable: WEL and WEU
WEL and WEU are control input signals having multiple functions. As the standard DRAM’s WE
signal function, these are used to write data into the memory on the RAM port when WEL and
WEU are both "high" at the falling edge of RAS.
In addition to the conventional WE signal function, both WEL and WEU determine the write-perbit function, when either WEL or WEU is "low" at the falling edge of RAS during RAM port
operations.
The WEL and WEU also determine the direction of data transfer between the RAM and SAM.
When both WEL and WEU are "high" at the falling edge of RAS, the data is transferred from RAM
to SAM (read transfer). When either WEL or WEU is "low" at the falling edge of RAS, the data
is transferred SAM to RAM (write transfer).
29/42
¡ Semiconductor
MSM54V16283
Write Mask Data/Data Input and Output: DQ0 - DQ15
In conventional write-per bit mode, the DQ pins function as mask data at the falling edge of RAS.
Data is written only to high DQ pins. Data on low DQ pins is masked and internal data is retained.
After that, they function as input/output pins similar to a standard DRAM.
In persistent write-per-bit mode, DQ pins do not consider the falling edge of RAS. The mask data
is determined in the mask register load cycle.
Serial Clock: SC
SC is a main serial cycle control input signal. All operations of the SAM port are synchronized
with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In
a serial read cycle, the output data becomes valid on the SDQ pins after the maximum specified
serial access time tSCA from the rising edge of SC.
In a serial write cycle, data on SDQ pins at the rising edge of SC are fetched into the SAM register.
Serial Enable: SE
The SE is a serial access enable control and serial read/write control signal. In a serial read cycle,
SE is used as an output control. In a serial write cycle, SE is used as a write enable control. When
SE is "high", serial access is disabled. However, the serial address pointer location is still
incremented when SC is clocked even when SE is "high".
Special Function Input: DSF
The DSF is latched at the falling edge of RAS and CAS. It allows for the selection of several RAM
ports and transfer operating modes. In addition to the conventional multiport DRAM, the special
functions consisting of flash write, block write, load/read color register, and split read/write
transfer can be invoked.
Special Function Output: QSF
QSF is an output signal, which during split register mode indicates which half of the split SAM
is being accessed. QSF "low" indicates that the lower split SAM (0 - 255) is being accessed. QSF
"high" indicates that the upper SAM (256 - 511) is being accessed.
QSF is enabled by SE. When SE is "high", QSF is in high impedance.
Serial Input/Output: SDQ0 - SDQ15
Serial input/output mode is determined by the most recent read or write transfer cycle. When
a read transfer cycle is performed, the SAM port is in the output mode. When a write or pseudo
write transfer cycle is performed, the SAM port is switched from output mode to input mode.
30/42
¡ Semiconductor
MSM54V16283
OPERATION MODES
Table-1 shows the function truth table for a listing of all available RAM ports, and transfer
operations of the MSM54V16283.
The RAM port and data transfer operations are determined by the state of CAS, TRG, WEL, WEU
and DSF at the falling edge of RAS, and by the level of DSF at the falling edge of CAS.
Table-1. Function Truth Table
RASØ
Code
CBRR
CASØ Address
W/IO
CAS TRG WE DSF DSF RASØ CASØ RASØ
0
*
1
0
—
*
*
*
CAS
/WEØ
*
Write Pers.
Register
Mask W.M. WM Color
—
Reset Reset
—
Function
CBR Refresh
(Register Reset)
CBR Refresh
CBRS
0
*
0
1
— STOP
*
*
*
—
—
—
—
CBRN
0
*
1
1
—
*
*
*
—
—
—
—
CBR Refresh (No Reset)
ROR
1
1
*
0
— Row
—
*
—
—
—
—
—
RAS Only Refresh
MWT
1
0
0
0
*
Row TAP WM1
*
Yes
—
Masked Write Transfer
MSWT
1
0
0
1
*
Row TAP WM1
*
Yes
RT
1
0
1
0
*
Row TAP
*
*
SRT
1
0
1
1
*
Row TAP
*
*
RWM
1
1
0
0
0
Row Column WM1 Din,Dout Yes
BWM
1
1
0
0
1
Row
FWM
1
1
0
1
*
Row
RW
1
1
1
0
0
Row Column
BW
LMR
LCR
Notes:
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
*
Row
Row
Row
Column
A3c - 8c
*
Column
A3c - 8c
*
*
WM1
Column
Select
WM1 —
*
*
*
*
Din,Dout
Column
Select
Mask
Data
Color
Data
No/ Load
Yes
Use
No/ Load
—
(Stop Register Set)
Masked Split
Yes
Use
—
—
—
—
Read Transfer
—
—
—
—
Split Read Transfer
Yes
Yes
No/ Load
Yes
Use
No/ Load
Yes
Use
No/ Load
—
Use
Use
Yes
Use
No
No
—
—
No
No
—
Use
—
Set Load
—
—
—
—
Load
Write Transfer
Read/Write
(New/Old Mask)
Masked Block Write
(New/Old)
Masked Flash Write
(New/Old)
Read/Write
(No Mask)
Block Write
(No Mask)
Load Mask Register
(Old Mask Set)
Load Color Register
1. With CBRS and SAM operations use stop register.
2. After LMR, RWM, BWM, FWM and MSWT, use the old mask which can be reset by
CBRR.
31/42
¡ Semiconductor
MSM54V16283
If the DSF is "high" at the falling edge of RAS, special functions such as split transfer, flash write,
load mask register, load color register, CBRS and CBRN can be invoked.
If the DSF is "low" at the falling edge of RAS and "high" at the falling edge of CAS, the block write
feature can be invoked.
RAM PORT OPERATION
Extended RAM Read Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L"
CAS falling edge --- DSF = "L"
The MSM54V16283 offers an accelerated page mode cycle (EXTENDED PAGE MODE) by
eliminating output disable from CAS "high", and it allows CAS precharge time (tCP) to occur
without the output data becoming invalid. This new data out operates (Extended data out) as any
RAM read or Page Mode Read, except data will be held valid after CAS goes "high", as long as
RAS is "low".
RAM Write Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L"
CAS falling edge --- DSF = "L"
1) Write cycle with no mask: RAS falling edge -- WEL = WEU = "H"
If either WEL or WEU is set "low" at the falling edge of CAS after RAS goes "low", a write cycle
is excuted. If either WEL or WEU is set "low" before the CAS falling edge, this cycle becomes an
early write cycle, and all DQ pins attain high impedance.
If either WEL or WEU is "low" when CAS goes "low", the write affects only those corresponding
8 bits with the latched data.
If both WEL and WEU are set "low" after the CAS falling edge, this cycle becomes a late write
cycle, and all 16 data are latched on the falling edge of WEL or WEU.
Byte write occurs if either WEL or WEU falls during the cycle. DQ pins don't achieve high
impedance in this cycle, so data should be entered with TRG in "high".
2) Write cycle with mask: RAS falling edge -- WEL or WEU = "L"
If either WEL or WEU is set "low" at the falling edge of RAS, two modes of mask write can be
invoked.
#1 In new mask mode mask data is loaded and used. The mask data on DQ0 - DQ15 is latched
into the write mask register at the falling edge of RAS. When the mask data is low, writing is
inhibited into the RAM and the mask data is high, data is written into the RAM. This mask data
is in effect during the RAS cycle. In page mode cycle the mask data is retained during page access.
#2 If a load mask register cycle (LMR) has been performed, the mask data is not loaded from DQ
pins, and the mask data stored in the mask register is persistently used.
This operation is known as persistent write mask, set by LMR and reset by CBRR.
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Load/Read Color Register:
MSM54V16283
RAS falling edge --- CAS = TRG = WEL = WEU = DSF = "H"
CAS falling edge --- DSF = "H"
The MSM54V16283 is provided with an on-chip 16-bit color register for use during the flash write
or block write operation. Each bit of the color register corresponds to one of the DRAM I/O
blocks.
The data presented on the DQi lines is subsequently latched into the color register at the falling
edge of either CAS or WE whichever occurs later.
The read color register cycle is activated by holding both WEL and WEU "high" at the falling edge
of CAS, and throughout the remainder of the cycle. The data in the color register becomes valid
on the DQi lines after the specified access times from RAS and TRG are satisfied.
During the load/read color register cycle, the memory cells on the row address latched at the
falling edge of RAS are refreshed.
Load/Read Mask Register:
RAS falling edge --- CAS = TRG = WEL = WEU = DSF = "H"
CAS falling edge --- DSF = "L"
The MSM54V16283 is provided with an on-chip 16-bit mask register for use during the mask
write cycle, flash write cycle, block write cycle, masked write transfer, and masked split write
transfer. Each bit of the mask register corresponds to one of the DRAM I/O blocks.
The data presented on the DQi lines is subsequently latched into the mask register at the falling
edge of either CAS or WE whichever occurs later.
The read mask register cycle is activated by holding both WEL and WEU "high" at the falling edge
of CAS, and throughout the remainder of the cycle. The data in the mask register becomes valid
on the DQi lines after the specified access times from RAS and TRG are satisfied.
During the load/read mask register cycle, the memory cells on the row address latched at the
falling edge of RAS are refreshed.
Flash Write: RAS falling edge --- CAS = TRG = DSF = "H", WEL = WEU = "L"
Flash write allows for the data in the color register to be written into all the memory locations of
a selected row.
Each bit of the color register corresponds to one of the DRAM I/O blocks. The flash write
operation can be selectively controlled on an I/O basis in the same manner as the write per bit
operation. The mask data is the same as that of a RAM write cycle.
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MSM54V16283
Block Write: RAS falling edge --- CAS = TRG = "H", DSF = "L"
CAS falling edge --- DSF = "H"
Block write allows for the data in the color register to be written into 8 consecutive column
address locations, starting from a selected column address in a selected row.
The block write operation can be selectively controlled on an I/O basis, and a column mask
capability is also available. This function is implemented as lower byte and upper byte. During
a block write cycle, the 3 least significant column address locations (A0C, A1C and A2C) are
internally controlled, and only the 6 most significant column addresses (A3C - A8C) are latched
at the falling edge of CAS.
1) No mask block write: WEL and WEU "high" at the falling edge of RAS
The data on 16 DQ pins is cleared by the data of the color register.
2) Masked block write: WEL or WEU "low" at the falling edge of RAS
The mask data is the same as that of a RAM write cycle. (new mask and persistent mask)
Bit 0
Bit 15
Color Register
11001110
01110011
I/O Mask
11111010
01101011
Column Mask
10010011
00111100
Lower Byte
Upper Byte
Column 7
1
1
0
0
1
*
1
*
*
*
*
*
*
*
*
*
Column 6
1
1
0
0
1
*
1
*
*
*
*
*
*
*
*
*
Column 5
*
*
*
*
*
*
*
*
*
1
1
*
0
*
1
1
Column 4
*
*
*
*
*
*
*
*
*
1
1
*
0
*
1
1
Column 3
1
1
0
0
1
*
1
*
*
1
1
*
0
*
1
1
Column 2
*
*
*
*
*
*
*
*
*
1
1
*
0
*
1
1
Column 1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Column 0
1
1
0
0
1
*
1
*
*
*
*
*
*
*
*
*
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
8 Column ¥ 8 DQ (Upper Byte)
DQ0
8 Column ¥ 8 DQ (Lower Byte)
Note : Location "*" can not be loaded.
Example of Block Write
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MSM54V16283
SAM PORT OPERATION
Single Register Mode
High speed serial read or write operations can be performed through the SAM port independent
of the RAM port operation, except during read/write transfer cycles.
The preceding transfer operation determines the direction of data flow through the SAM port.
If the preceding transfer is a read transfer, the SAM port is in the output mode. If the preceding
transfer is write transfer, the SAM port is in the input mode.
Serial data can be read out of the SAM after a read transfer has been performed. The data is shifted
out of the SAM starting at any of the 512 bits locations.
The TAP location corresponds to the column address selected at the falling edge of CAS during
the read or write transfer cycle. The SAM registers are configured as a circular data register. The
data is shifted out sequentially. It starts from the selected TAP location at the most significant bit
(511), then wraps around to the least significant bit (0).
Split Register Mode
In split register mode data can be shifted into or out of one half of the SAM, while a split read or
split write transfer is being performed on the other half of the SAM.
Conventional (non split) read, or write transfer cycle must precede any split read or split write
transfers. The split read and write transfers will not change the SAM port mode set by the
preceding conventional transfer operation. In the split register mode, serial data can be shifted
in or out of one of the split SAM registers, starting from any at the 256 TAP locations, excluding
the last address of each split SAM the data is shifted in or out sequentially starting from the
selected TAP location at the most significant bit (255 or 511) of the first split SAM, and then the
SAM pointer moves to the TAP location selected for the second split SAM to shift data in or out
sequentially, starts from this TAP location at the most significant bit (511 or 255), and finally
wraps around to the least significant bit.
TAP
0
1
2
TAP
255
256 257
511
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MSM54V16283
DATA TRANSFER OPERATIONS
Upper SAM
256 ¥ 16
256 ¥ 256 ¥ 16
Memory
Array
Lower SAM
256 ¥ 16
Upper SAM
256 ¥ 16
256 ¥ 256 ¥ 16
Memory
Array
Serial Decoder
256 ¥ 256 ¥ 16
Memory
Array
Lower SAM
256 ¥ 16
The MSM54V16283 features two types of bidirectional data transfer capability between RAM
and SAM.
1) Conventional (non split) transfer: 512 words by 16 bits of data can be loaded from RAM to
SAM (Read transfer), or from SAM to RAM (Write transfer).
2) Split transfer: 256 words by 16 bits of data can be loaded from the lower/upper half of the
RAM to the lower/upper half of the SAM (Split read transfer), or from the lower/upper half
of SAM to the lower/upper half of RAM (Split write transfer).
The conventional transfer and split transfer modes are controlled by the DSF input signal.
Data transfer is invoked by holding the TRG signal "low" at the falling edge of RAS.
The MSM54V16283 supports 4 types of transfer operations: Read transfer, Split read transfer,
Write transfer and Split write transfer as shown in the truth table. The type of transfer operation
is determined by the state of CAS, WEL, WEU and DSF latched at the falling edge of RAS. During
conventional transfer operations, the SAM port is switched from input to output mode (Read
transfer), or output to input mode (Write transfer). It remains unchanged during split transfer
operation (Split read transfer or Split write transfer).
Both RAM and SAM are divided by the most significant row address (AX8), as shown in Figure
1. Therefore, no data transfer between AX8 = 0 side RAM and AX8 = 1 side RAM can be provided
through the SAM. Care must be taken if the split read transfer on AX8 = 1 side (or AX8 = 0 side)
is provided after the read transfer or the split read transfer, is provided on AX8 = 0 side (or AX8
= 1 side).
256 ¥ 256 ¥ 16
Memory
Array
AX8 = 0
AX8 = 1
SAM I/O Buffer
SDQ0 - 15
Figure 1. RAM and SAM Configuration
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MSM54V16283
Read Transfer: RAS falling edge --- CAS = WEL = WEU = "H", TRG = DSF = "L"
Read transfer consists of loading a selected row of data from the RAM into the SAM register. A
read transfer is invoked by holding CAS "high", TRG "low", WEL and WEU "high", and DSF "low"
at the falling edge of RAS. The row address selected at the falling edge of RAS determines the
RAM row to be transferred into the SAM. The transfer cycle is completed at the rising edge of
TRG. When the transfer is completed, the SAM port is set into the output mode. In a read/real
time read transfer cycle, the transfer of a new row of data is completed at the rising edge of TRG,
and this data becomes valid on the SDQ lines after the specified access time tSCA from the rising
edge of the subsequent SC cycles. The start address of the serial pointer of the SAM is determined
by the column address selected at the falling edge of CAS. In a read transfer cycle (which is
preceded by a write transfer cycle), SC clock must be held at a constant VIL or VIH after the SC
high time has been satisfied. A rising edge of the SC clock must not occur until after the specified
delay tTSD from the rising edge of TRG.
In a real time read transfer cycle (which is preceded by another read transfer cycle), the previous
row data appears on the SQD lines until the TRG signal goes "high", and the serial access time
tSCA for the following serial clock is satisfied. This feature allows for the first bit of the new row
of data to appear on the serial output as soon as the last bit of the previous row has been strobed
without any timing loss. To make this continuous data flow possible, the rising edge of TRG must
be synchronized with RAS, CAS, and the subsequent rising edge of SC (tRTH, tCTH and tTSL/tTSD
must be satisfied).
Masked Write Transfer: RAS falling edge --- CAS = "H", TRG = DSF = "L"
WEL or WEU = "L"
Write transfer cycle consists of loading the content of the SAM register into a selected row of the
RAM. This write transfer is the same as a mask write operation in RAM, so new and persistent
(old) mask modes can be supported. (Masked write transfer)
If the SAM data to be transferred must first be loaded through the SAM, a Masked write transfer
operation (all DQ pins "low" at falling edge of RAS) must precede the write transfer cycles. A
masked write transfer is invoked by holding CAS "high", TRG "low", WEL or WEU "low", and
DSF "low" at the falling edge of RAS. The row address selected at the falling edge of RAS
determines the RAM row address into which the data will be transferred. The column address
selected at the falling edge of CAS determines the start address of the serial pointer of the SAM.
After the write transfer is completed, the SDQ lines are set in the input mode so that serial data
synchronized with the SC clock can be loaded.
When consecutive write transfer operations are performed, new data must not be written into
the serial register until the RAS cycle of the preceding write transfer is completed. Consequently,
the SC clock must be held at a constant VIL or VIH during the RAS cycle. A rising edge of the SC
clock is only allowed after the specified delay tCSD from the falling edge of the CAS, at which time
a new row of data can be written in the serial register.
Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to the
other address of RAM by write transfer cycle. However, the address to write data must be the
same as that of the read transfer cycle (row address AX8).
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¡ Semiconductor
MSM54V16283
Split Data Transfer and QSF
The MSM54V16283 features a bidirectional split data transfer capability between the RAM and
SAM. During split data transfer operation, the serial register is split into two halves which can
be controlled independently. Split read or split write transfer operation can be performed to or
from one half of the serial register, while serial data can be shifted into or out of the other half of
the serial register. The most significant column address location (A8C) is controlled internally to
determine which half of the serial register will be reloaded from the RAM. QSF is an output
which indicates which half of the serial register is in an active state. QSF changes state when the
last SC clock is applied to active split SAM.
Split Read Transfer: RAS falling edge --- CAS = WEL = WEU = DSF = "H", TRG = "L"
The MSM54V16283 supports two types of split register operation.
#1 Normal split register operation
#2 Boundary split register operation using programmable SAM stops described later.
Normal split read transfer consists of loading 256 words by 16 bits of data from a selected row
of the split RAM into the corresponding non-active split SAM register. Serial data can be shifted
out from the other half of the split SAM register simultaneously. During split read transfer
operation, the RAM port input clocks do not have to be synchronized with the serial clock SC,
thus eliminating timing restrictions as in the case of real time read transfers. A split read transfer
can be performed after a delay of tSTS from the change of state of the QSF output is satisfied.
Conventional (non-split) read transfer operation must precede split read transfer cycles.
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MSM54V16283
Masked Split Write Transfer: RAS falling edge --- CAS = DSF = "H", TRG = "L"
WEL or WEU = "L"
Split write transfer consists of loading 256 words by 16 bits of data from the non-active split SAM
register into a selected row of the corresponding split RAM. Serial data can be shifted into the
other half of the split SAM register simultaneously. During split write transfer operation, the
RAM port input clocks do not have to be synchronized with the serial clock SC, thus allowing
for real time transfer. This operation is the same as a mask write operation in RAM, so new and
persistent modes can be supported.
A split write transfer can be performed after a delay of tSTS from the change of state of the QSF
output is satisfied.
A masked write transfer operation must precede split write transfer. The purpose is to switch the
SAM port from output mode to input mode, and to set the initial TAP location prior to split write
transfer operations.
Programmable SAM Stops in Split Transfer Cycle
The MSM54V16283 has a boundary split register operation using programmable stops. If a CBRS
cycle has been performed, the split transfer cycle performs the boundary operation.
Figure 2 shows an example of a boundary split register (4 stop points). The stop points define a
SAM location at which the access will change from one half of the SAM to the other half (at the
TAP address).
Lower SAM
TAP1
0
Upper SAM
TAP3
TAP2
255
256
511
S.T. (TAP3)
S.T. (TAP2)
Figure 2. Example of Boundary Split Register
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¡ Semiconductor
MSM54V16283
SAM Stop Set Cycle (CBRS): RAS falling edge --- CAS = "L", WEL or WEU = "L", DSF = "H"
SAM stop location data (boundaries) are latched from address inputs at the falling edge of RAS.
To determine the boundary A4 - A7 are used, and A0 - A3, and A8 are ignored.
Once the CBRS is executed, the programmable SAM stop operation continues until CBRR.
SAM Stop Boundary Table
Number of Stop Points
Address
Size of Partition
A4
A5
A6
A7
1
1
1
1
1
256
2
1
1
1
0
128
4
1
1
0
X
64
8
1
0
X
X
32
16
0
X
X
X
16
Register Reset Cycle (CBRR): RAS falling edge --- CAS = "L", WEL = WEU = "H", DSF = "L"
A CBRR can reset the programmable SAM stop operation, and persistent mask write operation.
The CBRR will take effect immediately; it doesn’t require a split transfer cycle.
POWER UP
Power must be applied to the RAS and TRG input signals to pull them "high" before, or at the
same time as, the VCC supply is turned on. After power-up, a pause of 200 ms minimum is
required with RAS and TRG held "high". After the pause, a minimum of 8 RAS and 8 SC dummy
cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer
operations can begin. During the initialization period, the TRG signal must be held "high". If the
internal refresh counter is used, a minimum 8 CAS before RAS cycles are required instead of 8
RAS cycles.
(NOTE) INITIAL STATE AFTER POWER UP
The initial state can not be guaranteed for various power up conditions and input signal levels.
Therefore, it is recommended that the initial state be set (ex. Perform a CBRR cycle to select Non
Persistent Write-per-bit mode) after the initialization of the device is performed and before valid
operations begin.
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¡ Semiconductor
MSM54V16283
PACKAGE DIMENSIONS
(Unit : mm)
SSOP64-P-525-0.80-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.34 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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¡ Semiconductor
MSM54V16283
(Unit : mm)
TSOPII70/64-P-400-0.65-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.59 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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