HM538123B Series
1 M VRAM (128-kword × 8-bit)
ADE-203-231D (Z)
Rev. 4.0
Nov. 1997
Description
The HM538123B is a 1-Mbit multiport video RAM equipped with a 128-kword × 8-bit dynamic RAM and a
256-word × 8-bit SAM (serial access memory). Its RAM and SAM operate independently and
asynchronously. It can transfer data between RAM and SAM. In addition, it has two modes to realize fast
writing in RAM. Block write and flash write modes clear the data of 4-word × 8-bit and the data of one row
(256-word × 8-bit) respectively in one cycle of RAM. And the HM538123B makes split transfer cycle
possible by dividing SAM into two split buffers equipped with 128-word × 8-bit each. This cycle can
transfer data to SAM which is not active, and enables a continuous serial access.
Features
• Multiport organization
Asynchronous and simultaneous operation of RAM and SAM capability
RAM: 128-kword × 8-bit and
SAM: 256-word × 8-bit
• Access time
RAM: 60 ns/70 ns/80 ns/100 ns max
SAM: 20 ns/22 ns/25 ns/25 ns max
• Cycle time
RAM: 125 ns/135 ns/150 ns/180 ns min
SAM: 25 ns/25 ns/30 ns/30 ns min
• Low power
Active RAM: 413 mW max
SAM: 275 mW max
Standby 38.5 mW max
• High-speed page mode capability
• Mask write mode capability
• Bidirectional data transfer cycle between RAM and SAM capability
• Split transfer cycle capability
• Block write mode capability
• Flash write mode capability
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HM538123B Series
• 3 variations of refresh (8 ms/512 cycles)
5$6-only refresh
&$6-before-5$6 refresh
Hidden refresh
• TTL compatible
Ordering Information
Type No.
Access Time
Package
HM538123BJ-6
HM538123BJ-7
HM538123BJ-8
HM538123BJ-10
60 ns
70 ns
80 ns
100 ns
400-mil 40-pin plastic SOJ (CP-40D)
2
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HM538123B Series
Pin Arrangement
HM538123BJ Series
SC
SI/O0
SI/O1
SI/O2
SI/O3
DT/OE
I/O0
I/O1
I/O2
I/O3
VCC
WE
NC
RAS
NC
A8
A6
A5
A4
VCC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V SS
SI/O7
SI/O6
SI/O5
SI/O4
SE
I/O7
I/O6
I/O5
I/O4
VSS
DSF
NC
CAS
QSF
A0
A1
A2
A3
A7
(Top View)
Pin Description
Pin Name
Function
A0 – A8
Address inputs
I/O0 – I/O7
RAM port data inputs/outputs
SI/O0 – SI/O7
SAM port data inputs/outputs
5$6
Row address strobe
&$6
Column address strobe
:(
Write enable
'7 2(
/
Data transfer/Output enable
SC
Serial clock
6(
SAM port enable
DSF
Special function input flag
QSF
Special function output flag
VCC
Power supply
VSS
Ground
NC
No connection
3
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HM538123B Series
Block Diagram
A0 – A8
A0 – A8
Row Address
Buffer
Refresh
Counter
0
Data
Register
Transfer
Gate
Serial Output
Buffer
Color
Resister
Mask
Register
Input Data
Control
Address Mask
Register
511
Transfer
Gate
Data
Register
Sense Amplifier & I/O Bus
Column Decoder
Block Write Flash Write
Control
Control
0
255 Memory Array
SAM Column Decoder
Serial Address
Counter
Row Decoder
SAM I/O Bus
A0 – A7
Column Address
Buffer
Serial Input
Buffer
SI/O0 – SI/O7
Input
Buffer
Output
Buffer
Timing Generator
RAS
CAS
DT/OE
WE
DSF
SC
SE
I/O0 – I/O7
4
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QSF
HM538123B Series
Pin Functions
5$6 (input pin):
5$6 is a basic RAM signal. It is active in low level and standby in high level. Row
address and signals as shown in table 1 are input at the falling edge of 5$6. The input level of these signals
determine the operation cycle of the HM538123B.
Table 1
Operation Cycles of the HM538123B
Input Level At The Falling Edge Of 5$6
DSF At The Falling Edge Of
&$6
'7/2( :(
6(
DSF
&$6
Operation Mode
L
X
X
X
X
—
CBR refresh
H
L
L
L
L
X
Write transfer
H
L
L
H
L
X
Pseudo transfer
H
L
L
X
H
X
Split write transfer
H
L
H
X
L
X
Read transfer
H
L
H
X
H
X
Split read transfer
H
H
L
X
L
L
Read/mask write
H
H
L
X
L
H
Mask block write
H
H
L
X
H
X
Flash write
H
H
H
X
L
L
Read/write
H
H
H
X
L
H
Block write
H
H
H
X
H
X
Color register read/write
Note: X; Don’t care
&$6 (input pin):
Column address and DSF signal are fetched into chip at the falling edge of &$6, which
determines the operation mode of HM538123B. &$6 controls output impedance of I/O in RAM.
A0 – A8 (input pins): Row address (AX0 – AX8) is determined by A0 – A8 level at the falling edge of
5$6. Column address (AY0 – AY7) is determined by A0 – A7 level at the falling edge of &$6. In transfer
cycles, row address is the address on the word line which transfers data with SAM data register, and column
address is the SAM start address after transfer.
:( (input pin):
pin has two functions at the falling edge of 5$6 and after. When :( is low at the
falling edge of 5$6, the HM538123B turns to mask write mode. According to the I/O level at the time,
write on each I/O can be masked. (:( level at the falling edge of 5$6 is don’t care in read cycle.) When
:( is high at the falling edge of 5$6, a normal write cycle is executed. After that, :( switches read/write
cycles as in a standard DRAM. In a transfer cycle, the direction of transfer is determined by :( level at
the falling edge of 5$6. When :( is low, data is transferred from SAM to RAM (data is written into
RAM), and when :( is high, data is transferred from RAM to SAM (data is read from RAM).
:(
5
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HM538123B Series
I/O0 – I/O7 (input/output pins): I/O pins function as mask data at the falling edge of 5$6 (in mask write
mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are
retained. After that, they function as input/output pins as those of a standard DRAM. In block write cycle,
they function as address mask data at the falling edge of &$6.
'7/2( (input pin):
'7/2( pin functions as '7 (data transfer) pin at the falling edge of 5$6 and as 2(
(output enable) pin after that. When '7 is low at the falling edge of 5$6, this cycle becomes a transfer
cycle. When '7 is high at the falling edge of 5$6, RAM and SAM operate independently.
SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin
synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of
SC is fetched into the SAM data register.
6( (input pin):
6( pin activates SAM. When 6( is high, SI/O is in the high impedance state in serial read
cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. 6( can be used as a
mask for serial write because internal pointer is incremented at the rising edge of SC.
SI/O0 – SI/O7 (input/output pins): SI/Os are input/output pins in SAM. Direction of input/output is
determined by the previous transfer cycle. When it was a read transfer cycle, SI/O outputs data. When it
was a pseudo transfer cycle or write transfer cycle, SI/O inputs data.
DSF (input pin): DSF is a special function data input flag pin. It is set to high at the falling edge of 5$6
when new functions such as color register read/write, split transfer, and flash write, are used. DSF is set to
high at the falling edge of &$6 when block write is executed.
QSF (output pin): QSF outputs data of address A7 in SAM. QSF is switched from low to high by
accessing address 127 in SAM and from high to low by accessing 255 address in SAM.
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HM538123B Series
Operation of HM538123B
RAM Read Cycle ('7/2( high, &$6 high and DSF low at the falling edge of 5$6, DSF low at the falling
edge of &$6)
Row address is entered at the 5$6 falling edge and column address at the &$6 falling edge to the device as
in standard DRAM. Then, when :( is high and '7/2( is low while &$6 is low, the selected address data
outputs through I/O pin. At the falling edge of 5$6, '7/2( and &$6 become high to distinguish RAM
read cycle from transfer cycle and CBR refresh cycle. Address access time (tAA) and 5$6 to column address
delay time (tRAD) specifications are added to enable high-speed page mode.
RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write) ('7/2( high, &$6 high and DSF
low at the falling edge of 5$6, DSF low at the falling edge of &$6)
• Normal Mode Write Cycle (:( high at the falling edge of 5$6)
When &$6 and :( are set low after driving 5$6 low, a write cycle is executed and I/O data is written
in the selected addresses. When all 8 I/Os are written, :( should be high at the falling edge of 5$6 to
distinguish normal mode from mask write mode.
If :( is set low before the &$6 falling edge, this cycle becomes an early write cycle and I/O becomes
in high impedance. Data is entered at the &$6 falling edge.
If :( is set low after the &$6 falling edge, this cycle becomes a delayed write cycle. Data is input at
the :( falling. I/O does not become high impedance in this cycle, so data should be entered with 2( in
high.
If :( is set low after tCWD (min) and tAWD (min) after the &$6 falling edge, this cycle becomes a readmodify-write cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid
I/O contention, data should be input after reading data and driving 2( high.
• Mask Write Mode (:( low at the falling edge of 5$6)
If :( is set low at the falling edge of 5$6, the cycle becomes a mask write mode which writes only to
selected I/O. Whether or not an I/O is written depends on I/O level (mask data) at the falling edge of
5$6. Then the data is written in high I/O pins and masked in low ones and internal data is retained.
This mask data is effective during the 5$6 cycle. So, in high-speed page mode, the mask data is
retained during the page access.
7
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HM538123B Series
High-Speed Page Mode Cycle ('7/2( high, &$6 high and DSF low at the falling edge of 5$6)
High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling &$6
while 5$6 is low. Its cycle time is one third of the random read/write cycle. In this cycle, read, write, and
block write cycles can be mixed. Note that address access time (tAA), 5$6 to column address delay time
(tRAD), and access time from &$6 precharge (tACP) are added. In one 5$6 cycle, 256-word memory cells of
the same row address can be accessed. It is necessary to specify access frequency within t RASP max (100 µs).
Color Register Set/Read Cycle (&$6 high,
)
/
'7 2(
high,
:(
high and DSF high at the falling edge of
5$6
In color register set cycle, color data is set to the internal color register used in flash write cycle or block
write cycle. 8 bits of internal color register are provided at each I/O. This register is composed of static
circuits, so once it is set, it retains the data until reset. Color register set cycle is just as same as the usual
write cycle except that DSF is set high at the falling edge of 5$6, and read, early write and delayed write
cycle can be executed. In this cycle, HM538123B refreshs the row address fetched at the falling edge of
5$6.
Flash Write Cycle (&$6 high, '7/2( high, :( low and DSF high at the falling edge of 5$6)
In a flash write cycle, a row of data (256-word × 8-bit) is cleared to 0 or 1 at each I/O according to the data
of color register mentioned before. It is also necessary to mask I/O in this cycle. When &$6and '7/2( is
set high, :( is low, and DSF is high at the falling edge of 5$6, this cycle starts. Then, the row address to
clear is given to row address and mask data is given to I/O. Mask data is as same as that of a RAM write
cycle. High I/O is cleared, low I/O is not cleared and the internal data is retained. Cycle time is the same
as those of RAM read/write cycles, so all bits can be cleared in 1/256 of the usual cycle time. (See figure
1.)
8
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HM538123B Series
Color Register Set Cycle
Flash Write Cycle
Flash Write Cycle
RAS
CAS
Address
Row
Xi
Xj
WE
DT/OE
DSF
I/O
*1
Color Data
*1
Execute flash write into each
I/O on row address Xi using
color resister.
Set color register
Execute flash write into
each I/O on row address
Xj using color resister.
Figure 1 Use of Flash Write
Block Write Cycle (&$6 high,
falling edge of &$6)
/
'7 2(
high and DSF low at the falling edge of
5$6
, DSF high at the
In a block write cycle, 4 columns of data (4-word × 8-bit) is cleared to 0 or 1 at each I/O according to the
data of color register. Column addresses A0 and A1 are disregarded. The data on I/Os and addresses can
be masked. I/O level at the falling edge of &$6 determines the address to be cleared. (See figure 2.)
• Normal Mode Block Write Cycle (:( high at the falling edge of 5$6)
The data on 8 I/Os are all cleared when :( is high at the falling edge of 5$6.
• Mask Block Write Mode (:( low at the falling edge of 5$6)
When :( is low at the falling edge of 5$6, HM538123B starts mask block write mode to clear the data
on an optional I/O. The mask data is the same as that of a RAM write cycle. High I/O is cleared, low
I/O is not cleared and the internal data is retained. The mask data is available in the 5$6 cycle. In
page mode block write cycle, the mask data is retained during the page access.
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HM538123B Series
Color Register Set Cycle
Block Write Cycle
Block Write Cycle
RAS
CAS
Address
Row
Row
Column A2–A7
*1
WE
Row
Column A2–A7
*1
DT/OE
DSF
Color Data
I/O
*1
Address Mask
*1
Address Mask
*1
WE
Low
High
I/O
I/O Mask Data
Don't care
Mode
Mask
Non mask
I/O Mask Data
Low: Mask
High: Non Mask
Address Mask Data
I/O0
I/O1
I/O2
I/O3
Column0 (A0 = 0, A1 = 0) Mask Data
Column1 (A0 = 1, A1 = 0) Mask Data
Column2 (A0 = 0, A1 = 1) Mask Data
Column3 (A0 = 1, A1 = 1) Mask Data
Low: Mask
High: Non Mask
Figure 2 Use of Block Write
Transfer Operation
The HM538123B provides the read transfer cycle, split read transfer cycle, pseudo transfer cycle, write
transfer cycle and split write transfer cycle as data transfer cycles. These transfer cycles are set by driving
&$6 high and '7/2( low at the falling edge of 5$6. They have following functions:
(1) Transfer data between row address and SAM data register (except for pseudo transfer cycle)
Read transfer cycle and split read transfer cycle: RAM to SAM
Write transfer cycle and split write transfer cycle: SAM to RAM
(2) Determine SI/O state (except for split read transfer cycle and split write transfer cycle)
Read transfer cycle: SI/O output
Pseudo transfer cycle and write transfer cycle: SI/O input
(3) Determine first SAM address to access after transferring at column address (SAM start address).
SAM start address must be determined by read transfer cycle or pseudo transfer cycle (split transfer cycle
isn’t available) before SAM access, after power on, and determined for each transfer cycle.
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HM538123B Series
Read Transfer Cycle (&$6 high, '7/2( low, :( high and DSF low at the falling edge of 5$6)
This cycle becomes read transfer cycle by driving '7/2( low, :( high and DSF low at the falling edge of
. The row address data (256 × 8-bit) determined by this cycle is transferred to SAM data register
synchronously at the rising edge of '7/2(. After the rising edge of '7/2(, the new address data outputs
from SAM start address determined by column address. In read transfer cycle, '7/2( must be risen to
transfer data from RAM to SAM.
5$6
This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min)
specified between the last SAM access before transfer and '7/2( rising edge and tSDH (min) specified
between the first SAM access and '7/2( rising edge must be satisfied. (See figure 3.)
When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set
high impedance before tSZS (min) of the first SAM access to avoid data contention.
RAS
CAS
Address
DT/OE
Xi
Yj
L
DSF
t SDD
t SDH
SC
Yj
SI/O
SAM Data before Transfer
Figure 3
Pseudo Transfer Cycle (&$6 high,
)
/
'7 2(
Yj + 1
SAM Data after Transfer
Real Time Read Transfer
low,
:(
low,
6(
high and DSF low at the falling edge of
5$6
Pseudo transfer cycle switches SI/O to input state and set SAM start address without data transfer to RAM.
This cycle starts when &$6 is high, '7/2( low, :( low, 6( high and DSF low at the falling edge of 5$6.
Data should be input to SI/O later than tSID (min) after 5$6 becomes low to avoid data contention. SAM
access becomes enabled after tSRD (min) after 5$6 becomes high. In this cycle, SAM access is inhibited
during 5$6 low, therefore, SC must not be risen.
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HM538123B Series
Write Transfer Cycle (&$6 high, '7/2( low, :( low, 6( low and DSF low at the falling edge of 5$6)
Write transfer cycle can transfer a row of data input by serial write cycle to RAM. The row address of data
transferred into RAM is determined by the address at the falling edge of 5$6. The column address is
specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access
becomes enabled after tSRD (min) after 5$6 becomes high. SAM access is inhibited during 5$6 low. In
this period, SC must not be risen. Data transferred to SAM by read transfer cycle or split read transfer cycle
can be written to other addresses of RAM by write transfer cycle. However, the address to write data must
be the same as that of the read transfer cycle or the split read transfer cycle (row address AX8). Figure 4
shows the example of row bit data transfer. In case AX8 is 0, data cannot be transferred RAM address
within the range of 100000000 to 111111111. Same as the case of AX8 = 1.
Split Read Transfer Cycle (&$6 high, '7/2( low, :( high and DSF high at the falling edge of 5$6)
To execute a continuous serial read by real time read transfer, HM538123B must satisfy SC and '7/2(
timings and requires an external circuit to detect SAM last address. Split read transfer cycle makes it
possible to execute a continuous serial read without the above timing limitation. Figure 5 shows the block
diagram for a split transfer. SAM data register (DR) consists of 2 split buffers, whose organizations are
128-word × 8-bit each. Let us suppose that data is read from upper data register DR1 (The row address
AX8 is 0 and SAM address A7 is 1.). When split read transfer is executed setting row address AX8 0 and
SAM start addresses A0 to A6, 128-word × 8-bit data are transferred from RAM to the lower data register
DR0 (SAM address A7 is 0) automatically. After data are read from data register DR1, data start to be read
from SAM start addresses of data register DR0. If the next split read transfer isn’t executed while data are
read from data register DR0, data start to be read from SAM start address 0 of DR1 after data are read from
data register DR0. If split read transfer is executed setting row address AX8 1 and SAM start addresses A0
to A6 while data are read from data register DR1, 128-word × 8-bit data are transferred to data register
DR2. After data are read from data register DR1, data start to be read from SAM start addresses of data
register DR2. If the next split read transfer isn’t executed while data is read from data register DR2, data
start to be read from SAM start address 0 of data register DR3 after data are read from data register DR2.
In this time, SAM data is the one transferred to data register DR3 finally while row address AX8 is 1. In
split read data transfer, the SAM start address A7 is automatically set in the data register which isn’t used.
The data on SAM address A7, which will be accessed next, outputs to QSF, QSF is switched from low to
high by accessing SAM last address 127 and from high to low by accessing address 255.
Split read transfer cycle is set when &$6 is high, '7/2( is low, :( is high and DSF is high at the falling
edge of 5$6. The cycle can be executed asyncronously with SC. However, HM538123B must be satisfied
tSTS (min) timing specified between SC rising and 5$6 falling. SAM start address must be accessed,
satisfying tRST (min), tCST (min) and tAST (min) timings specified between 5$6 or &$6 falling and column
address. (See figure 6.)
In split read transfer, SI/O isn’t switched to output state. Therefore, read transfer must be executed to
switch SI/O to output state when the previous transfer cycle is pseudo transfer or write transfer cycle.
12
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HM538123B Series
(Row address)
A8 ........ A0
000000000
SAM
SAM
(Row address)
A8 ........A0
000000000
........
Possible
RAM
RAM
011111111
100000000
011111111
100000000
Impossible
RAM
RAM
111111111
111111111
SAM
SAM
(Read transfer cycle)
(Write transfer cycle)
DR3
Memory
Array
AX8 = 1
DR2
SAM I/O Bus
SAM Column Decoder
DR0
AX8 = 0
SAM I/O Bus
Memory
Array
DR1
Figure 4 Example of Row Bit Data Transfer
SAM I/O Buffer
SI/O
Figure 5 Block Diagram for Split Transfer
Split Write Transfer Cycle (&$6 high, '7/2( low, :( low and DSF high at the falling edge of 5$6)
A continuous serial write cannot be executed because accessing SAM is inhibited during 5$6 low in write
transfer. Split write transfer cycle makes it possible. In this cycle, tSTS (min), tRST (min), tCST (min) and tAST
(min) timings must be satisfied like split read transfer cycle. And it is impossible to switch SI/O to input
state in this cycle. If SI/O is in output state, pseudo transfer cycle should be executed to switch SI/O into
input state. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to
other addresses of RAM by split write transfer cycle. However, pseudo transfer cycle must be executed
before split write transfer cycle. And the MSB of row address (AX8) to write data must be the same as that
of the read transfer cycle or the split read transfer cycle.
13
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HM538123B Series
RAS
tSTS (min)
tRST (min)
CAS
t CST (min)
Address
Xi
Yj
t AST (min)
DT/OE
DSF
SC
255
(127)
n
(n + 127)
127
(255)
127 + Yj
(Yj)
Figure 6 Limitation in Split Transfer
SAM Port Operation
Serial Read Cycle
SAM port is in read mode when the previous data transfer cycle is read transfer cycle. Access is
synchronized with SC rising, and SAM data is output from SI/O. When 6( is set high, SI/O becomes high
impedance, and the internal pointer is incremented by the SC rising. After indicating the last address
(address 255), the internal pointer indicates address 0 at the next access.
Serial Write Cycle
If previous data transfer cycle is pseudo transfer cycle or write transfer cycle, SAM port goes into write
mode. In this cycle, SI/O data is fetched into data register at the SC rising edge like in the serial read cycle.
If 6( is high, SI/O data isn’t fetched into data register. Internal pointer is incremented by the SC rising, so
6( high can be used as mask data for SAM. After indicating the last address (address 255), the internal
pointer indicates address 0 at the next access.
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HM538123B Series
Refresh
RAM Refresh
RAM, which is composed of dynamic circuits, requires refresh to retain data. Refresh is executed by
accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) 5$6-only refresh cycle, (2)
&$6-before-5$6 (CBR) refresh cycle, and (3) Hidden refresh cycle.
Besides them, the cycles which
activate 5$6 such as read/write cycles or transfer cycles can refresh the row address. Therefore, no refresh
cycle is required when all row addresses are accessed within 8 ms.
(1) 5$6-Only Refresh Cycle: 5$6-only refresh cycle is executed by activating only 5$6 cycle with &$6
fixed to high after inputting the row address (= refresh address) from external circuits. To distinguish
this cycle from data transfer cycle, '7/2( must be high at the falling edge of 5$6.
(2) CBR Refresh Cycle: CBR refresh cycle is set by activating &$6 before 5$6. In this cycled, refresh
address needs not to be input through external circuits because it is input through an internal refresh
counter. In this cycle, output is in high impedance and power dissipation is lowered because &$6
circuits don’t operate.
(3) Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating
5$6 when '7/2( and &$6 keep low in normal RAM read cycles.
SAM Refresh
SAM parts (data register, shift register and selector), organized as fully static circuitry, require no refresh.
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
VT
–1.0 to +7.0
V
VCC
–0.5 to +7.0
V
Short circuit output current
Iout
50
mA
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Terminal voltage
*1
Power supply voltage
Note:
*1
1. Relative to VSS.
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HM538123B Series
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
*1
Supply voltage
Input high voltage
*1
*1
Input low voltage
Symbol
Min
Typ
Max
Unit
VCC
4.5
5.0
5.5
V
VIH
2.4
—
6.5
V
—
0.8
V
*2
VIL
–0.5
Notes: 1. All voltages referred to VSS
2. –3.0 V for pulse width ≤ 10 ns
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM538123B
-6
-7
-8
-10
Test Conditions
Parameter
Symbol
Min Max Min Max Min Max Min Max Unit RAM Port
SAM Port
Operating
current
ICC1
—
75
SC = VIL,
6( = VIH
ICC7
—
125 —
ICC2
—
7
Standby
current
-only
refresh
current
5$6
Page mode
current
—
—
70
—
—
55
mA
120 —
100 —
95
mA
7
7
7
mA
—
60
—
,
cycling
tRC = Min
5$6 &$6
6( = VIL,
SC cycling
tSCC = Min
,
5$6
&$6
ICC8
—
50
—
50
—
40
—
40
mA
ICC3
—
75
—
70
—
60
—
55
mA
= VIH
6( = VIL,
SC cycling
tSCC = Min
cycling
= VIH
tRC = Min
5$6
&$6
ICC9
—
125 —
120 —
100 —
95
mA
ICC4
—
80
80
70
65
mA
—
—
—
—
16
This Material Copyrighted by Its Respective Manufacturer
130 —
130 —
110 —
105 mA
SC = VIL,
6( = VIH
6( = VIL,
SC cycling
tSCC = Min
cycling
= VIL
tPC = Min
&$6
5$6
ICC10
SC = VIL,
6( = VIH
SC = VIL,
6( = VIH
6( = VIL,
SC cycling
tSCC = Min
HM538123B Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont)
HM538123B
-6
-7
-8
-10
Test Conditions
Parameter
Symbol
Min Max Min Max Min Max Min Max Unit RAM Port
SAM Port
-beforerefresh
current
ICC5
—
50
—
45
—
40
—
35
mA
SC = VIL,
6( = VIH
ICC11
—
100 —
95
—
80
—
75
mA
Data transfer ICC6
current
—
80
75
—
65
—
60
mA
ICC12
—
130 —
&$6
cycling
tRC = Min
5$6
5$6
—
125 —
105 —
6( = VIL,
SC cycling
tSCC = Min
,
cycling
tRC = Min
5$6 &$6
100 mA
SC = VIL,
6( = VIH
6( = VIL,
SC cycling
tSCC = Min
Input leakage ILI
current
–10 10
–10 10
–10 10
–10 10
µA
Output
leakage
current
ILO
–10 10
–10 10
–10 10
–10 10
µA
Output high
voltage
VOH
2.4
—
2.4
—
2.4
—
2.4
—
V
IOH = –2 mA
Output low
voltage
VOL
—
0.4
—
0.4
—
0.4
—
0.4
V
IOL = 4.2 mA
Notes: 1. ICC depends on output loading condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once while 5$6 is low and &$6 is high.
Capacitance (Ta = 25°C, VCC = 5 V, f = 1 MHz, Bias: Clock, I/O = VCC, address = VSS)
Parameter
Symbol
Min
Typ
Max
Unit
Address
CI1
—
—
5
pF
Clock
CI2
—
—
5
pF
I/O, SI/O, QSF
CI/O
—
—
7
pF
17
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1,*16
Test Conditions
•
•
•
•
•
Input rise and fall time : 5 ns
Output load : See figures
Input pulse levels: VSS to 3.0 V
Input timing reference levels : 0.8 V, 2.4 V
Output timing reference levels : 0.8 V, 2.0 V
I OH = – 2 mA
+5V
I OH = – 2 mA
I OL = 4.2 mA
I OL = 4.2 mA
I/O
*1
100 pF
Output Load (A)
Note: 1.
Including scope & jig
18
This Material Copyrighted by Its Respective Manufacturer
+5V
SI / O
*1
50 pF
Output Load (B)
HM538123B Series
Common Parameter
HM538123B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Uni Note
t
s
Random read or write cycle
time
tRC
125 —
135 —
150 —
180 —
ns
55
60
70
ns
5$6
precharge time
tRP
55
—
—
—
—
5$6
pulse width
tRAS
60
10000 70
10000 80
10000 100 10000 ns
&$6
pulse width
tCAS
20
—
20
—
20
—
25
—
ns
Row address setup time
tASR
0
—
0
—
0
—
0
—
ns
Row address hold time
tRAH
10
—
10
—
10
—
10
—
ns
Column address setup time
tASC
0
—
0
—
0
—
0
—
ns
Column address hold time
tCAH
15
—
15
—
15
—
15
—
ns
5$6
to &$6 delay time
tRCD
20
40
20
50
20
60
20
75
ns
5$6
hold time referenced to
tRSH
20
—
20
—
20
—
25
—
ns
hold time referenced to
tCSH
60
—
70
—
80
—
100 —
ns
to 5$6 precharge time
tCRP
10
—
10
—
10
—
10
—
ns
Transition time (rise to fall)
tT
3
50
3
50
3
50
3
50
ns
Refresh period
tREF
—
8
—
8
—
8
—
8
ms
2
&$6
&$6
5$6
&$6
3
'7
to 5$6 setup time
tDTS
0
—
0
—
0
—
0
—
ns
'7
to 5$6 hold time
tDTH
10
—
10
—
10
—
10
—
ns
DSF to 5$6 setup time
tFSR
0
—
0
—
0
—
0
—
ns
DSF to 5$6 hold time
tRFH
10
—
10
—
10
—
10
—
ns
DSF to &$6 setup time
tFSC
0
—
0
—
0
—
0
—
ns
DSF to &$6 hold time
tCFH
15
—
15
—
15
—
15
—
ns
Data-in to &$6 delay time
tDZC
0
—
0
—
0
—
0
—
ns
4
Data-in to 2( delay time
tDZO
0
—
0
—
0
—
0
—
ns
4
Output buffer turn-off delay
referred to &$6
tOFF1
—
20
—
20
—
20
—
20
ns
5
Output buffer turn-off delay
referred to 2(
tOFF2
—
20
—
20
—
20
—
20
ns
5
19
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Read Cycle (RAM), Page Mode Read Cycle
HM538123B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Uni Note
t
s
Access time from 5$6
tRAC
—
60
—
70
—
80
—
100
ns
6, 7
Access time from &$6
tCAC
—
20
—
20
—
20
—
25
ns
7, 8
Access time from 2(
tOAC
—
20
—
20
—
20
—
25
ns
7
Address access time
tAA
—
35
—
35
—
40
—
45
ns
7, 9
Read command setup time
tRCS
0
—
0
—
0
—
0
—
ns
Read command hold time
tRCH
0
—
0
—
0
—
0
—
ns
10
Read command hold time
referenced to 5$6
tRRH
10
—
10
—
10
—
10
—
ns
10
to column address delay tRAD
15
25
15
35
15
40
15
55
ns
2
5$6
time
Column address to 5$6lead
time
tRAL
35
—
35
—
40
—
45
—
ns
Column address to &$6lead
time
tCAL
35
—
35
—
40
—
45
—
ns
Page mode cycle time
tPC
45
—
45
—
50
—
55
—
ns
tCP
10
—
10
—
10
—
10
—
ns
Access time from &$6
precharge
tACP
—
40
—
40
—
45
—
50
ns
Page mode 5$6 pulse width
tRASP
60
100000 70
&$6
precharge time
20
This Material Copyrighted by Its Respective Manufacturer
100000 80
100000 100 100000 ns
HM538123B Series
Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle
HM538123B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Uni Note
t
s
Write command setup time
tWCS
0
—
0
—
0
—
0
—
ns
Write command hold time
tWCH
15
—
15
—
15
—
15
—
ns
Write command pulse width
tWP
15
—
15
—
15
—
15
—
ns
Write command to 5$6lead
time
tRWL
20
—
20
—
20
—
20
—
ns
Write command to &$6lead
time
tCWL
20
—
20
—
20
—
20
—
ns
Data-in setup time
tDS
0
—
0
—
0
—
0
—
ns
12
Data-in hold time
tDH
15
—
15
—
15
—
15
—
ns
12
:(
to 5$6 setup time
tWS
0
—
0
—
0
—
0
—
ns
:(
to 5$6 hold time
tWH
10
—
10
—
10
—
10
—
ns
Mask data to 5$6 setup time
tMS
0
—
0
—
0
—
0
—
ns
Mask data to 5$6 hold time
tMH
10
—
10
—
10
—
10
—
ns
tOEH
20
—
20
—
20
—
20
—
ns
tPC
45
—
45
—
50
—
55
—
ns
2(
hold time referred to :(
Page mode cycle time
&$6
precharge time
tCP
10
—
10
—
10
—
10
—
ns
&$6
to data-in delay time
tCDD
20
—
20
—
20
—
20
—
ns
tRASP
60
100000 70
Page mode 5$6 pulse width
100000 80
11
13
100000 100 100000 ns
21
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Read-Modify-Write Cycle
HM538123B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Uni Note
t
s
Read-modify-write cycle time
tRWC
185 —
200 —
230 —
ns
pulse width (read-modify- tRWS
write cycle)
5$6
110 10000 120 10000 130 10000 150 10000 ns
tCWD
45
—
45
—
45
—
50
—
ns
14
Column address to :( delay
time
tAWD
60
—
60
—
65
—
70
—
ns
14
to data-in delay time
tODD
20
—
20
—
20
—
20
—
ns
12
Access time from 5$6
tRAC
—
60
—
70
—
80
—
100
ns
6, 7
Access time from &$6
tCAC
—
20
—
20
—
20
—
25
ns
7, 8
Access time from 2(
tOAC
—
20
—
20
—
20
—
25
ns
7
Address access time
tAA
—
35
—
35
—
40
—
45
ns
7, 9
15
25
15
35
15
40
15
55
ns
&$6
2(
5$6
to :( delay time
175 —
to column address delay tRAD
time
Read command setup time
tRCS
0
—
0
—
0
—
0
—
ns
Write command to 5$6 lead
time
tRWL
20
—
20
—
20
—
20
—
ns
Write command to &$6 lead
time
tCWL
20
—
20
—
20
—
20
—
ns
Write command pulse width
tWP
15
—
15
—
15
—
15
—
ns
Data-in setup time
tDS
0
—
0
—
0
—
0
—
ns
12
Data-in hold time
tDH
15
—
15
—
15
—
15
—
ns
12
tOEH
20
—
20
—
20
—
20
—
ns
2(
hold time referred to :(
Refresh Cycle
HM538123B
-6
-7
-8
-10
Min Max
Min Max
Min Max
Uni Note
t
s
Parameter
Symbol Min Max
&$6
setup time
(&$6-before-5$6 refresh)
tCSR
10
—
10
—
10
—
10
—
ns
hold time
(&$6-before-5$6 refresh)
tCHR
10
—
10
—
10
—
10
—
ns
tRPC
10
—
10
—
10
—
10
—
ns
&$6
5$6
&$6
precharge to
hold time
22
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Flash Write Cycle, Block Write Cycle
HM538123B
-6
Parameter
&$6
2(
to data-in delay time
to data-in delay time
-7
-8
-10
Symbol Min Max
Min Max
Min Max
Min Max
Uni Note
t
s
tCDD
20
—
20
—
20
—
20
—
ns
13
tODD
20
—
20
—
20
—
20
—
ns
13
Read Transfer Cycle
HM538123B
-6
Parameter
-7
-8
-10
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit Notes
hold time referenced to 5$6
tRDH
50
10000
60
10000
65
10000
80
10000
ns
hold time referenced to &$6
tCDH
20
—
20
—
20
—
25
—
ns
hold time referenced to column tADH
address
25
—
25
—
30
—
30
—
ns
'7
'7
'7
'7
precharge time
tDTP
20
—
20
—
20
—
30
—
ns
'7
to 5$6 delay time
tDRD
65
—
65
—
70
—
80
—
ns
SC to 5$6 setup time
tSRS
25
—
25
—
30
—
30
—
ns
1st SC to 5$6 hold time
tSRH
60
—
70
—
80
—
100
—
ns
1st SC to &$6 hold time
tSCH
25
—
25
—
25
—
25
—
ns
1st SC to column address hold time tSAH
40
—
40
—
45
—
50
—
ns
Last SC to '7 delay time
tSDD
5
—
5
—
5
—
5
—
ns
Last SC to '7 delay time
tSDD2
25
—
25
—
25
—
25
—
ns
1st SC to '7 hold time
tSDH
10
—
10
—
15
—
15
—
ns
to QSF delay time
tRQD
—
65
—
70
—
75
—
85
ns
15
to QSF delay time
tCQD
—
35
—
35
—
40
—
40
ns
15
tDQD
—
35
—
35
—
35
—
35
ns
15
QSF hold time referred to 5$6
tRQH
20
—
20
—
20
—
25
—
ns
QSF hold time referred to &$6
tCQH
5
—
5
—
5
—
5
—
ns
QSF hold time referred to '7
tDQH
5
—
5
—
5
—
5
—
ns
Serial data-in to 1st SC delay time
tSZS
0
—
0
—
0
—
0
—
ns
Serial clock cycle time
tSCC
25
—
25
—
30
—
30
—
ns
5$6
&$6
'7
to QSF delay time
17
23
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Read Transfer Cycle (cont)
HM538123B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Uni Note
t
s
SC pulse width
tSC
5
—
5
—
10
—
10
—
ns
SC precharge time
tSCP
10
—
10
—
10
—
10
—
ns
SC access time
tSCA
—
20
—
22
—
25
—
25
ns
Serial data-out hold time
tSOH
5
—
5
—
5
—
5
—
ns
Serial data-in setup time
tSIS
0
—
0
—
0
—
0
—
ns
Serial data-in hold time
tSIH
15
—
15
—
15
—
15
—
ns
to column address delay tRAD
15
25
15
35
15
40
15
55
ns
5$6
time
Column address to 5$6 lead
time
tRAL
35
—
35
—
40
—
45
—
ns
precharge to '7 high
hold time
tDTHH
10
—
10
—
10
—
10
—
ns
5$6
24
This Material Copyrighted by Its Respective Manufacturer
15
HM538123B Series
Pseudo Transfer Cycle, Write Transfer Cycle
HM538123B
-6
Parameter
Symbol Min Max
-7
-8
-10
Min Max
Min Max
Min Max
Uni Note
t
s
6(
setup time referred to 5$6 tES
0
—
0
—
0
—
0
—
ns
6(
hold time referred to 5$6
10
—
10
—
10
—
10
—
ns
25
—
25
—
30
—
30
—
ns
tEH
SC setup time referred to 5$6 tSRS
to SC delay time
tSRD
20
—
20
—
25
—
25
—
ns
Serial output buffer turn-off
time referred to 5$6
tSRZ
10
40
10
40
10
45
10
50
ns
to serial data-in delay
tSID
40
—
40
—
45
—
50
—
ns
5$6
to QSF delay time
tRQD
—
65
—
70
—
75
—
85
ns
15
&$6
to QSF delay time
tCQD
—
35
—
35
—
40
—
40
ns
15
tRQH
20
—
20
—
20
—
25
—
ns
tCQH
5
—
5
—
5
—
5
—
ns
Serial clock cycle time
tSCC
25
—
25
—
30
—
30
—
ns
SC pulse width
tSC
5
—
5
—
10
—
10
—
ns
SC precharge time
tSCP
10
—
10
—
10
—
10
—
ns
SC access time
tSCA
—
20
—
22
—
25
—
25
ns
15
access time
tSEA
—
20
—
22
—
25
—
25
ns
15
tSOH
5
—
5
—
5
—
5
—
ns
Serial write enable setup time tSWS
5
—
5
—
5
—
5
—
ns
Serial data-in setup time
tSIS
0
—
0
—
0
—
0
—
ns
Serial data-in hold time
tSIH
15
—
15
—
15
—
15
—
ns
5$6
5$6
time
QSF hold time referred to
5$6
QSF hold time referred to
&$6
6(
Serial data-out hold time
25
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Split Read Transfer Cycle, Split Write Transfer Cycle
HM538123B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Uni Note
t
s
Split transfer setup time
tSTS
20
—
20
—
20
—
25
—
ns
Split transfer hold time
referenced to 5$6
tRST
60
—
70
—
80
—
100 —
ns
Split transfer hold time
referenced to &$6
tCST
20
—
20
—
20
—
25
—
ns
Split transfer hold time
tAST
referenced to column address
35
—
35
—
40
—
45
—
ns
SC to QSF delay time
tSQD
—
30
—
30
—
30
—
30
ns
QSF hold time referred to SC
tSQH
5
—
5
—
5
—
5
—
ns
Serial clock cycle time
tSCC
25
—
25
—
30
—
30
—
ns
SC pulse width
tSC
5
—
5
—
10
—
10
—
ns
SC precharge time
tSCP
10
—
10
—
10
—
10
—
ns
SC access time
tSCA
—
20
—
22
—
25
—
25
ns
Serial data-out hold time
tSOH
5
—
5
—
5
—
5
—
ns
Serial data-in setup time
tSIS
0
—
0
—
0
—
0
—
ns
Serial data-in hold time
tSIH
15
—
15
—
15
—
15
—
ns
to column address delay tRAD
15
25
15
35
15
40
15
55
ns
35
—
35
—
40
—
45
—
ns
5$6
time
Column address to 5$6 lead
time
26
This Material Copyrighted by Its Respective Manufacturer
tRAL
15
15
HM538123B Series
Serial Read Cycle, Serial Write Cycle
HM538123B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Uni Note
t
s
Serial clock cycle time
tSCC
25
—
25
—
30
—
30
—
ns
SC pulse width
tSC
5
—
5
—
10
—
10
—
ns
SC precharge width
tSCP
10
—
10
—
10
—
10
—
ns
Access time from SC
tSCA
—
20
—
22
—
25
—
25
ns
15
Access time from 6(
tSEA
—
20
—
22
—
25
—
25
ns
15
Serial data-out hold time
tSOH
5
—
5
—
5
—
5
—
ns
Serial output buffer turn-off
time referred to 6(
tSEZ
—
20
—
20
—
20
—
20
ns
Serial data-in setup time
tSIS
0
—
0
—
0
—
0
—
ns
Serial data-in hold time
tSIH
15
—
15
—
15
—
15
—
ns
Serial write enable setup time tSWS
5
—
5
—
5
—
5
—
ns
Serial write enable hold time
15
—
15
—
15
—
15
—
ns
Serial write disable setup time tSWIS
5
—
5
—
5
—
5
—
ns
Serial write disable hold time
15
—
15
—
15
—
15
—
ns
tSWH
tSWIH
5
Notes: 1. AC measurements assume tT = 5 ns.
2. When tRCD > tRCD (max) or tRAD > tRAD (max), access time is specified by tCAC or tAA.
3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals.
Transition time tT is measured between VIH and VIL.
4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write
cycle and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied.
5. tOFF1 (max), tOFF2 (max) and tSEZ (max) are defined as the time at which the output achieves the
open circuit condition (VOH – 100 mV, VOL + 100 mV).
6. Assume that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
8. When tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max), access time is specified by tCAC.
9. When tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max), access time is specified by tAA.
10. If either tRCH of tRRH is satisfied, operation is guaranteed.
11. When tWCS ≥ tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit
(high impedance) condition.
12. These parameters are specified by the later falling edge of &$6 or :(.
13. Either tCDD (min) or tODD (min) must be satisfied because output buffer must be turned off by &$6 or
2( prior to applying data to the device when output buffer is on.
14. When tAWD ≥ tAWD (min) and tCWD ≥ tCWD (min) in read-modify-write cycle, the data of the selected
address outputs to an I/O pin and input data is written into the selected address. tODD (min) must
be satisfied because output buffer must be turned off by 2( prior to applying data to the device.
15. Measured with a load circuit equivalent to 2 TTL loads and 50 pF.
27
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
16. After power-up, pause for 100 µs or more and execute at least 8 initialization cycle (normal
memory cycle or refresh cycle), then start operation.
17. After read transfer cycle, if split read transfer cycle is executed without SC access and SC
address is 126 or 254, tSDD2 (min) must be satisfied 25 ns. Except for those cases, tSDD (min) is
effective and satisfied 5 ns.
18. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
Timing Waveforms*18
Read Cycle
t RC
t RAS
t RP
RAS
t CRP
t CSH
t RSH
t CAS
t RCD
CAS
t RAD
t ASR
Address
t RAL
t RAH
t ASC
Row
Column
t RCS
WE
t CAL
t CAH
t RRH
t RCH
t CAC
t AA
I/O
(Output)
t CDD
t OFF1
t RAC
Valid Dout
t OAC
t DZC
I/O
(Input)
t DZO
t DTS
t DTH
t FSR
t RFH
DT/OE
DSF
28
This Material Copyrighted by Its Respective Manufacturer
t FSC
t CFH
t OFF2
HM538123B Series
Early Write Cycle
t RC
t RAS
t RP
RAS
t CRP
t CSH
t RCD
CAS
t ASR
Address
t RAH
t CAH
t ASC
Row
t WS
t RSH
t CAS
Column
t WH
t WCS
t WCH
*1
WE
I/O
(Output)
I/O
(Input)
High-Z
t MH
t MS
t DS
Mask Data
t DTS
t DTH
t DH
Valid Din
DT/OE
t FSR
t RFH
t FSC
t CFH
DSF
Note:
1.
This cycle becomes a normal mode write cycle when :( is high and a mask write cycle
when :( is low.
Delayed Write Cycle
t RC
t RAS
t RP
RAS
CAS
t CAS
t ASR
Address
t RAH
Row
t WS
t ASC
t CAH
Columun
t RWL
t WH
I/O
(Input)
DT/OE
t MS
t MH
t RFH
t DS
t DZC
Mask Data
t DTH
t DTS
t FSR
t CWL
t WP
*1
WE
I/O
(Output)
t CRP
t CSH
t RSH
t RCD
t OFF2
t ODD
t FSC
t DH
Valid Din
t OEH
t CFH
DSF
Note:
1.
This cycle becomes a normal mode write cycle when :( is high and a mask write cycle
when :( is low.
29
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Read-Modify-Write Cycle
t RWC
t RP
t RWS
RAS
t CRP
t RCD
CAS
t RAD
t ASR
Address
t RAH
t ASC
Row
t WS
WE
t CAH
Column
t WH
t AWD
t CWD
t RCS
t RWL
t CWL
t WP
t CAC
t AA
*1
t RAC
I/O
(Output)
Valid Dout
t MS
I/O
(Input)
t MH
Mask Data
t DTS
t OAC
t DZC
t DH
Valid Din
t OFF2
t ODD
t DZO
t DTH
t DS
t OEH
DT/OE
t RFH
t FSR
t FSC
t CFH
DSF
Note:
1.
This cycle becomes a normal mode write cycle when :( is high and a mask write cycle
when :( is low.
Page Mode Read Cycle
t RC
t RASP
RAS
t CSH
t RCD
t CAS
CAS
t RAD
t ASR
Address
t RAH
Row
t ASC
WE
t PC
t CP
t CAL
t CAH
Column
t RCS
t ASC
I/O
(Input)
t DTS
t DZO
t DTH
t FSR
t RFH
t CDD
t OAC t OFF2
t CAL
t CAH
t ASC
Column
t AA
t ACP
t CAC
t RRH
t RCH
t RCS
t RCH
t OFF1
Valid
Dout
t DZC
t AA
t ACP
t CAC
Valid
Dout
t DZC
t OAC
30
This Material Copyrighted by Its Respective Manufacturer
t FSC
t CFH
t FSC
t CDD
t OFF2
t CFH
t OFF1
Valid Dout
t DZC
t OAC
DT/OE
DSF
t CRP
t RAL
t CAL
t CAH
Column
t RCH
t RSH
t CAS
t CP
t CAS
t RCS
t RAC t OFF1
t AA
t CAC
I/O
(Output)
t RP
t FSC
t CFH
t CDD
HM538123B Series
Page Mode Write Cycle (Early Write)
t RC
t RP
t RASP
RAS
t PC
t CSH
t RCD
CAS
t ASR
Address
t CAS
t RAH t ASC
t RSH
t CAS
t CP
t CAS
t CAH t ASC
Row
Column
t WS t WH t WCS t WCH
WE
t CP
t CAH t ASC
t CRP
t CAH
Column
Column
t WCS t WCH
t WCS t WCH
*1
High-Z
I/O
(Output)
t MS
I/O
(Input)
t DS
t MH
Mask
Data
t DTS
t DH
t DS
Valid Din
t DH
t DH
t DS
Valid Din
Valid Din
t DTH
DT/OE
t FSR
t RFH
t CFH
t FSC
t FSC
t CFH
t FSC
t CFH
DSF
Note:
1.
This cycle becomes a normal mode write cycle when :( is high and a mask write cycle
when :( is low.
Page Mode Write Cycle (Delayed Write)
t RC
t RASP
t RP
RAS
t CSH
t PC
t RCD
CAS
t ASR t RAH t ASC
Address
Row
t WS
t CP
t CAS
t CAH
Column
t ASC
t CAH
Column
t ASC
t CRP
t CAH
Column
t RWL
t CWL
t CWL
t WH
t RSH
t CAS
t CP
t CAS
t WP
t CWL
t WP
t WP
*1
WE
I/O
(Output)
t MS
I/O
(Input)
t MH
Mask
Data
t DS
t DH
Valid
Din
t DS
t DH
t DS
Valid
Din
Valid
Din
t OEH
t DTS
DT/OE
t FSR
t DH
t RFH t FSC
t CFH
t FSC t CFH
t FSC
t CFH
DSF
Note:
1.
This cycle becomes a normal mode write cycle when :( is high and a mask write cycle
when :( is low.
31
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
5$6-Only Refresh Cycle
t RC
t RP
t RAS
RAS
t RPC
t CRP
CAS
t ASR
t RAH
Row
Address
t OFF1
I/O
(Output)
t CDD
I/O
(Input)
t OFF2
t ODD
t DTS
t DTH
t FSR
t RFH
DT/OE
DSF
&$6-Before-5$6 Refresh Cycle
t RC
t RP
RAS
t RPC
t CP
t RPC
t CSR
t CHR
Inhibit Falling Transition
CAS
Address
WE
I/O
(Output)
DT/OE
DSF
32
This Material Copyrighted by Its Respective Manufacturer
t RP
t RAS
t OFF1
High-Z
t CSR
HM538123B Series
Hidden Refresh Cycle
t RC
t RAS
t RC
t RAS
t RP
t RP
RAS
t RCD
CAS
t CRP
t CHR
t RAD t RAL
t RAH t
ASC t CAH
t ASR
Address
t RSH
Row
Column
t RCS
t RRH
t CAC
WE
t AA
t RAC
I/O
(Output)
Valid Dout
t DZC
I/O
(Input)
t OAC
t OFF2
t DZO
t DTH
t DTS
DT/OE
t OFF1
t RFH
t FSR
t FSC
t CFH
DSF
Color Register Set Cycle (Early Write)
t RC
t RP
t RAS
RAS
t CSH
t RCD
CAS
t ASR
Address
t CRP
t RSH
t CAS
t RAH
Row
t WS
t WH
t WCS
t WCH
t DS
t DH
WE
High-Z
I/O
(Output)
I/O
(Input)
Color Data
t DTS
t DTH
t FSR
t RFH
DT/OE
DSF
33
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Color Register Set Cycle (Delayed Write)
t RC
t RP
t RAS
RAS
t CSH
t CRP
t RSH
t RCD
t CAS
CAS
t ASR
Address
t RAH
Row
t RWL
t CWL
t WS
t WP
WE
I/O
(Output)
High-Z
t DS
I/O
(Input)
t DH
Color Data
t DTS
DT/OE
t OEH
t FSR
t RFH
DSF
Color Register Read Cycle
t RC
t RP
t RAS
RAS
t CSH
CAS
t ASR
Address
t CRP
t RSH
t CAS
t RCD
t RAH
Row
t WS
t RCS
t WH
WE
t RRH
t CDD
t OFF1
t CAC
t RAC
I/O
(Output)
Valid Out
t DZC
I/O
(Input)
t DZO
t DTS
DT/OE
t RCH
t FSR
DSF
34
This Material Copyrighted by Its Respective Manufacturer
t DTH
t RFH
t OAC
t OFF2
t ODD
HM538123B Series
Flash Write Cycle
t RC
t RAS
t RP
RAS
t CRP
CAS
t RCD
t ASR
t RAH
Row
Address
t WS
t WH
WE
t OFF1
I/O
(Output)
t OFF2
t CDD
High-Z
t MS
t ODD
I/O
(Input)
t DTS
DT/OE
t MH
Mask Data
t DTH
t FSR
t RFH
DSF
Block Write Cycle
t RC
t RP
t RAS
RAS
t CSH
t CRP
CAS
t RCD
t RAH
t ASR
Address
t WS
Row
t WH
WE
t RSH
t ASC
t CRP
t CAH
Column A2-A8
*1
t OFF1
I/O
(Output)
t OFF2
t CDD
High-Z
t ODD
I/O
(Input)
t DTS
t MS
t MH
I/O Mask Data
t DTH
t DS
t DH
Address
Mask Data
DT/OE
t FSR
t RFH
t FSC
t CFH
DSF
Note:
1.
This cycle becomes a normal mode write cycle when :( is high and a mask write cycle
when :( is low.
35
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Page Mode Block Write Cycle
t RC
t RP
t RASP
RAS
t CSH
t PC
t RCD
t CAS
t CP
t RSH
t CAS
t CP
t CAS
t CRP
CAS
t ASR t RAH
t WS
t CAH
Column
A2-A8
Row
Address
t ASC
t ASC
t CAH
t ASC
Column
A2-A8
t CAH
Column
A2-A8
t WH
*1
WE
I/O
(Output)
High-Z
t MS
I/O
(Input)
t MH
t DTS
t DS
t DH
Address
Mask
I/O
Mask
t DS
t DH
Address
Mask
t DS
t DH
Address
Mask
t DTH
DT/OE
t FSR
t RFH
t FSC
t CFH
t FSC
t CFH
t FSC
t CFH
DSF
Note:
1.
This cycle becomes a normal mode write cycle when :( is high and a mask write cycle
when :( is low.
36
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Read Transfer Cycle (1)
t RC
t RP
t RAS
RAS
t CRP
t CSH
t RCD
t RSH
t CAS
CAS
t RAD
t RAH
t ASR
Address
t RAL
t ASC t CAH
SAM Start
Address
Row
t WS
t WH
WE
t DTHH
High-Z
I/O
(Output)
t CDH
t DTS
t DRD
t ADH
t RDH
t DTP
DT/OE
t FSR
t RFH
DSF
t SCC
SC
t SCC
SI/O
(Output)
Valid Sout
Valid Sout
t SCC
t SCC
t SC
t SDH
t SCA
t SOH
t SCA
t SOH
t SCA
t SOH
t SCA
t SOH
t SDD
t SDD2* 3
Valid Sout
Valid Sout
Previous Row
SI/O
(Input)
t SCP
t SOH
Valid Sout
New Row
t DQD
t DQH
QSF
*1
SAM Address MSB
t RQD
t RQH
QSF
*2
t CQD
t CQH
SAM Address MSB
Notes: 1. This QSF timing is referred when SC is risen once or more between the previous transfer cycle
and &$6 falling edge of this cycle (QSF is switched by '7 rising).
2. This QSF timing is referred when SC isn't risen between the previous transfer cycle and &$6
falling edge of this cycle (QSF is switched by 5$6 or &$6 falling).
3. After read transfer cycle, if split read transfer cycle is executed without SC access and SC address
is 126 or 254, tSDD2 (min) must be satisfied 25 ns. Except for those cases, tSDD (min) is effective and
satisfied 5 ns.
37
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Read Transfer Cycle (2)
t RC
t RAS
t RP
RAS
t CSH
t CRP
t RCD
t RSH
t CAS
CAS
t ASR
Address
t RAD
t RAH
Row
t WS
t RAL
t ASC
t CAH
Sam Start
Address
t WH
WE
t DTHH
High-Z
I/O
(Output)
t DTS
t DTH
t FSR
t RFH
t DRD
t DTP
DT/OE
DSF
t SRS
t SC
t SDH
t SCP
t SRH
t SIS
t SOH
t SIH
t SZS
Valid
Sin
t DQD
t DQH
SAM Address MSB
t CQD
t CQH
t RQD
t RQH
38
This Material Copyrighted by Its Respective Manufacturer
t SCA
t SCA
t SCH
t SAH
QSF
t SCP
Inhibit Rising Transition
SC
SI/O
(Output)
SI/O
(Input)
t SCC
t SC
Valid Sout
HM538123B Series
Pseudo Transfer Cycle
t RC
t RAS
t RP
RAS
t CSH
t CRP
t RSH
t RCD
t CAS
CAS
t ASC
t RAH
t ASR
SAM Start
Address
Row
Address
t WS
t CAH
t WH
WE
High - Z
I/O
(Output)
t DTS
t DTH
DT/OE
t FSR
t RFH
t ES
t SEZ
t EH
DSF
t SWS
SE
t SRS
t SRD
t SCP
t SC
t SCP
Inhibit Rising Transition
SC
t SCA
t SOH
SI/O
(Output)
t SCC
t SC
Valid
Sout
t SRZ
Valid Sout
t SIS
t SID
SI/O
(Input)
t CQD
t RQD
t SIH
Valid Sin
t SIS
t SIH
Valid Sin
t CQH
t RQH
QSF
SAM Address MSB
39
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Write Transfer Cycle
t RC
t RAS
t RP
RAS
t CRP
t CSH
t RSH
t RCD
t CAS
CAS
t RAH
t ASR
Address
Row
t WS
t ASC
t CAH
SAM Start
Address
t WH
WE
High-Z
I/O
(Output)
t DTS
t DTH
DT/OE
t FSR
t RFH
DSF
t ES
t EH
t SWS
SE
t SRS
t SRD
t SWS t SC
t SCP
SC
SI/O
(Output)
SI/O
(Input)
t SCP
Inhibit Rising Transition
t SIS
t SIH
t SIS
Valid Sin
t RQD
t RQH
SAM Address MSB
40
This Material Copyrighted by Its Respective Manufacturer
t SIH
Valid Sin
t CQD
QSF
t SCC
t SC
t CQH
t SIS
t SIH
Valid Sin
HM538123B Series
Split Read Transfer Cycle
t RC
t RP
t RAS
RAS
t CSH
t RSH
t RCD
t CRP
t CRP
t CAS
CAS
t RAD
t ASR
Address
t RAL
t RAH
t ASC
SAM Start
Address Yi
Row
t WS
t CAH
t WH
WE
t OFF1
High-Z
I/O
(Output)
t DTS
t DTH
t FSR
t RFH
DT/OE
DSF
t CST
t AST
t RST
Low
SE
t SCC
t SC
t STS
SC
SI/O
(Output)
511
(255)
t SCA
n
(n+255)
n+1
(n+256)
t SCA
Valid
Sout
Valid
Sout
n+2
(n+257)
253
(509)
254
(510)
255
(511)
Yi+255
(Yi)
t SOH
t SOH
Valid Sout
t SCP
Valid
Sout
Valid
Sout
Valid
Sout
SI/O
(Input)
t SQD
t SQD
t SQH
t SQH
QSF
SAM Address MSB
41
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Split Write Transfer Cycle
t RC
t RP
t RAS
RAS
t CSH
t RSH
t RCD
t CAS
CAS
t ASR
Address
t RAL
t RAH
SAM Start
Address Yi
Row
t WS
t CAH
t ASC
t WH
WE
t OFF1
High-Z
I/O
(Output)
t DTS
t DTH
t FSR
t RFH
DT/OE
DSF
t CST
t AST
t RST
Low
SE
t SCC
t SC
t STS
SC
SI/O
(Output)
SI/O
(Input)
n
(n+255)
511
(255)
t SIS
n+1
(n+256)
t SIH
Valid
Sin
Valid Sin
t SCP
t SIS
Valid
Sin
n+3
(n+258)
n+2
(n+257)
t SIH
Valid
Sin
Valid
Sin
This Material Copyrighted by Its Respective Manufacturer
Valid
Sin
Valid Sin
t SQH
SAM Address MSB
Yi+255
(Yi)
t SIH
t SQD
t SQD
42
255
(511)
t SIS
t SQH
QSF
254
(510)
HM538123B Series
Serial Read Cycle
SE
tSCC
SC
tSCC
tSC
tSCP
tSCP
tSC
tSC
tSCA
SI/O
(Output)
Valid Sout
tSCC
tSC
tSCA
tSOH
tSEA
tSEZ
tSOH
tSCP
tSCA
Valid Sout
Valid Sout
Valid
Sout
Serial Write Cycle
tSWIS
tSWH
tSWIH
tSWS
SE
tSCC
tSC
tSCP
SC
tSIS
SI/O
(Input)
tSIH
Valid Sin
tSCC
tSC
tSCC
tSC
tSCP
tSIS
tSC
tSCP
tSIH
Valid Sin
tSIS
tSIH
Valid Sin
43
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Package Dimensions
HM538123BJ Series (CP-40D)
Unit: mm
25.80
26.16 Max
0.43 ± 0.10
0.41 ± 0.08
1.27
0.10
Dimension including the plating thickness
Base material dimension
44
This Material Copyrighted by Its Respective Manufacturer
0.31
2.30 +– 0.14
1.30 Max
20
0.25
0.80 +– 0.17
10.16 ± 0.13
0.74
3.50 ± 0.26
1
11.18 ± 0.13
21
40
9.40 ± 0.25
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
CP-40D
—
Conforms
1.73 g
HM538123B Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
45
This Material Copyrighted by Its Respective Manufacturer
HM538123B Series
Revision Record
Rev.
Date
Contents of Modification
Drawn by
Approved by
1
Mar.18, 1994
Initial issue
M. Takahashi T. Kizaki
2.0
Dec.8, 1994
Addition of figure 4: Example of row bit data
transfer
M. Takahashi T. Kizaki
Addition of description about figure 4 for write
transfer cycle
3.0
Apr. 24, 1995
AC Chracteristics
Addition of tSDD2 (min): 25/25/25/25 ns
Addition of notes 17
Timing waveforms
Read transfer cycle
Addition of tSDD2 timing
Addition of notes 3
4.0
Nov. 1997
Change of Subtitle
46
This Material Copyrighted by Its Respective Manufacturer
M. Takahashi T. Kizaki