Pr y ar in im el ¡ Semiconductor MSM54V24632A ¡ Semiconductor MSM54V24632A 11 Feb. 1998 131,072-Word ¥ 32-Bit ¥ 2-Bank SGRAM without Graphics Functions DESCRIPTION The MSM54V24632A is a synchronous graphics random access memory without graphics oriented functions; Block Write, Write per bit, Single write and Burst stop. It is organized as 128K words ¥ 32 bits ¥ 2 banks. This device can operate up to 125MHz by using synchronous interface. FEATURES • • • • • • • • • • • • • • • • 131,072-words ¥ 32 bits ¥ 2 banks memory Single 3.3 V±0.3 V power supply LVTTL compatible inputs and outputs All input signals are latched at rising edge of system clock Auto precharge and controlled precharge Internal pipelined operation: column address can be changed every clock cycle Dual internal banks controlled by A9 (Bank Address: BA) Independent byte operation via DQM0 to DQM3 Simplified function (No Block write, Write per bit, Single write and Burst stop) Programmable burst sequence (Sequential / Interleave) Programmable burst length (1, 2, 4, 8 and full page) Programmable CAS latency (1, 2 and 3) Power Down operation and Clock Suspend operation Auto refresh and Self refresh capability 1,024 refresh cycle / 16 ms Package : 100-pin plastic QFP (QFP100-P-1420-0.65-BK4) (Product : MSM54V24632A-xxGS-BK4) xx indicates speed rank. PRODUCT FAMILY Family Clock Frequency MHz (Max.) MSM54V24632A-8 125 MSM54V24632A-10 100 MSM54V24632A-12 83 Package 100-pin Plastic QFP (14 ¥ 20 mm) 1 MSM54V24632A ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) DQ29 Vss(Q) DQ30 DQ31 Vss NC NC NC NC NC NC NC NC NC NC Vcc DQ0 DQ1 Vss(Q) DQ2 100pin Plastic QFP 81 82 83 84 85 86 87 88 89 90 91 92 93 94 79 Vcc(Q) 3 78 DQ27 4 77 DQ26 5 76 Vss(Q) 6 75 DQ25 7 74 DQ24 8 73 Vcc(Q) 9 72 DQ15 10 71 DQ14 11 70 Vss(Q) 12 69 DQ13 13 68 DQ12 14 67 Vcc(Q) 15 66 Vss 16 65 Vcc 17 64 DQ11 18 63 DQ10 19 62 Vss(Q) 20 61 DQ9 21 60 DQ8 22 59 Vcc(Q) 23 58 NC 24 57 DQM3 25 56 DQM1 26 55 CLK 27 54 CKE 28 53 NC 29 52 NC 30 51 A8 50 A7 49 A6 48 A5 47 A4 Pin Name 46 Vss 45 NC 44 NC 43 NC 42 NC 41 NC 40 NC Function 39 NC 38 NC 37 NC 36 NC 35 Vcc 34 A3 33 A2 32 A1 3 95 80 DQ28 2 31 A0 Note: 96 1 Pin Name CLK 97 98 99 100 DQ3 Vcc(Q) DQ4 DQ5 Vss(Q) DQ6 DQ7 Vcc(Q) DQ16 DQ17 Vss(Q) DQ18 DQ19 Vcc(Q) Vcc Vss DQ20 DQ21 Vss(Q) DQ22 DQ23 Vcc(Q) DQM0 DQM2 WE CAS RAS CS A9 NC Function System Clock DQM0~DQM3 Data Input/Output Mask CS Chip Select DQi Data Input/Output CKE Clock Enable VCC Power Supply (3.3 V) A0 - A8 Address VSS Ground (0 V) A9 Bank Select Address VCC(Q) Data Output Power Supply (3.3 V) RAS Row Address Strobe VSS(Q) Data Output Ground (0 V) CAS Column Address Strobe NC No Connection WE Write Enable The same power supply voltage must be provided to every VCC pin and VCC(Q)pin. The same GND voltage level must be provided to every VSS pin and VSS(Q) pin. ¡ Semiconductor MSM54V24632A PIN DESCRIPTION CLK Fetches all inputs at the "H" edge. CS Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQM0, DQM1, DQM2 and DQM3. CKE Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address: RA0 – RA8 Column address: CA0 – CA7 A9 Selects bank to be activated during row address latch time and selects bank for precharge and read/ write during column address latch time. A9= "L" : Bank A, A9= "H" : Bank B RAS CAS Functionality depends on the combination. For details, see the function truth table. WE DQM0 ~DQM3 Masks the read data of two clocks later when DQM0~DQM3 is set "H" at the "H" edge of the clock signal. DQi Data inputs/outputs are multiplexed on the same pin. Masks the write data of the same clock when DQM0~DQM3 is set "H" at the "H" edge of the clock signal. 3 MSM54V24632A ¡ Semiconductor BLOCK DIAGRAM CKE CLK CS RAS CAS WE DQM0 DQM1 DQM2 DQM3 Programing Register Timing Register Latency & Burst Controller I/O Controller Bank Controller A9 Internal Col. Address Counter A0-A9 8 Input Data Register Column Address Buffers 8 9 Row Address Buffers 9 Row Decoders Word Drivers 4Mb Memory Cells Row Decoders Word Drivers 4Mb Memory Cells Sense Amplifier Column Decoders 5 32 32 Column Decoders Sense Amplifier Internal Row Address Counter Input Buffers 32 Read Data Register 32 16 Output DQ0-DQ31 Buffers ¡ Semiconductor MSM54V24632A ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (Voltages referenced to VSS) Parameter Symbol Rating Voltage on Any Pin Relative to VSS VIN, VOUT –0.5 to 4.6 V VCC Supply Voltage VCC, VCCQ –0.5 to 4.6 V °C Unit Storage Temperature Tstg –55 to 150 Power Dissipation PD* 1 W Short Circuit Current IOS 50 mA Operating Temperature Topr 0 to 70 °C *: Ta = 25°C Recommended Operating Conditions (Voltages referenced to VSS = 0 V) Symbol Min. Typ. Max. Unit VCC, VCCQ 3.0 3.3 3.6 V Input High Voltage VIH 2.0 — VCC + 0.2 V Input Low Voltage VIL –0.3 — 0.8 V Parameter Power Supply Voltage Capacitance (VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) Parameter Input Capacitance (A0 - A9) Input Capacitance (CLK, CKE, CS, RAS, CAS, WE, DQM0~DQM3) Input/Output Capacitance (DQ0 - DQ31) Symbol Typ. Max. Unit CIN1 — 5 pF CIN2 — 5 pF COUT — 7 pF 5 MSM54V24632A ¡ Semiconductor DC Characteristics Condition Parameter Symbol Bank CKE Output High Voltage VOH — — IOH = –2 mA Output Low Voltage VOL — — IOL = 2 mA 0.4 — 0.4 V Input Leakage Current ILI — — — –10 10 –10 10 –10 10 mA — — –10 10 –10 10 –10 10 mA Output Leakage Current ILO ICC1 Average Power Supply Current (Operating) ICC1D Both Banks Active 0.4 — — 180 — 160 — 140 mA 1, 2 CKE ≥ VIH tCC = min tRC = min tRRD = min No Burst — 240 — 200 — 180 mA 1, 2 CKE ≥ VIH tCC = min Average Power ICC3S Both Banks Active Supply Current (Clock Suspension) CKE £ VIL tCC = min ICC2 — CKE ≥ VIH tCC = min tRC = min No Burst Both Banks Precharge Power Supply Current (Stand by) — 80 — 70 — 60 mA 3 — 35 — 30 — 25 mA 3 — 95 — 80 — 70 mA 3 One Bank Active CKE ≥ VIH tCC = min ICC4 Both Banks Active CKE ≥ VIH tCC = min — 210 — 180 — 160 mA 1, 2 Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) ICC5 One Bank Active CKE ≥ VIH tCC = min tRC = min — 170 — 150 — 130 mA Both Banks Precharge CKE £ VIL tCC = min Average Power Supply Current (Power down) ICC7 Both Banks Precharge CKE £ VIL tCC = min Average Power Supply Current (Active Stand by) ICC3 Power Supply Current (Burst) Notes: 7 — One Bank Active Others Version –8 –10 –12 Unit Note Min. Max. Min. Max. Min. Max. 2.4 — 2.4 — 2.4 — V ICC6 — 2 — 2 — 2 mA — 2 — 2 — 2 mA 1. Measured with outputs open. 2. Address and data can be changed once or not be changed during one cycle. 3. Address and data can be changed once or not be changed during two cycles. 2 ¡ Semiconductor MSM54V24632A Mode Set Address Keys CAS Latency Operation Code A8 A7 TM 0 0 Mode Setting 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved Note: A6 A5 Burst Type A4 CL 0 0 0 1 1 0 0 1 1 1 Burst Length A3 BT A2 A1 A0 BT = 0 BT = 1 Reserved 0 Sequential 0 0 0 1 1 1 1 Interleave 0 0 1 2 2 2 0 1 0 4 4 1 3 0 1 1 8 8 0 0 Reserved 1 0 0 Reserved Reserved 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved A9 should stay "L" during mode set cycle. POWER ON SEQUENCE 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 ms or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply an Auto-refresh eight or more times. 5. Enter the mode register setting command. 7 MSM54V24632A ¡ Semiconductor AC Characteristics 1 Note 1, 2 Parameter Symbol CL = 3 Clock Cycles Time CL = 2 tCC CL = 1 MSM54V24632A-8 MSM54V24632A-10 MSM54V24632A-12 Unit Note Min. Max. Min. Max. Min. Max. 8 — 10 — 12 — ns 12 — 15 — 18 — ns 24 — 30 — 36 — ns CL = 3 Access Time from CL = 2 Clock CL = 1 — 7 — 9 — 10 ns 3, 4 tAC — 10 — 13 — 15 ns 3, 4 — 22 — 27 — 32 ns 3, 4 Clock "H" Pulse Time tCH 2.5 — 3 — 4 — ns Clock "L" Pulse Time tCL 2.5 — 3 — 4 — ns Input Setup Time tSI 2.5 — 3 — 3 — ns Input Hold Time tHI 1 — 1 — 1.5 — ns Output Low Impedance Time form Clock tOLZ 3 — 3 — 3 — ns Output High Impedance Time form Clock tOHZ — 6 — 8 — 10 ns Output Hold from Clock tOH 3 — 3 — 3 — ns RAS Cycle Time tRC 72 — 90 — 106 — ns RAS Precharge Time tRP 24 — 30 — 36 — ns RAS Active Time tRAS 48 105 60 105 72 105 ns RAS to CAS Delay Time tRCD 24 — 30 — 36 — ns Write Recovery Time tWR 16 — 20 — 24 — ns Write Command Input Time tOWD form Output 16 — 20 — 24 — ns RAS to RAS Bank Active Delay Time tRRD 16 — 20 — 24 — ns Refresh Time tREF — 16 — 16 — 16 ms Power-down Exit Set-up Time tPDE 8 — 10 — 12 — ns Input Level Transition Time tT 1 5 1 5 1 5 ns 9 3 ¡ Semiconductor MSM54V24632A AC Characteristics 2 Note 1, 2 Parameter Symbol MSM54V24632A-8 MSM54V24632A-10 MSM54V24632A-12 Unit Note CL 3 2 1 3 2 1 3 2 1 tCK 8 12 24 10 15 30 12 18 36 ns CAS to CAS Delay Time (Min.) lCCD 1 1 1 1 1 1 1 1 1 Cycle Clock Disable Time from CKE lCKE 1 1 1 1 1 1 1 1 1 Cycle Data Output High Impedance Time from DQM lDOZ 2 2 2 2 2 2 2 2 2 Cycle Data Input Mask Time from DQM lDOD 0 0 0 0 0 0 0 0 0 Cycle Data Input Time from Write Command lDWD 0 0 0 0 0 0 0 0 0 Cycle Data Output High Impedance Time from lROH Precharge Command 2 2 1 2 2 1 2 2 1 Cycle Active Command Input Time from Mode Register Set Command Input (Min.) 3 3 3 3 3 3 3 3 3 Cycle lMRD 9 MSM54V24632A ¡ Semiconductor Notes : 1. AC measurements assume tT = 1 ns. 2. The reference level for timing of input signals is 1.4 V. 3. Output load. 1.4 V Z = 50 W 50 W Output 30 pF 4. An access time is measured at 1.4 V. 5. If tT is longer than 1ns, the reference level for timing of input signals is VIH and VIL. 11 , , , , , ¡ Semiconductor MSM54V24632A TIMING WAVEFORM Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tRC CKE CS tRP RAS tRCD CAS ADDR Ra Ca0 Rb Cb0 A9 A8 Ra Rb tOH DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 tOHZ tAC Db2 Db3 tWR WE DQM0 ~DQM3 Row Active Read Command Row Active Write Command Precharge Command Precharge Command 11 MSM54V24632A ¡ Semiconductor Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 2, Burst Length = 4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK ,, , ,, tCC tCL High CKE tHI CS tSI tHI RAS lCCD tHI tSI CAS tSI ADDR tSI tSI Ra Ca Cb tHI A9 BS A8 Ra Cc tHI BS BS tAC DQ Qa BS BS tHI Db tOLZ Qc tSI tOH tOHZ tOWD tHI WE tSI DQM0 ~DQM3 Row Active Write Command Read Command 13 Precharge Command Read Command ¡ Semiconductor *Notes: MSM54V24632A 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE and DQM0, DQM1, DQM2, DQM3 are invalid. 2. When issuing an active, read or write command, the bank is selected by A9. A9 Active, read or write 0 Bank A 1 Bank B 3. The auto precharge function is enabled or disabled by the A8 input when the read or write command is issued. A8 A9 0 0 Operation After the end of burst, bank A holds the active status. 1 0 After the end of burst, bank A is precharged automatically. 0 1 After the end of burst, bank B holds the active status. 1 1 After the end of burst, bank B is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A8 and A9 inputs. A8 A9 0 0 Bank A is precharged. Operation 0 1 Bank B is precharged. 1 X Both banks A and B are precharged. 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1 CLK + tOHZ) after DQMi entry. 13 MSM54V24632A ¡ Semiconductor , , , , ,, , , , , , , , Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS Bank A Active RAS CAS lCCD ADDR Ca0 Cb0 Cc0 Cd0 A9 A8 DQ Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 tWR *Note2 WE *Note1 DQM0 ~DQM3 Read Command Read Command Write Command Write Command Precharge Command *Notes: 15 1. To write data before a burst read ends, DQMi should be asserted three cycles prior to the write command, to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. ¡ Semiconductor MSM54V24632A , , , ,, , , , , , Read & Write Cycle with Auto Precharge @ Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 17 18 19 CLK High CKE CS RAS tRRD CAS ADDR Ra Rb Ra Rb Ca Cb A9 A8 WE CAS Latency = 1 DQ Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start DQM0 ~DQM3 CAS Latency = 2 DQ Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start DQM0 ~DQM3 CAS Latency = 3 DQ Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start tWR DQM0 ~DQM3 Row Active (A-Bank) A Bank Read with Auto Precharge Row Active (B-Bank) B Bank Write with Auto Precharge B Bank Precharge Start Point 15 MSM54V24632A ¡ Semiconductor , , , , , , , Bank Interleave Random Row Read Cycle @ CAS Latency = 2, Burst Length = 4 0 CLK CKE CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 High tRC RAS CAS ADDR A9 A8 DQ WE tRRD RAa CAa RAa RBb CBb RAc RBb CAc RAc QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3 DQM0 ~DQM3 Row Active (A-Bank) Read Command (A-Bank) Read Command (B-Bank) Row Active (B-Bank) Precharge Command (A-Bank) 17 Read Command (A-Bank) Precharge Command (B-Bank) Row Active (A-Bank) 19 ¡ Semiconductor MSM54V24632A Bank Interleave Random Row Write Cycle @ CAS Latency = 2, Burst Length = 4 , , ,, , , , ,, 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb RAc CA A9 A8 RAa DQ RBb RAc DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 WE DQM0 ~DQM3 Row Active (A-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Row Active (B-Bank) Row Active (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 17 MSM54V24632A ¡ Semiconductor , , , , , , Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK High CKE *Note1 CS RAS CAS ADDR RAa CAa RBb CBb CAc CBd CAe A9 A8 RAa RAa DQ QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 lROH WE DQM0 ~DQM3 Row Active (A-Bank) Row Active (B-Bank) Read Command (A-Bank) *Note: 19 Read Command (B-Bank) Read Command (B-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Read Command (A-Bank) 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 19 , ,, , , , , ,, , ¡ Semiconductor MSM54V24632A Bank Interleave Page Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb CAc CBd A9 A8 RAa DQ RAb DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 WE DQM0 ~DQM3 Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Write Command (B-Bank) Write Command (B-Bank) Write Command (A-Bank) Precharge Command (Both Bank) 19 MSM54V24632A ¡ Semiconductor Bank Interleave Random Row Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 , , , , , 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc A9 A8 RAa RBb DQ QAa0 QAa1 QAa2 QAa3 RAc DBb0 DBb1 DBb2 DBb3 WE DQM0 ~DQM3 Row Active (A-Bank) Row Active (B-Bank) Read Command (A-Bank) 21 Precharge Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) Row Active (A-Bank) QAc0 QAc1 QAc2 QAc3 ¡ Semiconductor MSM54V24632A Bank Interleave Page Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A9 A8 DQ WE DQM0 ~DQM3 ,, , , , ,, High CAa0 CBb0 QAa0 QAa1 QAa2 QAa3 Read Command (A-Bank) CAc0 DBb0 DBb1 DBb2 DBb3 Write Command (B-Bank) QAc0 QAc1 QAc2 QAc3 Read Command (A-Bank) 21 MSM54V24632A ¡ Semiconductor Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4 0 CKE CS RAS CAS ADDR A9 A8 DQ0 - 7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ¨ , , , , , , , Ra ¨ CLK 1 *Note1 *Note1 Ca Cb Cc Ra Qa0 Qa1 Qa2 Qb0 Qb1 tOHZ *Note4 DQ8 - 15 Qa0 Qa2 Qa3 Dc0 tOHZ Qb0 Qb1 Dc2 *Note3 Dc0 Dc1 *Note2 WE DQM0 *Note4 DQM1 Row Active Read DQM Read Command *Notes: 23 1. 2. 3. 4. CLOCK Suspension Read DQM Read Command Read DQM Write DQM Write Command When CKE is deactivated, the next clock cycle will be ignored. When DQMs are asserted, the read data after two clock cycles will be masked. When DQMs are asserted, the write data in the same clock cycle will be masked. When DQM0 is set High, the input/output data of DQ0 - DQ7 will be masked. When DQM2 is set High, the input/output data of DQ8 - DQ15 will be masked. When DQM3 is set High, the input/output data of DQ16 - DQ23 will be masked. When DQM4 is set High, the input/output data of DQ24 - DQ31 will be masked. CLOCK Suspension Write DQM ¡ Semiconductor MSM54V24632A Read Interruption by Precharge Command @ Burst Length = 8 , , , ,,, ,, , ,, , ,, 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR Ra Ca A9 A8 Ra WE CAS Latency = 1 *Note1 Qa0 DQ Qa1 Qa2 Qa3 Qa4 Qa5 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa0 Qa1 Qa2 Qa3 Qa4 DQM0 ~DQM3 CAS Latency = 2 *Note2 DQ DQM0 ~DQM3 CAS Latency = 3 *Note2 DQ DQM0 ~DQM3 Row Active *Notes: Read Command Precharge Command 1. When CAS latency = 1, and if row precharge is esserted before a burst read ends, then the read data will not output after the next clock cycle of precharge command. 2. If row precharge is asserted before burst read ends when CAS latency = 2 or 3, then the read data will not output after the second clock cycle of the precharge command. 23 , , , , , , MSM54V24632A ¡ Semiconductor Power Down Mode @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK *Note2 tPDE tSI tSI *Note1 CKE tSI tREF(min.) CS RAS CAS Ra ADDR Ca A9 Ra A8 DQ Qa0 Qa1 Qa2 WE DQM0 ~DQM3 Row Active Power-down Entry *Notes: 25 Power-down Exit Clock Suspention Entry Clock Suspention Exit Read Command Precharge Command 1. When both banks are in precharge state, and if CKE is set low, then the MSM54V24632A enters powerdown mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, set CKE high for longer than tPDE, and the inputs will be set within the same cycle. , , ,,, , ¡ Semiconductor MSM54V24632A Self Refresh Cycle 0 CLK 1 2 tRCmin. CKE tSI CS RAS CAS ADDR A9 A8 DQ WE DQM0 ~DQM3 tPDE Ra BS Ra Hi - Z Self Refresh Entry Hi - Z Self Refresh Exit Row Active 25 MSM54V24632A ¡ Semiconductor Mode Register Set Cycle 0 CLK CKE CS 1 2 3 Auto Refresh Cycle 4 5 6 0 1 2 3 CAS ADDR DQ WE DQM0 ~DQM3 key 6 7 8 9 10 High tRC Ra Hi - Z MRS 27 5 11 12 ,, ,, , , High lMRD RAS 4 New Command Hi - Z Auto Refresh Auto Refresh ¡ Semiconductor MSM54V24632A FUNCTION TRUTH TABLE (Table 1) (1/2) Current State1 CS RAS CAS WE BA Idle Row Active Read Write H X L L L H L L L L L L Action ADDR X NOP X X NOP BA X ILLEGAL 2 BA CA ILLEGAL 2 BA RA Row Active L BA A8 NOP 4 H X X Auto-Refresh or Self-Refresh 5 X X H H H H H L L X H H H L X L L L L H X X X X OP Code X Mode Register write NOP L H H X X X NOP L H L H BA CA, A8 Read L H L L BA CA, A8 Write L L H H BA RA ILLEGAL 2 L L H L BA A8 Precharge L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L BA X Reserved L H L H BA CA, A8 Term Burst, start new Burst Read L H L L BA CA, A8 Term Burst, start new Burst Write L L H H BA RA ILLEGAL 2 L L H L BA A8 Term Burst, execute Row Precharge L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L BA X Reserved (Term Burst) --> Row Active L H L H BA CA, A8 Term Burst, Start new Burst Read L H L L BA CA, A8 Term Burst, start new Burst write L L H H BA RA ILLEGAL 2 L L H L BA A8 Term Burst, executo Row Precharge L L L X X X ILLEGAL Read with H X X X X X NOP (Continue Burst to End and enter Row Precharge) Auto Precharge L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 L H L H BA CA, A8 ILLEGAL 2 L H L L X X L L H X BA RA, A8 L L L X X X ILLEGAL ILLEGAL ILLEGAL 2 Write with H X X X X X NOP (Continue Burst to End and enter Row Precharge) Auto Precharge L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 L H L H BA CA, A8 ILLEGAL 2 L H L L X X L L H X BA RA, A8 L L L X X X ILLEGAL ILLEGAL 2 ILLEGAL 27 MSM54V24632A ¡ Semiconductor FUNCTION TRUTH TABLE (Table 1) (2/2) Current State1 CS RAS CAS WE BA Precharge Write Recovery Row Active Refresh Action ADDR X X NOP --> Idle after tRP H X X NOP --> Idle after tRP L BA X ILLEGAL 2 L X BA CA ILLEGAL 2 L H H BA RA ILLEGAL 2 L L H L BA A8 NOP 4 L L L X X X ILLEGAL H X X X L H H L H H L H L H X X X X X NOP L H H H X X NOP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A8 ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Row Active after tRCD L H H H X X NOP --> Row Active after tRCD L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A8 ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Idle after tRC L H H X X X NOP --> Idle after tRC L H L X X X ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL Mode Register H X X X X X NOP Access L H H H X X NOP L H H L X X ILLEGAL L H L X X X ILLEGAL L L X X X X ILLEGAL ABBREVIATIONS RA = Row Address CA = Column Address Notes: 29 BA = Bank Address AP = Auto Precharge NOP = No OPeration command 1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of tCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A8. 5. Illegal if any bank is not idle. ¡ Semiconductor MSM54V24632A FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 Self Refresh Power Down 6 6 CKEn CS RAS CAS WE ADDR Action H x X X X X X INVALID L H H X X X X Exit Self Refresh --> ABI L H L H H H X Exit Self Refresh --> ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self Refresh) H X X X X X X INVALID L H H X X X X Exit Power Down --> ABI L H L H H H X Exit Power Down --> ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL 7 L L X X X X X NOP (Continue power down mode) All Banks Idle 7 H H X X X X X Refer to Table 1 (ABI) H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H L X ILLEGAL H L L L L H X Enter Self Refresh H L L L L L X ILLEGAL L L X X X X X NOP Any State Other H H X X X X X Refer to Operations in Table 1 than Listed Above H L X X X X X Begin Clock Suspend Next Cycle L H X X X X X Enaole Clock of Next Cycle L L X X X X X Continue Clock Suspension Notes: 6. If a minimam set-up time tPDE is satisfied when CKE transitions from "L" to "H", CKE operates asynchronously so that a command can be input in the same internal clock cycle. 7. Power-down and self refresh can be entered only when all the banks are in an idle state. 29