E2G1053-18-54 This version: Jul. 1998 MSM56V16800E ¡ Semiconductor MSM56V16800E ¡ Semiconductor 2-Bank ¥ 1,048,576-Word ¥ 8-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MSM56V16800E is a 2-bank ¥ 1,048,576-word ¥ 8-bit synchronous dynamic RAM, fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES • • • • • • • Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 2-bank ¥ 1,048,576-word ¥ 8-bit configuration 3.3 V power supply, ±0.3 V tolerance Input : LVTTL compatible Output : LVTTL compatible Refresh : 4096 cycles/64 ms Programmable data transfer mode – CAS latency (1, 2, 3) – Burst length (1, 2, 4, 8, full page) – Data scramble (sequential, interleave) • CBR auto-refresh, Self-refresh capability • Package: 44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM56V16800E-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Max. Frequency Access Time (Max.) tAC1 tAC2 tAC3 MSM56V16800E-8 125 MHz 22 ns 10 ns 6 ns MSM56V16800E-10 100 MHz 27 ns 9 ns 9 ns 1/30 ¡ Semiconductor MSM56V16800E PIN CONFIGURATION (TOP VIEW) VCC DQ1 VSSQ DQ2 VCCQ DQ3 VSSQ DQ4 VCCQ NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 VSS 43 DQ8 42 VSSQ 41 DQ7 40 VCCQ 39 DQ6 38 VSSQ 37 DQ5 36 VCCQ 35 NC 34 NC 33 DQM 32 CLK 31 CKE 30 NC 29 A9 28 A8 27 A7 26 A6 25 A5 24 A4 23 VSS 44-Pin Plastic TSOP (II) (K Type) Pin Name Note: Function Pin Name Function CLK System Clock DQM Data Input/Output Mask CS Chip Select DQi Data Input/Output CKE Clock Enable VCC Power Supply (3.3 V) A0 - A10 Address VSS Ground (0 V) A11 Bank Select Address VCCQ Data Output Power Supply (3.3 V) RAS Row Address Strobe VSSQ Data Output Ground (0 V) CAS Column Address Strobe NC No Connection WE Write Enable The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/30 ¡ Semiconductor MSM56V16800E PIN DESCRIPTION CLK Fetches all inputs at the "H" edge. CS Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE and DQM. CKE Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address: RA0 – RA10 Column address: CA0 – CA8 A11 Selects bank to be activated during row address latch time and selects bank for precharge and read/ write during column address latch time. A11 = "L" : Bank A, A11 = "H" : Bank B RAS CAS Functionality depends on the combination. For details, see the function truth table. WE DQM Masks the read data of two clocks later when DQM is set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQM is set "H" at the "H" edge of the clock signal. DQi Data inputs/outputs are multiplexed on the same pin. 3/30 ¡ Semiconductor MSM56V16800E BLOCK DIAGRAM CKE CLK CS RAS CAS WE DQM Programming Register Timing Register Latency & Burst Controller I/O Controller Bank Controller A11 Internal Col. Address Counter A0 A11 9 Input Data Register Column Address Buffers 9 12 Row Address Buffers 12 8 8 Column Decoders Sense Amplifier Internal Row Address Counter Input Buffers Row Decoders Word Drivers 8Mb Memory Cells Row Decoders Word Drivers 8Mb Memory Cells 8 Read Data Register 8 8 Output Buffers DQ1 DQ8 Sense Amplifier Column Decoders 4/30 ¡ Semiconductor MSM56V16800E ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (Voltages referenced to VSS) Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT –0.5 to VCC + 0.5 V VCC Supply Voltage VCC, VCCQ –0.5 to 4.5 V Storage Temperature Tstg –55 to 125 °C Power Dissipation PD* 600 mW Parameter Short Circuit Current IOS 50 mA Operating Temperature Topr 0 to 70 °C *: Ta = 25°C Recommended Operating Conditions (Voltages referenced to VSS = 0 V) Parameter Symbol Min. Typ. Power Supply Voltage Max. Unit VCC, VCCQ 3.0 3.3 3.6 V Input High Voltage VIH 2.0 — VCC + 2.0 V Input Low Voltage VIL VSS – 2.0 — 0.8 V Capacitance (VCC = 1.4 V, Ta = 25°C, f = 1 MHz) Parameter Input Capacitance (CLK) Input Capacitance (CKE, CS, RAS, CAS, WE, DQM, A0 - A11) Input/Output Capacitance (DQ1 - DQ8) Symbol Min. Max. Unit CCLK 2.5 4 pF CIN 2.5 5 pF CI/O 4 6.5 pF 5/30 ¡ Semiconductor MSM56V16800E DC Characteristics Condition Parameter Symbol Bank CKE Output High Voltage VOH — — IOH = –2 mA Output Low Voltage VOL — — IOL = 2 mA — 0.4 — 0.4 V Input Leakage Current ILI — — — –10 10 –10 10 mA Output Leakage Current ILO — — — –10 10 –10 10 mA CKE ≥ VIH tCC = min tRC = min No Burst — 85 — 70 mA 1, 2 CKE ≥ VIH tCC = min tRC = min tRRD = min No Burst — 115 — 100 mA 1, 2 — 40 — 30 mA 3 — 3 — 3 mA 2 — 45 — 35 mA 3 ICC1 Average Power Supply Current (Operating) One Bank Active ICC1D Both Banks Active Others Version Unit Note E-8 E-10 Min. Max. Min. Max. 2.4 — — 2.4 V Both Banks Precharge CKE ≥ VIH tCC = min Average Power ICC3S Both Banks Active Supply Current (Clock Suspension) CKE £ VIL tCC = min Power Supply Current (Stand by) ICC2 One Bank Active CKE ≥ VIH tCC = min ICC4 Both Banks Active CKE ≥ VIH tCC = min — 105 — 90 mA 1, 2 Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) ICC5 One Bank Active CKE ≥ VIH tCC = min tRC = min — 80 — 70 mA Both Banks Precharge CKE £ VIL tCC = min — 2 — 2 mA Average Power Supply Current (Power down) ICC7 Both Banks Precharge CKE £ VIL tCC = min — 2 — 2 mA Average Power Supply Current (Active Stand by) ICC3 Power Supply Current (Burst) Notes: ICC6 2 1. Measured with outputs open. 2. The address and data can be changed once or left unchanged during one cycle. 3. The address and data can be changed once or left unchanged during two cycles. 6/30 ¡ Semiconductor MSM56V16800E Mode Set Address Keys CAS Latency Burst Type Burst Length A6 A5 A4 CL A3 BT A2 A1 A0 BT = 0 BT = 1 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 0 1 1 1 Interleave 0 0 1 2 2 0 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved Note: A7, A8, A9, A10 and A11 should stay "L" during mode set cycle. POWER ON SEQUENCE 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 ms or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. 7/30 ¡ Semiconductor MSM56V16800E AC Characteristics Parameter Note 1, 2 Symbol CL = 3 Clock Cycles Time CL = 2 tCC CL = 1 CL = 3 Access Time from CL = 2 Clock CL = 1 tAC Clock "H" Pulse Time Clock "L" Pulse Time MSM56V16800E-8 MSM56V16800E-10 Min. Max. Min. Max. 8 — 10 — ns 12 — 15 — ns 24 — 30 — ns — 6 — 9 ns Unit Note 3, 4 — 10 — 9 ns 3, 4 — 22 — 27 ns 3, 4 tCH 3 — 3 — ns tCL 3 — 3 — ns Input Setup Time tSI 2 — 3 — ns Input Hold Time tHI 1 — 1 — ns Output Low Impedance Time from Clock tOLZ 3 — 3 — ns Output High Impedance Time from Clock tOHZ — 9 — 8 ns Output Hold from Clock tOH 3 — 3 — ns RAS Cycle Time tRC 70 — 90 — ns RAS Precharge Time tRP 20 — 30 — ns ns RAS Active Time tRAS 48 105 60 105 RAS to CAS Delay Time tRCD 20 — 30 — ns Write Recovery Time tWR 8 — 15 — ns Write Command Input Time tOWD from Output 20 — 20 — ns RAS to RAS Bank Active Delay Time tRRD 20 — 20 — ns Refresh Time tREF — 64 — 64 ms Power-down Exit Set-up Time tPDE 10 — 10 — ns Input Level Transition Time tT — 3 — 3 ns CAS to CAS Delay Time (Min.) lCCD 1 1 Cycle Clock Disable Time from CKE lCKE 1 1 Cycle Data Output High Impedance Time from DQM lDOZ 2 2 Cycle Data Input Mask Time from DQM lDOD 0 0 Cycle Data Input Time from Write Command lDWD 0 0 Cycle Data Output High Impedance Time from Precharge Command lROH CL CL Cycle Active Command Input Time from Mode Register Set Command Input (Min.) lMRD 3 3 Cycle 3 8/30 ¡ Semiconductor MSM56V16800E Notes : 1. AC measurements assume that tT = 1 ns. 2. The reference level for timing of input signals is 1.4 V. 3. Output load. Output 50 pF External Load 4. The access time is defined at 1.5 V. 5. If tT is longer than 1 ns, then the reference level for timing of input signals is VIH and VIL. 9/30 , , , , , , ¡ Semiconductor MSM56V16800E TIMING WAVEFORM Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tRC CKE CS tRP RAS tRCD CAS ADDR Ra Ca0 Rb Cb0 A11 A10 Ra Rb tOH DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 tOHZ tAC Db2 Db3 tWR WE DQM Row Active Read Command Row Active Write Command Precharge Command Precharge Command 10/30 ¡ Semiconductor MSM56V16800E Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 2, Burst Length = 4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ,,, ,, CLK tCC tCL High CKE CS tSI tHI RAS lCCD tHI tSI CAS tSI ADDR tSI tSI Ra Ca Cb tHI A11 BS A10 Ra Cc tHI BS BS tAC DQ Qa BS BS tHI Db tOLZ Qc tSI tOH tOHZ tOWD tHI WE tSI DQM Row Active Write Command Read Command Precharge Command Read Command 11/30 ¡ Semiconductor *Notes: MSM56V16800E 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE and DQM are invalid. 2. When issuing an active, read or write command, the bank is selected by A11. A11 Active, read or write 0 Bank A 1 Bank B 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 A11 0 0 After the end of burst, bank A holds the idle status. Operation 1 0 After the end of burst, bank A is precharged automatically. 0 1 After the end of burst, bank B holds the idle status. 1 1 After the end of burst, bank B is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs. A10 A11 0 0 Bank A is precharged. 0 1 Bank B is precharged. 1 X Both banks A and B are precharged. Operation 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1 CLK + tOHZ) after DQM entry. 12/30 ¡ Semiconductor MSM56V16800E , ,,, , ,, , ,, , Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 CLK CKE CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 High Bank A Active RAS CAS lCCD ADDR A11 A10 DQ Ca0 Cb0 Qa0 Cc0 Qa1 Qb0 Qb1 Dc0 Cd0 Dc1 tOWD WE Dd0 tWR *Note2 *Note1 DQM Read Command Read Command Write Command Write Command Precharge Command *Notes: 1. To write data before a burst read ends, DQM should be asserted three cycles prior to the write command to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 13/30 , , , ,, , ,,, , , , ¡ Semiconductor MSM56V16800E Read & Write Cycle with Auto Precharge @ Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 17 18 19 CLK High CKE CS RAS tRRD CAS ADDR Ra Rb Ra Rb Ca Cb A11 A10 WE CAS Latency = 1 DQ Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start DQM CAS Latency = 2 DQ Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start DQM CAS Latency = 3 DQ Qa0 Qa1 Qa2 Qa3 A-Bank Precharge Start tWR DQM Row Active (A-Bank) A Bank Read with Auto Precharge Row Active (B-Bank) B Bank Write with Auto Precharge B Bank Precharge Start Point 14/30 ,,, , ,,,, ¡ Semiconductor MSM56V16800E Bank Interleave Random Row Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS tRC RAS tRRD CAS ADDR RAa CAa RBb CBb RAc CAc A11 A10 RAa RBb DQ RAc QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3 WE DQM Row Active (A-Bank) Read Command (A-Bank) Read Command (B-Bank) Row Active (B-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Precharge Command (B-Bank) Row Active (A-Bank) 15/30 ¡ Semiconductor MSM56V16800E , , ,, , ,, ,,, Bank Interleave Random Row Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb RAc CA A11 A10 RAa DQ RBb RAc DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 WE DQM Row Active (A-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Row Active (B-Bank) Row Active (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 16/30 ,,,, ¡ Semiconductor MSM56V16800E Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE *Note1 CS RAS CAS ADDR RAa CAa RBb CBb CAc CBd CAe A11 A10 RAa RAa DQ QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 lROH WE DQM Row Active (A-Bank) Row Active (B-Bank) Read Command (A-Bank) *Note: Read Command (B-Bank) Read Command (B-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Read Command (A-Bank) 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 17/30 ¡ Semiconductor MSM56V16800E Bank Interleave Page Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS , , , RAS CAS ADDR RAa CAa RBb CBb CAc CBd A11 A10 RAa DQ RAb DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Write Command (B-Bank) Write Command (B-Bank) Write Command (A-Bank) Precharge Command (Both Bank) 18/30 ¡ Semiconductor MSM56V16800E , , , , , , , , Bank Interleave Random Row Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc A11 A10 RAa RBb DQ QAa0 QAa1 QAa2 QAa3 RAc DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 WE DQM Row Active (A-Bank) Row Active (B-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) Row Active (A-Bank) 19/30 ¡ Semiconductor MSM56V16800E Bank Interleave Page Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ,,, , ,, , , , CLK High CKE CS RAS CAS ADDR CAa0 CBb0 CAc0 A11 A10 DQ QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 WE DQM Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) 20/30 ¡ Semiconductor MSM56V16800E Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4 0 CKE CS RAS CAS ADDR A11 A10 DQ1 - 8 2 3 4 5 6 7 DQM 9 10 11 12 13 14 15 16 17 18 19 ¨ , ,,, Ra *Note1 *Note1 Ca Cb Qa0 Row Active Read Command *Notes: Cc Ra Qa1 Qa2 Qb0 Qb1 tOHZ *Note2 WE 8 ¨ CLK 1 CLOCK Suspension Read DQM Read Command Dc0 tOHZ Read DQM Dc2 *Note3 Write DQM Write Command CLOCK Suspension Write DQM 1. When Clock Suspension is asserted, the next clock cycle is ignored. 2. When DQM is asserted, the read data after two clock cycles is masked. 3. When DQM is asserted, the write data in the same clock cycle is masked. 21/30 ,, , , , ,, ¡ Semiconductor MSM56V16800E Read to Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 Da1 Da2 Da3 12 13 14 15 16 17 18 19 CLK CKE CS *Note1 RAS tRCD CAS ADDR Ra Ca0 Ca0 A11 A10 Ra DQ Da0 tWR WE DQM Row Active Read Command Precharge Command Write Command *Note: 1. In case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. DQM must be high at least 3 clocks prior to the write command. 22/30 ¡ Semiconductor MSM56V16800E Read Interruption by Precharge Command @ Burst Length = 8 , ,, , ,,,, , ,,, , ,, 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR Ra Ca A11 A10 Ra WE CAS Latency = 1 *Note1 Qa0 DQ Qa1 Qa2 Qa3 Qa4 Qa5 lROH DQM CAS Latency = 2 *Note2 DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 lROH DQM CAS Latency = 3 *Note3 DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 lROH DQM Row Active *Notes: Read Command Precharge Command 1. When the CAS latency = 1, and if row precharge is asserted before a burst read ends, then the read data will not output after the next clock cycle of the precharge command. 2. When the CAS latency = 2, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. 3. When the CAS latency = 3, and if row precharge is asserted before burst read ends, then the read data will not output after the third clock cycle of the precharge command. 23/30 ,,, , ,, , ¡ Semiconductor MSM56V16800E Power Down Mode @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI *Note1 tPDE *Note2 tSI tSI CKE CS RAS CAS Ra ADDR Ca A11 Ra A10 DQ Qa0 Qa1 Qa2 WE DQM Row Active Power-down Entry *Notes: Power-down Exit Clock Suspention Entry Clock Suspention Exit Read Command Precharge Command 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16800E enters powerdown mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than tPDE (1 CLK). 24/30 , ,,, , ¡ Semiconductor MSM56V16800E Self Refresh Cycle 0 1 2 CLK tRC CKE tSI CS RAS CAS ADDR Ra A11 BS A10 Ra DQ Hi - Z Hi - Z WE DQM Self Refresh Entry Self Refresh Exit Row Active 25/30 ¡ Semiconductor MSM56V16800E , , , , ,,,, , , Auto Refresh Cycle Mode Register Set Cycle 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK High CKE High CS tRC lMRD RAS CAS ADDR key Ra Hi - Z DQ Hi - Z WE DQM MRS New Command Auto Refresh Auto Refresh 26/30 ¡ Semiconductor MSM56V16800E FUNCTION TRUTH TABLE (Table 1) (1/2) Current State1 CS RAS CAS WE BA Idle Row Active Read Write Action ADDR H X X X X X NOP L H H H X X NOP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA Row Active L L H L BA A10 NOP 4 L L L H X X Auto-Refresh or Self-Refresh 5 L L L L L OP Code H X X X X X Mode Register Write NOP L H H X X X NOP L H L H BA CA, A10 Read L H L L BA CA, A10 Write L L H H BA RA ILLEGAL 2 L L H L BA A10 Precharge L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L BA X Reserved L H L H BA CA, A10 Term Burst, start new Burst Read L H L L BA CA, A10 Term Burst, start new Burst Write L L H H BA RA ILLEGAL 2 L L H L BA A10 Term Burst, execute Row Precharge L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L BA X ILLEGAL 2 L H L H BA CA, A10 Term Burst, start new Burst Read L H L L BA CA, A10 Term Burst, start new Burst Write L L H H BA RA ILLEGAL 2 L L H L BA A10 Term Burst, execute Row Precharge L L L X X X ILLEGAL Read with H X X X X X NOP (Continue Burst to End and enter Row Precharge) Auto Precharge L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 L H L H BA CA, A10 ILLEGAL 2 L H L L X X L L H X BA RA, A10 ILLEGAL ILLEGAL 2 L L L X X X ILLEGAL Write with H X X X X X NOP (Continue Burst to End and enter Row Precharge) Auto Precharge L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 L H L H BA CA, A10 ILLEGAL 2 L H L L X X L L H X BA RA, A10 L L L X X X ILLEGAL ILLEGAL 2 ILLEGAL 27/30 ¡ Semiconductor MSM56V16800E FUNCTION TRUTH TABLE (Table 1) (2/2) Current State1 CS RAS CAS WE BA Precharge Write Recovery Row Active Action ADDR H X X X X X NOP --> Idle after tRP L H H H X X NOP --> Idle after tRP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 NOP 4 L L L X X X ILLEGAL H X X X X X NOP L H H H X X NOP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Row Active after tRCD L H H H X X NOP --> Row Active after tRCD L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Idle after tRC L H H X X X NOP --> Idle after tRC L H L X X X ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL Mode Register H X X X X X NOP Access L H H H X X NOP L H H L X X ILLEGAL L H L X X X ILLEGAL L L X X X X ILLEGAL Refresh ABBREVIATIONS RA = Row Address CA = Column Address Notes: BA = Bank Address AP = Auto Precharge NOP = No OPeration command 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of lCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 28/30 ¡ Semiconductor MSM56V16800E FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 Self Refresh Power Down CKEn CS RAS CAS WE H X X X X L H H X X L H L H H L H L H H L H L H L L H L L X L L X X X X ADDR Action X INVALID X X Exit Self Refresh --> ABI H X Exit Self Refresh --> ABI L X ILLEGAL X X ILLEGAL X X ILLEGAL X X NOP (Maintain Self Refresh) H X X X X X X INVALID L H H X X X X Exit Power Down --> ABI L H L H H H X Exit Power Down --> ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL 6 L L X X X X X NOP (Continue power down mode) H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H L X ILLEGAL H L L L L H X Enter Self Refresh H L L L L L X ILLEGAL L L X X X X X NOP Any State Other H H X X X X X Refer to Operations in Table 1 than Listed Above H L X X X X X Begin Clock Suspend Next Cycle L H X X X X X Enable Clock of Next Cycle L L X X X X X Continue Clock Suspension All Banks Idle 6 (ABI) Note: 6. Power-down and self refresh can be entered only when all the banks are in an idle state. 29/30 ¡ Semiconductor MSM56V16800E PACKAGE DIMENSIONS (Unit : mm) TSOPII44-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.54 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 30/30