PI6C2509-133 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Low-Noise Phase-Locked Loop Clock Driver with 9 Clock Outputs Product Features Product Description Operating Frequency up to 150 MHz The PI6C2509-133 is a quiet, low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing low-noise clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay feature allows the CLK_IN input clock to be distributed, providing 5 clocks for the first bank, and an additional 4 clocks for the second bank. Low-Noise Phase-Locked Loop Clock Distribution to meet 133 MHz Registered DIMM Synchronous DRAM module specifications for server/workstation/PC applications Allows Clock Input to have Spread Spectrum modulation for EMI reduction Zero Input-to-output delay: Distribute One Clock Input to one bank of five and one bank of four outputs, with separate output enables This clock driver is designed to meet the PC133 SDRAM Registered DIMM specification. For test purposes, the PLL can be bypassed by strapping AVCC to ground. Low jitter: Cycle-to-Cycle jitter ±75ps max. On-chip series damping resistor at clock output drivers for low noise and EMI reduction Operates at 3.3V VCC Package: Plastic 24-pin TSSOP (L) Logic Block Diagram Product Pin Configuration 1G 5 AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC 1G FB_OUT 1Y[0:4] 2G CLK_IN FB_IN AVCC 4 PLL 2Y[0:3] FB_OUT 1 24 1 23 2 22 3 4 24-Pin 21 20 5 L 19 6 18 7 17 8 16 9 15 10 14 11 13 12 CLK_IN AVCC VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC 2G FB_IN PSXXXX 06/01/99 PI6C2509-133 Low-Noise, Phase-Locked Loop Clock Driver with 9 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Functional Table Input Control Outputs X(1)G X(1)Y[0:3] FB_O UT L L CLK _IN H CLK _IN CLK _IN Note: 1. X is either 1 or 2 Pin Functions Pin Name Pin No. Type De s cription CLK_IN 24 I Clock input. CLK_IN allows spread spectrum. FB_IN 13 I Feedback input. FB_IN provides the feedback signal to the internal PLL. 1G 11 I Output bank enable. When 1G is LOW, outputs 1Y[0:4] are disabled to a logic low state. When 1G is HIGH, all outputs 1Y[0:4] are enabled. 2G 14 I Output bank enable. When 2G is LOW, outputs 2Y[0:3] are disabled to a logic low state. When 2G is HIGH, all outputs 2Y[0:3] are enabled. FB_OUT 12 O Feedback output. FB_OUT is dedicated for external feedback. FB_OUT has an embedded series- damping resistor of the same value as the clock outputs 1Yx, 2Yx. 1Y[0:4] 3,4,5,8,9 O Clock outputs. These outputs provide low- skew copies of CLK_IN. Each output has an embedded series- damping resistor. 2Y[3:0] 16,17, 20, 21 O Clock outputs. These outputs provide low- skew copies of CLK_IN. Each output has an embedded series- damping resistor. AVCC 23 Power Analog power supply. AVCC can be also used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK_IN. is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VCC 2,10,15,22 Power Power supply. GND 6,7,18,19 Ground Ground. 2 PSXXXX 06/01/99 PI6C2509-133 Low-Noise, Phase-Locked Loop Clock Driver with 9 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Specifications Absolute maximum ratings over operating free-air temperature range. Symbol Parame te r M in. VI Input voltage range VO Output voltage range M ax. VCC + 0.5 - 0.5 Units V VI_DC DC input voltage +5.0 IO_DC DC output current 100 mA Power Maximum power dissipation at TA = 55°C in still air 1.0 W TSTG Storage temperature 150 °C - 65 Note: Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. Parame te r Te s t Conditions VCC ICC VI = VCC or GND; IO = 0(1) 3.6V CI VI = VCC or GND CO VO = VCC or GND M in. Typ. M ax. Units 10 µA 4 3.3V pF 6 Note: 1. Continuous output current Recommended Operating Conditions Symbol Parame te r M in. M ax. VCC Supply voltage 3.0 3.6 VIH High level input voltage 2.0 VIL Low level input voltage VI Input voltage 0.0 VCC TA O perating free- air temperature 0 70 0.8 Units V ºC Electrical characteristics over recommended operating free-air temperature range Pull Up/Down Currents of PI6C2509-133, VCC = 3.0V Symbol IOH IOL Parame te r Condition M in. Pull- up current VOUT = 2.4V - 13.6 Pull- up current VOUT = 2.0V - 22 Pull- down current VOUT = 0.8V 19 Pull- down current VOUT = 0.55V 13 3 M ax. Units mA PSXXXX 06/01/99 PI6C2509-133 Low-Noise, Phase-Locked Loop Clock Driver with 9 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 AC Specifications Timing requirements over recommended ranges of supply voltage and operating free-air temperature. Symbol Parame te r FCLK M in. M ax. Units Input clock frequency 25 150 MHz Input clock duty cycle 40 60 % 1 ms Stabilization time after power up Switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL=30pF Parame te r From tphase error, with and without Spread Spectrum CLK_IN↑ at 133 MHz Jitter, cycle- to- cycle with and without Spread Spectrum Any Output or FB_OUT in CLKn at 133 MHz Skew, at 133 MHz Any Y or FB_OUT VCC = 3.3V ±0.3V, 0-70°C To M in. Typ. M ax. FB_IN↑ 150 +150 Output or FB_OUT in CLKn+1 75 +75 Units ps 150 Any Y or FB_OUT Duty cycle tr, rise- time, 0.4V to 2.0V 45 50 55 1.0 tf, fall- time, 2.0V to 0.4V 1.1 % ns Note: These switching parameters are guaranteed, but not production tested. Package Mechanical Information Plastic 24-pin Thin Shrink Small-Outline Package (L package). 24 .169 .177 1 .303 .311 7.7 7.9 4.3 4.5 SEATING PLANE .047 Max 1.20 .004 .008 .007 .012 0.19 0.30 .0256 BSC 0.65 X.XX X.XX .002 .006 0.05 0.15 0.45 0.75 0.09 0.20 .018 .030 Ordering Information .252 BSC 6.4 DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS Part Numbe r Ope rating Fre que ncy Range Orde ring P/N PI6C2509- 133 25 MHz - 150 MHz PI6C2509- 133L Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 4 PSXXXX 06/01/99