HC2510C HC2510C General Description Features l l l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Ten Outputs No External RC Network Required External Feedback (FBIN) Pin is Used to Synchronize the Outputs to the Clock Input Separate Output Enable for Each Output Bank Operates at 3.3 V Vcc 125 MHz Maximum Frequency On-chip Series Damping Resistors Support Spread Spectrum Clock(SSC) Synthesizers ESD Protection Exceeds 3000 V per MIL-STD883, Method 3015 ; Exceeds 350 V Using Machine Model ( C = 200 pF, R = 0 ) Latch-Up Performance Exceeds 400 mA per JESD 17 Packaged in Plastic 24-Pin Thin Shrink SmallOutline Package Pin Configuration low-skew, low jitter, phaselocked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM. The HC2510C operates at 3.3V Vcc and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. The propagation delay from the CLK input to any clock output is nearly zero. Ten outputs provide low-skew and low-jitter clocks. All outputs can be enabled or disabled via the control input(G). Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The HC2510C is specially designed to interface with high speed SDRAM applications in the range of 25MHz to 125MHz and includes an internal RC network which provides excellent jitter characteristics and eliminates the needs for external components. For the test purpose, the PLL can be bypassed by strapping AVcc to ground. The HC2510C is characterized for operation from 0°C to 85°C. TSSOP 24 PACKAGE (TOP VIEW) AGND 1 24 CLK Vcc 2 23 AVcc 1Y0 3 22 Vcc 1Y1 4 21 1Y9 1Y2 5 20 1Y8 GND 6 19 GND GND 7 18 GND 1Y3 8 17 1Y7 1Y4 9 16 1Y6 Vcc 10 15 1Y5 G 11 14 Vcc 12 13 FBIN FBOUT The HC2510C is a Function Table INPUTS G 1 CLK OUTPUTS 1Y (0:9) FBOUT X L L L L H L H H H H H HC2510C Functional Block Diagram G 11 3 4 5 8 9 1Y0 1Y1 1Y2 1Y3 1Y4 15 1Y5 16 17 20 CLK AV CC 1Y7 1Y8 24 21 PLL FBIN 1Y6 1Y9 13 12 23 2 FBOUT HC2510C Table 1. Pin Description Pin Name Pin No. Type Functional Description CLK 24 I FBIN 13 I G 11 I FBOUT 12 O 1Y(0:9) 3,4,5,8,9 15,16,17,20,2 1 O AVcc 23 Power AGND 1 Groun d Clock Input. CLK provides the reference signal to the internal PLL. Feedback Input. FBIN provides the feedback signal to the internal PLL. Output Bank Enable. When G is high, all outputs 1Y(0:9) are enabled. When G is low, Outputs 1Y(0:9) are disable to a logic-low state. Feedback Output. FBOUT completes the feedback loop of the PLL by being wired to FBIN. Clock Outputs. These outputs provide low-skew copies of CLKIN. Each output has an embedded series-damping resistor. Analog Power Supply. AVcc provides the power reference for the analog circuitry. AVcc can be also used to bypass the PLL for the test purpose. When AVcc is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Analog Ground. AGND provides the ground reference for the analog circuitry. Vcc 2,10,14,22 Power Power Supply GND 6,7,18,19 Groun d Ground Table 2. Absolute Maximum Ratings Over Operating Free-air Temperature Range Symbols Parameter Value Unit Vcc Supply Voltage Range -0.5 to 4.6 V VI Input Voltage Range -0.5 to 6.5 V Vo Voltage Range applied to any input in the high or low state -0.5 to Vcc+0.5 V IIK Input Clamp Current ±50 mA VI <0 or V I >Vcc IOK Output Clamp Current ±50 mA Vo<0 or Vo >Vcc Io Continuous Output Current ±50 mA Vo =0 to Vcc PMAX Maximum Power Dissipaiton 0.7 W Tstg Storage Temperature Range - 65 to 150 °C 3 Conditions HC2510C Table 3. Recommended Operating Conditions Value Min Max Symbol Parameter AVCC VIH VIL VI IOH IOL TA Supply Voltage High-level Input Voltage Low-level Input Voltage Input Voltage High-level Output Current Low-level Output Current Operating Free-air Temperature 3 2 0 0 Unit 3.6 Condition V V V V mA mA °C 0.8 VCC -12 12 85 Table 4. Electrical Characteristics Over Recommended Operating Free-air Temperature Range Symbol Min Value Typ VIK Max AVCC (V) Test Conditions V II = -18mA IOH = -100µA IOH = -12 mA IOH = -6 mA IOL =100 mA IOL = 12 mA IOL = 6 mA VI =VCC or GND VI =VCC or GND, IO = 0, Ouputs: low or high One input at VCC - 0.6V, Other Inputs at VCC or GND VI = VCC or GND VO = VCC or GND II 0.2 0.8 0.55 ±5 µA 3 Min to Max 3 3 Min to Max 3 3 3.6 ICC 10 µA 3.6 ∆ICC 500 µA 3.3 to 3.6 pF pF 3.3 3.3 VOH -1.2 Unit Vcc-0.2 2.1 2.4 V VOL Ci Co V 4 6 Table 5.Timing Requirements Over Recommended Ranges of Supply Voltage and Operating free-air Temperature Symbol Parameter fclock Clock Frequency Input Clock Duty Cycle Stabilization Time♣ Value Min Max 25 40 125 60 1 ♣ Time to obtain phase lock of its feedback signal to its reference signal. 4 Unit MHz % ms HC2510C Table 6. Switching Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-air Temperature. (CL=30pF) = Parameter From(Input) tphase error ♣ 66MHz < CLKIN↑< 100MHz CLKIN↑ = 100MHz tsk Any Y of FBOUT Jitter(pk-pk) CLKIN > 66MHz Duty Cycle CLKIN > 66MHz TO(Output) tr tf VCC = 3.3V VCC = ±0.165V 3.3V±0.3V Unit Min Typ Max Min Typ Max FBIN↑ 150 150 ps FBIN↑ Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT -50 50 ps 200 ps -100 100 ps 45 55 % 1.3 1.9 0.8 2.1 ns 1.7 2.5 1.2 2.7 ns =These parameters are not production tested. ♣ Phase error does not include jitter. Figure 1. Load Circuit and Voltage Waveforms 3V 50% V CC From Output Under Test 0V Input 30pF 500§Ù tpd VOH 2V 2V 50% V CC 0.4V 0.4V VOL Output tr tf Voltage Waveforms Propagation Delay Times Load Circuit For Outputs Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz, Zo =50Ω, tr =1.2ns, tf=1.2ns 2.The outputs are measured one at a time with one transition per measurement. 5 HC2510C Figure 2. Phase Error and Skew Calculation CLKIN FBIN tphase error Any Any tSK FBOUT Any tSK 6