PI6C671F 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Clock Generator for Pentium Modules Features Description Supports Pentium or Pentium II CPU modules The PI6C671F is a mixed-voltage clock generator designed to provide all timing signals for Intel Pentium/Pentium II module-based motherboards. It provides four CPU, seven PCI, and up to eight SDRAM clocks. Additionally, three reference clocks (same frequency as the crystal) and two selectable 24/48 MHz clocks are available. Spread Spectrum capability reduces EMI Low power consumption Four CPU Clocks with VDDQ2 of 3.3V or 2.5V Enhanced drive on CPUCLK0 Pericom design improvements resulted in a low-power device optimized for 2.5V CPU operation. A special spread-spectrum feature may be enabled to minimize EMI. Seven PCI synchronous clocks (3.3V) One IOAPIC Clock @14.31818 MHz (Power from pin 46), with VDDQ1 of 3.3V or 2.5V The two-wire I2C serial interface can be used to reduce circuit noise and power consumption. I2C control lets you enable/disable each clock output driver, change CPU frequencies, and select 24 or 48 MHz outputs. Two 48/24 MHz clocks (3.3V) Six/eight SDRAM clocks (3.3V) Three Ref. Clocks @14.31818 MHz (3.3V) Internal crystal loading capacitor A power-down function (pin 44) puts the whole system in a lowpower mode by stopping the crystal oscillator and both PLLs. CPU and PCI clocks may also be stopped by the CPU_STOP# (pin 27), and PCI _STOP# (pin 26) functions. Ref. 14.31818 MHz crystal oscillator input Separate 66/60# MHz select pin Separate power management MODE control pin I2C Note: Purchase of I2C components from Pericom conveys a license to use them in an I2C system as defined by Philips. 2-Wire Serial Interface 48-pin SSOP Package (V) and TSSOP (A) Block Diagram Pin Configuration REF1 REF0 VSS XIN XOUT MODE VDDQ3 PCICLK_F PCICLK0 VSS PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDQ3 PCICLK5 VSS SEL66/60# SDATA SDCLK VDDQ3 48/24MHz 48/24MHz VSS Buffers 3 XIN REF0,1,2 REF VDDQ1 OSC XOUT IOAPIC0 VDDQ2 4 CPUCLK0-3 VDDQ3 PLL1 SEL Up to 8 SDRAM0-7 ÷2 6 PCICLK0-5 PCICLK_F 48/24 MHz PLL2 48/24 MHz All trademarks are of their respective companies. 392 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 10 48-Pin 39 38 11 A, V 37 12 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 25 24 VDD REF2 VDDQ1 IOAPIC0 PWR_DWN# VSS CPUCLK0 CPUCLK1 VDDQ2 CPUCLK2 CPUCLK3 VSS SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5 VDDQ3 SDRAM6/CPU_STOP# SDRAM7/PCI_STOP# VDD PS8137A 03/15/99 PI6C671F Clock Generator for Pentium Modules 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Descriptions 1 Signal Name Type Qty Pin Description Xin I 1 4 Crystal oscillator input or input for externally generated reference signal. X out O 1 5 Crystal oscillator output. Connect to external parallel resonant crystal. Select pin for enabling 66 MHz or 60 MHz. H=66 MHz, L=60 MHz. Has an internal pull-up resistor. 2 SEL66/60# I 1 18 CPUCLK (0-3) O 4 42,41,39,38 SD R A M O 6 29,30,32,33,35,36 SDRAM6/CPU_STOP# bi-dir 1 27 MODE=1: SDRAM6, MODE=0: CPU_STOP#. SDRAM7/PCI_STOP# bi-dir 1 26 MODE=1: SDRAM7, MODE=0: PCI_STOP#. MODE I 1 6 Mode Select pin for enabling power management features at pins 26 & 27. Has an internal pull-up resistor. PCICLK(0-5) O 6 9 , 1 1 , 1 2 , 1 3 , 1 4, 1 6 PCICLK_F O 1 8 R E F 0,R E F 1,R E F 2 O 3 2 , 1 , 47 IOAPIC0 O 1 45 IOAPIC0 clock outputs. Powered by VDDQ1, can be 2.5V or 3.3V PWR_DWN# I 1 44 PWR_DWN#, active LOW. 48/24MHz O 2 22,23 SDATA I 1 19 Serial data input for I2C control. SD C L K I 1 20 Clock input for I2C control. V SS Ground 7 VDD Power 2 2 5 , 48 VDDQ3 Power 5 7,15,21,28,34 VDDQ2 Power 1 40 CPUCLK power supply. Can be either 2.5V or 3.3V. VDQ1 Power 1 46 IOAPIC power supply. Can be either 2.5V or 3.3V. CPU & Host clock outputs. Powered by VDDQ2, can be 2.5V or 3.3V. 3 SDRAM clocks 60/66 MHz. Powered by VDDQ3(3.3V). Low skew PCI clock outputs. TTL compatible. Powered by VDDQ3 (3.3V). Free running synchronous PCI clock. Stops when in shut down mode. 5 14.318 MHz buffered reference clock outputs. 6 Selectable 48/24 MHz clock output. Powered by VDDQ3 (3.3V). 7 3,10,17,24,31,37,43 Ground pins for the device. 8 Power supply for analog circuits and core logic. 3.3V I/O power supply. 9 10 Driver Types Pin Driver Type Symbol 2 D R E F0 1,47 C REF1, REF2 14.318 MHz clock output. 8 E PCICLK_F 9,11,12, 13.14,16 E PCICLK PCI clock outputs TTL compatible 3.3V. 22,23 C 48/24MHz 48/24 MHz clock output 3.3V selectable. 26,27,29,30, 32,33,35,36 D SD R A M SDRAM clocks 60/66 MHz. 38,39,41,42 A C PU C L K CPU and host clock outputs: 2.5V or 3.3V B IOAPIC0, IOAPIC1 IOAPIC clock output: 2.5V or 3.3V. 45 4 Description 11 14.318 MHz clock output. 12 Free running clock during PCICLK stopped. 393 13 14 15 PS8137A 03/15/99 PI6C671F Clock Generator for Pentium Modules 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Power Management Functions Any or all clocks can be enabled or shut down via the I2C control interface. All clocks stop in the LOW state. CPU, SDRAM, and PCI clocks wait for one rising edge of PCICLK_F followed by a falling CPU_STOP# PCI_STOP# edge of the clock of interest before settling in the LOW state. To reduce power consumption the PI6C671F clocks may be disabled in accordance with the following table. PWR_DWN# CPUCLK, SDRAM PCICLK Other Clocks Crystal & VCOs X X 0 LOW LOW LOW Off 0 0 1 LOW LOW Running Running 0 1 1 LOW 33/30 MHz Running Running 1 0 1 66/60 MHz LOW Running Running 1 1 1 66/60 MHz 33/30 MHz Running Running 2-Wire I2C Control The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C671F is a slave receiver device. It can not be read back. Sub addressing is not supported. All preceding bytes must be sent in order to change one of the control bytes. Every bite put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers SDATA changes only when SDCLK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SDCLK is HIGH indicates a “start” condition. A LOW to HIGH transition on SDATA while SDCLK is HIGH is a “stop” condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW= write to addressed device). If the device’s own address is detected, PI6C671F generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgement of the address byte (D2), two more bytes must be sent: 1. “Command Code” byte, and 2. “Byte Count” byte. Although the data bits on these two bytes are “don’t care,” they must be sent and acknowledged. The I2C interface is disabled when the PWR_DWN# pin is LOW. Preset control register contents are retained. I2C Serial Configuration Byte 0: Functional and Frequency Select Clock Register (1 = enable, 0 = disable) Bit Pin No. @ Powerup Description 7 0 (Reserved) 6 0 (Reserved, don't change) 5 0 (Reserved, don't change) 4 0 (Reserved, don't change) 3 23 1 48/24 MHz (Freq Select) 1 = 48 MHz, 0 =24 MHz 2 22 1 48/24 MHz (Freq Select) 1 = 48 MHz, 0 = 24 MHz 1 0 0 0 Bit1 1 1 0 0 Bit0 1 : Tri-State 0 : Spread Spectrum 1 : Test Mode 0 : Normal Operation 394 PS8137A 03/15/99 PI6C671F Clock Generator for Pentium Modules 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Byte 1: CPU 24/48 MHz Active/Inactive Register (1 = enable, 0 = disable) 1 Bit Pin No. 48/24 MHz (Active/Inactive) 7 N/A SDRAM15 (Active/Inactive) 1 48/24 MHz (Active/Inactive) 6 N/A SDRAM14 (Active/Inactive) X (Reserved) 5 N/A SDRAM13 (Active/Inactive) Bit Pin No. @ Powerup 7 23 1 6 22 5 Byte 4: SDRAMActive/Inactive Register (1 = enable, 0 = disable) Description Description 4 N/A X CPUCLK4 (Active/Inactive) 4 N/A SDRAM12 (Active/Inactive) 3 38 1 CPUCLK3 (Active/Inactive) 3 N/A SDRAM11 (Active/Inactive) 2 39 1 CPUCLK2 (Active/Inactive) 2 N/A SDRAM10 (Active/Inactive) 1 41 1 CPUCLK1 (Active/Inactive) 1 N/A SDRAM9 (Active/Inactive) 0 42 1 CPUCLK0 (Active/Inactive) 0 N/A SDRAM8 (Active/Inactive) 7 3 4 5 Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable) Bit Pin No. @ Powerup 2 Bit Description Pin No. @ Powerup Description X (Reserved) 7 X (Reserved) 6 6 8 1 PCICLK_F (Active/Inactive) 6 X (Reserved) 5 16 1 PCICLK5 (Active/Inactive) 5 1 (Reserved) 4 14 1 PCICLK4 (Active/Inactive) 4 1 IOAPIC (Active/Inactive) 3 13 1 PCICLK3 (Active/Inactive) 3 X (Reserved) 2 12 1 PCICLK2 (Active/Inactive) 1 11 1 PCICLK1 (Active/Inactive) 0 9 1 PCICLK0 (Active/Inactive) 45 7 8 2 47 1 REF2 (Active/Inactive) 1 1 1 REF1 (Active/Inactive) 0 2 1 REF0 (Active/Inactive) 9 10 Byte 6: Optional Register for Possible Future Requirements Byte3: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Pin No. @ Powerup Description Bit Pin Number Description 7 26 1 SDRAM7 (Active/Inactive) 7 X (Reserved) 6 27 1 SDRAM6 (Active/Inactive) 6 X (Reserved) 5 29 1 SDRAM5 (Active/Inactive) 5 X (Reserved) 4 30 1 SDRAM4 (Active/Inactive) 4 X (Reserved) 3 32 1 SDRAM3 (Active/Inactive) 3 X (Reserved) 2 33 1 SDRAM2 (Active/Inactive) 2 X (Reserved) 1 35 1 SDRAM1 (Active/Inactive) 1 X (Reserved) 0 36 1 SDRAM0 (Active/Inactive) 0 X (Reserved) 395 11 12 13 14 15 PS8137A 03/15/99 PI6C671F Clock Generator for Pentium Modules 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Byte 7: Frequency Control DC Specifications Absolute Maximum DC Power Supply Bit @ Power up Description 7 X (Reserved) Symbol Supply Voltage Min. 6 X (Reserved) VDDQ3 3.3V Core & I/O -0.5 4. 6 5 X (Reserved) VDD 3.3V Core -0.5 4.6 4 X (Reserved) VDDQ2 2.5/3.3V I/O -0.5 4.6 3 X (Reserved) VDDQ1 2.5/3.3V I/O -0.5 4.6 2 1 FSEL2 1 1 FSEL1 0 1 FSEL0 FSEL2 FSEL1 FSEL0 0 0 (Reserved) 0 0 1 (Reserved) 0 1 0 (Reserved) 0 1 1 33 MHz 1 0 0 50 MHz 1 0 1 55 MHz 1 1 0 60 MHz 1 1 1 From SEL66/60# pin V DC Operating Requirements (VDD, VDDQ3=3.3V ±5%, VDDQ2=2.5V ±5%, TA=0 to 70°C) Symbol Parameter Condition Min. VOH2 2.5V Output High Voltage IOH = -1mA 2.1 VOH3 3.3V Output High Voltage IOH = -1mA 2.4 V O L2 2.5V Output Low Voltage IOL = 1mA 0.4 V O L3 3.3V Output Low Voltage IOL = 1mA 0.4 Frequency 0 Max. Units IDD Dynamic Supply Current IPD Power Down Supply Current Typ. Max. Units V 66 MHz Unloaded Outputs 55 70 mA PWR_DWN# = 0 MODE = Float (high) 14 20 µA Note: Typical values are at room temperature 396 PS8137A 03/15/99 PI6C671F Clock Generator for Pentium Modules 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1 Driver Specifications Symbol Parameter Condition Minimum Typical Maximum Units 2 Type A: CPUCLK1-3 2.5V Buffer Iohmin Pull-up Current Vout = 1.0V -49 Iolmin Vout = 1.2V 48 mA Pull-down Current 3 Type A: CPUCLK1-3 3.3V Buffer Iohmin Pull-up Current Vout = 1.0V -69 Iolmin Vout = 1.6V 63 mA Pull-down Current 4 Type B: IOAPIC 2.5V Buffer Iohmin Pull-up Current Vout = 1.4V -36 Iolmin Vout = 1.0V 36 5 mA Pull-down Current Type B: IOAPIC 3.3V Buffer Iohmin Pull-up Current Vout = 1.0V -58 Iolmin Vout = 1.9V 57 6 mA Pull-down Current 7 Type C: REF1, REF2, 48/24 MHz (3.3V) Buffer Iohmin Pull-up Current Vout = 1.0V -29 Iolmin Vout = 1.95V 29 8 mA Pull-down Current Type D: REF0, SDRAM (3.3V) Buffer Iohmin Pull-up Current Vout = 2.0V -54 Iolmin Vout = 1.0V 54 9 mA Pull-down Current 10 Type E: PCI Clock Buffer Iohmin Pull-up Current Vout = 1.0V 11 -33 mA Iolmin Pull-down Current Vout = 1.95V 30 12 Type F: CPUCLK0 2.5V Buffer Iohmin Pull-up Current Iohmax Vout = 1.0V -62 Vout = 2.5V 13 -19 mA Vout = 1.2V 60 14 Iohmin Pull-down Current Vout = 0.3V 41 15 397 PS8137A 03/15/99 PI6C671F Clock Generator for Pentium Modules 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 AC Timing Symbol Parameter Min. Max. Units 0.4 1.6 ns 250 ps 55 % tRF Host CLK rise/fall time, 0.4V - 2.0V tJITTER Host CLK Jitter Duty Cycle Measured the rising edge CLKs at 1.25V for the 2.5V clocks and at 1.5V for the 3.3V clocks tHSKW Host Bus CLK skew 250 tHSKSD Host to SDRAM 500 tPKPS PCI CLK period stability 500 tPSKW PCI Bus CLK skew 500 tHPOFFSET Host to PCI Clock Offset tSTB CLK Stabilization at power-up 45 1 ps 4 ns 3 ms 48-Pin SSOP Package Data 48 .291 .299 7.39 7.59 .395 .420 10.03 10.67 Gauge Plane .010 0.25 .02 0.51 .04 1.01 1 .015 0.381 x 45˚ .025 0.635 .008 0.20 Nom. .620 .630 15.75 16.00 .110 2.79 Max .008 0.20 .016 0.40 0-8˚ .008 0.20 .0135 0.34 .025 BSC 0.635 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 48-Pin TSSOP Package Data 48 .236 .244 1 6.0 6.2 .488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE .004 0.09 .008 0.20 .007 .010 .0197 BSC 0.50 X.XX X.XX 0.17 0.27 .002 .006 0.05 0.15 0.45 .018 0.75 .030 .319 BSC 8.1 DENOTES DIMENSIONS IN MILLIMETERS Ordering Information P/N Description PI6C671FV 48-pin SSOP Package PI6C671FA 48-pin TSSOP Package Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 398 PS8137A 03/15/99