INTEGRATED CIRCUITS PCK2000M CK97 (66/100MHz) Mobile System Clock Generator Product specification 1998 Sep 29 Philips Semiconductors Product specification CK97 (66/100MHz) Mobile System Clock Generator PIN CONFIGURATION • Reduced pincount version of PCK2000 for mobile applications • Mixed 2.5V and 3.3V operation • Two CPU clocks at 2.5V • Six synchronous PCI clocks at 3.3V, one free–running • One 3.3V reference clock @ 14.318 MHz • Reference 14.31818 MHz Xtal oscillator input • 100 MHz or 66 MHz operation • Power management control input pins • 175 ps CPU clock jitter • 175 ps skew on outputs • Available in 28–pin SSOP package • 1.5 – 4ns CPU–PCI delay • Power down if PWRDWN is held LOW • See PCK2000 for 48-pin version XTAL IN 1 28 VSSREF XTAL OUT 2 27 VDDREF VSSPCI0 3 26 REF PCICLK_F 4 25 VDDCPU PCICLK1 5 24 CPUCLK0 VDDPCI0 6 23 CPUCLK1 PCICLK2 7 22 VSSCPU PCICLK3 8 21 VDDCORE1 VDDPCI1 9 20 VSSCORE1 PCICLK4 10 19 PCISTOP PCICLK5 11 18 CPUSTOP VSSPCI1 12 17 PWRDWN VDDCORE0 13 16 SEL 15 SEL100/66 PCK2000M FEATURES PCK2000M VSSCORE0 14 TOP VIEW SA00448 DESCRIPTION The PCK2000M is a clock synthesizer/driver chip for a Pentium Pro or other similar processors, typically used in mobile applications. The PCK2000M has two CPU clock outputs at 2.5V. There are six PCI clock outputs running at 33 MHz. One of the PCI clock outputs is free–running. The 3.3V reference clock outputs at 14.318 MHz. All clock outputs meet Intel’s drive strength, rise/fall time, jitter, accuracy, and skew requirements. The part possesses dedicated powerdown, CPUSTOP, and PCISTOP input pins for power management control. These inputs are synchronized on–chip and ensure glitch–free output transitions. When the CPUSTOP input is asserted, the CPU clock outputs are driven LOW. When the PCISTOP inputs is asserted, the PCI clock outputs are driven LOW. Finally, when the PWRDWN input pin is asserted, the internal reference oscillator and PLLs are shut down, and all outputs are driven LOW, except the free running PCICLK_F clock output. The PCK2000M is available in a 28–pin SSOP package. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DRAWING NUMBER 28-Pin Plastic SSOP 0°C to +70°C PCK2000M DB PCK2000M DB SOT341-1 Intel and Pentium are registered trademarks of Intel Corporation. 1998 Sep 29 2 853-2128 20101 Philips Semiconductors Product specification CK97 (66/100MHz) Mobile System Clock Generator PCK2000M PIN DESCRIPTION PIN NUMBER SYMBOL 26 REF 14.318 MHz clock output FUNCTION 28 VSSREF GROUND for REF output 27 VDDREF POWER for REF output 1 XTAL_IN 14.318 MHz crystal input 2 XTAL_OUT 14.318 MHz crystal output 3, 12 VSSPCI [0–1] GROUND for PCI outputs 4 PCICLK_F Free-running PCI output 6, 9 VDDPCI [0–1] POWER for PCI outputs 5, 7, 8, 10, 11 PCICLK [1–5] PCI clock outputs. 13, 21 VDDCORE [0–1] Isolated POWER for core 14, 20 VSSCORE [0–1] Isolated GROUND for core 16 SEL 15 SEL100/66 Select pin for enabling 66 MHz or 100MHz or 66 MHz. L = 66 Mhz H = 100MHz 17 PWRDWN Control pin to put device in powerdown state, active low 18 CPUSTOP Control pin to disable CPU clocks, active low 19 PCISTOP Control pin to disable PCI clocks, active low 25 VDDCPU Power for CPU outputs 22 VSSCPU GROUND for CPU outputs 23, 24 CPUCLK [0–1] Logic select pins CPU and Host clock outputs 2.5V NOTE: 1. VDD and VSS names in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on the performance of the device. In reality, the platform will be configured with the VDDCPU pins tied to a 2.5V supply, all remaining VDD pins tied to a common 3.3V supply and all VSS pins being common. BLOCK DIAGRAM XTAL_IN X XTAL_OUT X 14.318 MHZ OSC PWRDWN LOGIC STOP LOGIC PLL1 PWRDWN LOGIC SEL0 X X REFCLK (14.318 MHz) X CPUCLK [0–1] X PCICLK_F (33MHz) LOGIC SEL100/66 X STOP LOGIC X PCICLK [1–5] (33MHz) CPUSTOP X PCISTOP X PWRDWN X SW00275 1998 Sep 29 3 Philips Semiconductors Product specification CK97 (66/100MHz) Mobile System Clock Generator PCK2000M SELECT FUNCTIONS SEL100/66 SEL0 FUNCTION NOTES 0 0 0 TRI-State 1 1 Active 66MHz 1 0 Test mode 1 1 Active 100MHz 1 NOTES: 1. Internal decode logic for all two select inputs implemented. OUTPUTS FUNCTION DESCRIPTION CPU PCI, PCI_F REF Tri-State Hi-Z Hi-Z Hi-Z Test mode TCLK/2 TCLK/6 TCLK FUNCTION TABLE SEL 100/66 CPU/PCI RATIO CPUCLK (0–1) (MHz) CPICLK (1–5) PCICLK_F (MHz) REF (MHz) 0 2 66.66 33.33 14.318 1 3 100 33.33 14.318 CLOCK ENABLE CONFIGURATION PCICLK_F OTHER CLOCKS LOW LOW Stopped OFF OFF LOW 33MHz Running Running Running 33MHz 33MHz Running Running Running 100/66MHz LOW 33MHz Running Running Running 100/66MHz 33MHz 33MHz Running Running Running CPUSTOP PCISTOP PWRDWN CPUCLK PCICLK X X 0 LOW 0 0 1 LOW 0 1 1 LOW 1 0 1 1 1 1 PLL OSCILLATOR POWER MANAGEMENT REQUIREMENTS LATENCY SIGNAL SIGNAL STATE NO. OF RISING EDGES OF FREE RUNNING PCICLK CPUSTOP 0 (DISABLED) 1 1 (ENABLED) 1 PCISTOP 0 (DISABLED) 1 1 (ENABLED) 1 PWRDWN 1 (NORMAL OPERATION) 3ms 0 (POWER DOWN) 2 MAX NOTES: 1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the first valid clock that comes out of the device. 2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device. 1998 Sep 29 4 Philips Semiconductors Product specification CK97 (66/100MHz) Mobile System Clock Generator PCK2000M ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to VSS (VSS = 0V) SYMBOL PARAMETER LIMITS CONDITION MIN MAX UNIT VDD3 DC 3.3V core supply voltage –0.5 +4.6 V VDDQ3 DC 3.3V I/O supply voltage –0.5 +4.6 V VDDQ2 DC 2.5V I/O supply voltage –0.5 +3.6 V IIK DC input diode current VI < 0 –50 mA VI DC input voltage Note 2 –0.5 5.5 V IOK DC output diode current VO > VCC or VO < 0 ±50 mA VO DC output voltage Note 2 –0.5 VCC + 0.5 V VO >= 0 to VCC ±50 mA –65 +150 °C 850 mW IO DC output source or sink current TSTG Storage temperature range PTOT Power dissipation per package plastic medium-shrink (SSOP) For temperature range: –40 to +125°C above +55°C derate linearly with 11.3mW/K NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS UNIT MIN MAX VDD3 DC 3.3V core supply voltage Note 1 3.135 3.465 V VDDQ3 DC 3.3V I/O supply voltage Note 2 3.135 3.465 V VDDQ2 DC 2.5V I/O supply voltage Note 3 2.135 2.625 V VI DC input voltage range 0 VDD3 V VO DC output voltage range 0 VDDQ2 VDDQ3 V Tamb Operating ambient temperature range in free air 0 +70 °C NOTES: 1. VDD3 = VDDCORE1 = VDDCORE2 = 3.3V 2. VDDQ3 = VDDREF = VDDPCI0 = 3.3V 3. VDDQ2 = VDDCPU0 = VDDCPU1 = 2.5V 1998 Sep 29 5 Philips Semiconductors Product specification CK97 (66/100MHz) Mobile System Clock Generator PCK2000M DC CHARACTERISTICS LIMITS TEST CONDITIONS SYMBOL Tamb = 0°C to +70°C PARAMETER VDD (V) OTHER MIN TYP UNIT MAX VIH HIGH level input voltage 3.135 to 3.465 VDDQ2 = 2.5V ±5% 2.0 VDD + 0.3 V VIL LOW level input voltage 3.135 to 3.465 VDDQ3 = 3.3V ±5% VSS – 0.3 0.8 V VOH2 2.5V output HIGH voltage CPUCLK 2.375 to 2.625 IOH = –1mA VDDQ3 = 3.3V ±5% 2.0 – V VOL2 2.5V output LOW voltage CPUCLK 2.375 to 2.625 IOL = 1mA – 0.4 V VOH3 3.3V output HIGH voltage REF 3.135 to 3.465 IOH = –1mA 2.0 – V VOL3 3.3V output LOW voltage REF 3.135 to 3.465 IOL = 1mA – 0.4 V VPOH PCI output HIGH voltage 3.135 to 3.465 IOH = –1mA 2.4 – V VPOL PCI output LOW voltage 3.135 to 3.465 IOL = 1mA – 0.55 V IOH CPUCLK output HIGH current 2.375 VOUT = 1.0V –27 – 2.625 VOUT = 2.375V – –27 IOH PCI output HIGH current 3.135 VOUT = 1.0V –33 – 3.465 VOUT = 3.135V – –33 IOL CPUCLK output LOW current 2.375 VOUT = 1.2V 27 – 2.625 VOUT = 0.3V – 30 IOL PCI output LOW current 3.135 VOUT = 1.95V 30 – 3.465 VOUT = 0.4V – 38 ±II Input leakage current 3.465 – 5 µA ±IOZ 3-State output OFF-State current 3.465 – 10 µA 5 pF Cin Input pin capacitance Cxtal Xtal pin capacitance, as seen by external crystal Cout Output pin capacitance Idd3 Operating O erating supply su ly current Operating O erating supply su ly current Powerdown supply current IO = 0 18 3.465 Powerdown supply current Idd2 VOUT = Vdd or GND mA mA pF 6 pF Outputs loaded1 170 mA 100MHz mode Outputs loaded1 170 mA 500 µA 66MHz mode Output loaded1 72 mA 100MHz mode Output loaded1 100 mA 100 µA All static inputs to VDD or GND NOTE: 1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section. 1998 Sep 29 mA 66MHz mode All static inputs to VDD or GND 2.625 mA 6 Philips Semiconductors Product specification CK97 (66/100MHz) Mobile System Clock Generator PCK2000M AC CHARACTERISTICS VDDREF = VDDPCI (0–1)= 3.3V ± 5%; VDDCPU = 2.5V ± 5%; fcrystal = 14.31818 MHz CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20pF) SYMBOL TEST CONDITIONS PARAMETER THKP (tP) CPUCLK period THKH (tH) CPUCLK HIGH time THKL (tL) CPUCLK LOW time THKP (tP) CPUCLK period THKH (tH) CPUCLK HIGH time 66MHz 100MHz LIMITS Tamb = 0°C to +70°C NOTES MIN MAX 15.5 2 15.0 1, 5 5.2 1, 5 5.0 UNIT ns 2 10.0 1, 5 3.0 10.5 ns THKL (tL) CPUCLK LOW time 1, 5 2.8 THRISE (tR) CPUCLK rise time 9 0.4 1.6 ns THFALL (tF) CPUCLK fall time 9 0.4 1.6 ns TJITTER (tJC) CPUCLK jitter 175 ps DUTY CYCLE (tD) Output Duty Cycle 1 55 % THSKW (tSK) CPU Bus CLK skew 2 45 175 ps THSTB (fST) CPUCLK stabilization from Power-up 7 3 ms PCI CLOCK OUTPUTS, PCI(1–5) AND PCI_F (LUMP CAPACITANCE TEST LOAD = 30pF) SYMBOL TEST CONDITIONS PARAMETER LIMITS Tamb = 0°C to +70°C NOTES MIN 30.0 UNIT MAX TPKP (tP) PCICLK period 3 TPKPS PCICLK period stability 8 TPKH (tH) PCICLK HIGH time 1 12.0 TPKL (tL) PCICLK LOW time 1 12.0 THRISE (tR) PCICLK rise time 10 0.5 2.0 ns THFALL (tF) PCICLK fall time 10 0.5 2.0 ns 500 ps TPSKW (tSK) PCI Bus CLK skew 2 THPOFFSET (tO) CPUCLK to PCICLK Offset 2, 4 TPSTB (fST) PCICLK stabilization from Power-up 7 ns 500 ps ns ns 1.5 4.0 ns 3 ms REF CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF) SYMBOL TEST CONDITIONS PARAMETER NOTES LIMITS Tamb = 0°C to +70°C MIN Frequency generated by Crystal UNIT MAX f Frequency, Actual THRISE (tR) Output rise edge rate 1 4 ns THFALL (tF) Output fall edge rate 1 4 ns DUTY CYCLE (tD) Duty Cycle 45 55 % THSTB (fST) Frequency stabilization from Power-up (cold start) 3 ms 1998 Sep 29 7 14.31818 MHz Philips Semiconductors Product specification CK97 (66/100MHz) Mobile System Clock Generator PCK2000M ALL CLOCK OUTPUTS SYMBOL TEST CONDITIONS PARAMETER NOTES LIMITS Tamb = 0°C to +70°C MIN MAX UNIT TPZL, TPZH Output enable time 1.0 8.0 ns TPLZ, TPHZ Output disable time 1.0 8.0 ns NOTES: 1. See Figure 3 for measure points. 2. Period, jitter, offset, and skew are measured on the rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks. 3. The PCICLK is the CPUCLK divided by two at CPUCLK = 66.6MHz. PCICLK is the CPUCLK divided by three at CPUCLK = 100MHz. 4. The CPUCLK must always lead the PCICLK as shown in Figure 2. 5. THKH is measured @ 2.0V as shown in Figure 4. 6. THKL is measured @ 0.4V as shown in Figure 4. 7. The time is specified from when VDDQ achieves its nominal operating level (typical condition is VDDQ = 3.3V) until the frequency output is stable and operating within specification. 8. Defined as once the clock is at its nominal operating frequency, the adjacent period changes cannot exceed the time specified. 9. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.0V (1mA) JEDEC specification. 10. THRISE and THFALL (REF, PCI) are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V AC WAVEFORMS VM = 1.25V @ VDDQ2 and 1.5V @ VDDQ3 VX = VOL + 0.3V VY = VOH –0.3V VOL and VOH are the typical output voltage drop that occur with the output load. THKP DUTY CYCLE VDDQ2 1.25V THKH VSS CPUCLK 2.5V CLOCKING INTERFACE 2.0 1.25 0.4 VDDQ2 THKL 1.25V TRISE CPUCLK TFALL VSS TPKP TPKH THSKW 3.3V CLOCKING INTERFACE (TTL) SW00240 2.4 1.5 0.4 TPKL Figure 1. CPUCLK to CPUCLK skew TRISE TFALL SW00242 Figure 3. 2.5V/3.3V Clock waveforms VDDQ2 1.25V VSS CPUCLK VDDQ3 1.5V PCICLK VSS THPOFFSET SW00241 Figure 2. CPUCLK to PCICLK offset 1998 Sep 29 8 Philips Semiconductors Product specification CK97 (66/100MHz) Mobile System Clock Generator PCK2000M VI SEL 100, 66, SEL1, SEL0 COMPONENT MEASUREMENT POINTS VM 2.5VOLT MEASURE POINTS GND VOH = 2.0V tPLZ tPZL VOL = 0.4V VDD VDDQ2 VIH = 1.7V 1.25V VIL = 0.7V VSS OUTPUT LOW-to-OFF OFF-to-LOW SYSTEM MEASUREMENT POINTS VM COMPONENT MEASUREMENT POINTS VX VOL 3.3VOLT MEASURE POINTS tPHZ tPZH VOH = 2.4V VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VSS VY VOL = 0.4V VM outputs enabled outputs disabled VSS outputs enabled VDDQ3 VIH = 2.0V 1.5V VIL = 0.7V SYSTEM MEASUREMENT POINTS SW00243 SW00239 Figure 5. Component versus system measure points Figure 4. 3-State enable and disable times. 1998 Sep 29 9 Philips Semiconductors Product specification CK97 (66/100MHz) Mobile System Clock Generator PCK2000M CPUSTOP CPUCLK (INTERNAL) PCICLK (INTERNAL) PCICLK (FREE-RUNNING) CPUSTOP CPUCLK (EXTERNAL) PCISTOP CPUCLK (INTERNAL) PCICLK (INTERNAL) PCICLK (FREE-RUNNING) PCISTOP PCICLK (EXTERNAL) PWRDWN CPUCLK (INTERNAL) PCICLK (INTERNAL) PWRDWN CPUCLK (EXTERNAL) PCICLK (EXTERNAL) Á Á Á Á VCO CRYSTAL Figure 6. Power Management 1998 Sep 29 10 SW00244 Philips Semiconductors Product specification CK97 (66/100MHz) Mobile System Clock Generator SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm 1998 Sep 29 11 PCK2000M SOT341-1 Philips Semiconductors Product specification CK97 (66/100MHz) Mobile System Clock Generator PCK2000M Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 05-96 9397–750-04604