PERICOM PT7A6632

Data Sheet
PT7A6632 32-Channel HDLC Controller
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Features
Applications
• Provides up to 32 full-duplex HDLC/SDLC
• Primary rate interfaces
channels
• Basic-rate D-channel controller
• Compatible with 1.544 Mb/s T1 and 2.048Mb/s
• Multi-channel HDLC interfaces
CEPT PCM-30 carrier format
Introduction
• Provides on-board buffer memory management
• Supports standard hyperchannel configuration and
The PT7A6632 HDLC controller operates at layer 2
fully programmable hyperchannel configuration
(data link protocol level) of the Open Systems Inter-
• Provides on-board CRC-16, automatic flag and
connection (OSI) reference model. It supports HDLC
zero insertion and deletion functions in HDLC
and ISDN implementations.
format
• Provides programmable tri-state outputs to T1/E1
The PT7A6632 processes data transmitting and re-
serial interface and FILL/MASK, thus enabling up
ceiving on a T1 or E1 communication link. It con-
to 8 devices connecting to a TDM bus
nects between the T1/E1 serial bus and an external
• Provides data rate adaptation functions
memory shared with CPU(s), multiplexing /
• Compatible with HDLC, SNA SDLC, X.25, X.75,
demultiplexing up to 32 fully-duplex high-speed data
LAPB, and LAPD protocols
channels.
• Support non-HDLC signaling channels
It provides additional functions that support X.30 and
• Single +5V power supply
X.31 rate adaptation and fully flexible hyperchannels.
• Package: 68-pin PLCC
Figure 1. Application Diagram of PT7A6632
D0-D7
CPU
PT019(05/02)
External
Shared
Memory
A0-A15
HDLC
PT7A6632
1
E1/T1
Trunk
Interface
T1/CEPT
PCM-30
Line
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Contents
Features ....................................................................................................................................................... 1
Applications ................................................................................................................................................ 1
Introduction ................................................................................................................................................. 1
Block Diagram ............................................................................................................................................ 4
Pin Information ........................................................................................................................................... 4
Pin Assignment .................................................................................................................................. 4
Pin Configuration .............................................................................................................................. 5
Pin Description .................................................................................................................................. 6
Functional Description ................................................................................................................................ 9
General Description ........................................................................................................................... 9
Transmit Bit-Level Processor ........................................................................................................... 10
Timing .................................................................................................................................... 10
Data Rate Adaptation ............................................................................................................. 10
Hyperchannel ......................................................................................................................... 13
Tri-State Serial Data Output TSER ........................................................................................ 14
Channel Operation Modes...................................................................................................... 14
Data Transmission Order ........................................................................................................ 14
Receive Bit-Level Processor ............................................................................................................ 15
Timing .................................................................................................................................... 15
Data Rate Adaptation ............................................................................................................. 15
HDLC Frame Validity ............................................................................................................ 15
Hyperchannel ......................................................................................................................... 15
Channel Operation Modes...................................................................................................... 15
Data Reception Order............................................................................................................. 18
Memory Manager ............................................................................................................................ 18
State / Control Machine ................................................................................................................... 19
PT019(05/02)
2
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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External Memory Organization and Definition ......................................................................................... 20
General Structure ............................................................................................................................. 20
Activation Memory .......................................................................................................................... 21
Channel Activation Byte ........................................................................................................ 21
Channel Buffer Pointers ......................................................................................................... 21
Data Processing Memory ................................................................................................................. 24
General ................................................................................................................................... 24
Transmit Data Buffer .............................................................................................................. 24
Transmit Command Buffer ..................................................................................................... 26
Minimum Number of Data Bytes in a Tx Buffer.................................................................... 30
Receive Data Buffer ............................................................................................................... 31
Receive Command Buffer ...................................................................................................... 33
Minimum Buffer Size ............................................................................................................. 37
Device Operation ...................................................................................................................................... 38
Device Initialization ......................................................................................................................... 38
Channel Initialization ....................................................................................................................... 38
Data Transmission and Reception Operation ................................................................................... 39
Channel Period ................................................................................................................................ 41
Memory Address ............................................................................................................................. 42
Memory Address Extension ................................................................................................... 42
Activation Memory Address................................................................................................... 42
Memory Address Restrictions................................................................................................. 43
Interrupt Indication .......................................................................................................................... 43
Detailed Specifications .............................................................................................................................. 48
Absolute Maximum Ratings ............................................................................................................ 48
Recommended Operating Conditions .............................................................................................. 48
DC Electrical, Power Supply and Capacitance Characteristics ........................................................ 49
AC Characteristics ........................................................................................................................... 50
Serial Interface........................................................................................................................ 50
External Memory Interface ..................................................................................................... 54
Channel Activation/Deactivation ............................................................................................ 56
Input Characteristics ............................................................................................................... 57
Output Characteristics ............................................................................................................ 58
Mechanical Specifications ............................................................................................................... 59
Ordering Information ................................................................................................................................ 60
Notes ......................................................................................................................................................... 61
PT019(05/02)
3
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Block Diagram
Figure 2. Block Diagram of PT7A6632
16
RSER
A0-A15
D0-D7
Receive
Bit-Level
Processor
8
READ
WRITE
AS
RSYNC
RRED
Memory
RCLK
Manager
TCLK
DMND
TSER
Transmit
Bit-Level
Processor
ATTN
ATACK
SYSACC
INTR
TMAX
TSEREN
SYSCLK
5
CH0-CH4
State / Control Machine
Rx/Tx
2
RESET UAEN MDFS HCS0-HCS1 T1/CEPT SIS
Pin Information
Pin Assignment
Table 1. Pin Assignment
G r ou p
Sym b ol
F u n ct ion
Memory Interface
D0-D7, A0-A15, READ, WRITE, AS,
DMND
Data, Addresses & Signals with Shared
Memory
Serial Interface
RSER, RSYNC, RRED, TSER, TMAX,
SYSCLK, TCLK, RCLK, TSEREN
Data & Timing with Serial Interface
CPU Interface
ATTN, ATACK, SYSACC, INTR
Signals with CPU
State & Control
SIS, T1/CEPT, HCS0, HCS1, MDFS,
UAEN, RESET, CH0-CH4, Rx/Tx
Device Status & Control Signals
Power
VCC, GND
Power & Ground
PT019(05/02)
4
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Pin Configuration
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
NC
CH0
HCS1
HCS0
T1/CEPT
RESET
SIS
TMAX
NC
TSEREN
RCLK
RSYNC
RRED
RSER
NC
GND
GND
Figure 3. Pin Configuration
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
68-Pin
PLCC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
INTR
AS
ATTN
SYSACC
GND
GND
GND
VCC
WRITE
READ
ATACK
DMND
MDFS
UAEN
A15
A14
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
NC
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
CH1
CH2
CH3
CH4
Rx/Tx
TCLK
SYSCLK
TSER
VCC
GND
GND
D0
D1
D2
D3
D4
D5
Top View
PT019(05/02)
5
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Pin Description
Table 2. Pin Description
P in
Na me
Typ e
Descr ip t ion
1, 9, 43, 60,
63
NC
2
TMAX
I
Tr a n sm it m u lt ifr a m e syn c: pulse input from T1/E1 Trunk Interface, active HIGH.
Getting to high indicates the begining of a multiframe.
3
SIS
I
Ser ia l in t er fa ce select : decides the effective edge of TCLK and RCLK. See Table 25.
SIS = 1, falling edge of TCLK and RCLK effective.
SIS = 0, rising edge effective.
No con n ect ion
4
RESET
I
R eset : input for initializing the PT7A6632, active HIGH. The initialization will be
completed within 90 SYSCLK periods after RESET changes to LOW. The RESET sets
the device in the following state:
- HDLC mode,
- all the FILL/MASK bits are zeros,
- all channels deactivated,
- transmit channels output all ones.
5
T1/CEPT
I
Select T 1 or C E P T mod e: a HIGH sets the device in T1 framing mode, a LOW sets in
CEPT PCM-30 framing mode.
6
7
HCS0
HCS1
I
H yp er ch a n n el select : set standard hyperchannel patterns in T1 or CEPT mode:
- In T1 mode (T1/CEPT = 1),
HCS0 HCS1 = 01, four channels of 384 kb/s (H0),
= 10, single channel of 1.536Mb/s (H11).
- In CEPT PCM-30 mode (T1/CEPT = 0):
HCS0 HCS1 = 01, single channel of 1.92Mb/s, time-slot 0 and 16 are 64kb/s (H12),
= 10, reserved.
- In any of T1 or CEPT PCM-30 mode,
HCS0 HCS1 = 00, all channels are 64kb/s,
= 11, reserved.
8
10
11
12
13
CH0
CH1
CH2
CH3
CH4
O
C h a n n el n u mb er : indicates current active channel’s number (binary). CH0 is the LSB
and CH4 is the MSB.
14
Rx/Tx
O
R eceive/t r a n smit ch a n n el: indicates direction of current active channel. HIGH means
receive and LOW means transmit.
15
TCLK
I
Tr a n smit clock : Square wave input from T1/E1 Trunk Interface. Used for PT7A6632
transmit interface clock. Its phase must be aligned with that of SYSCLK and frequency
is one half of SYSCLK.
PT019(05/02)
6
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Table 2. Pin Description (Continued)
P in
Na me
Typ e
Descr ip t ion
16
SYSCLK
I
Syst em clock : Provides timing reference for all external memory interface. Frequency =
3.088MHz for T1 or 4.096MHz for CEPT PCM-30.
17
TSER
O
Tr a n smit t ed ser ia l d a t a : Serial data output line, tri-state output to T1/E1 interface, carries
transmitter data bit stream.
18, 52
VCC
I
Power su p p ly (+5V)
19, 20, 53,
54, 55, 61,
62
GND
I
G r ou n d
21-28
D0-D7
I/O
M em or y Da t a lin es: Bidirectional data bus between the PT7A6632 and the shared
memory. D0 is the LSB and D7 is the MSB.
29-42, 44-45
A0-A15
O
Memor y Ad d r ess lin es: Output address lines to the external memory. A0 is the LSB and
A15 is the MSB.
I
Up p er Ad d r ess E n a b le: Sets the upper address bus lines (A8-A15) state:
UAEN = 1: PT7A6632 sets A8-A15 in high impedance during Activation Memory access
with SYSACC asserted.
UAEN = 0: PT7A6632 sets A8-A15 LOW when SYSACC asserted.
46
UAEN
47
MDFS
I
Memor y Da t a For ma t Select :
MDF S = 1: the most significant bytes of next buffer start address, buffer size and data
length are at even addresses respectively in the external memory, and their
least significant bytes at odd addresses (68000MPU).
MDF S = 0: inverse with the above, i.e., the most significant bytes of next buffer start
address, buffer size and data length are at odd addresses respectively in the
external memory, and their least significant bytes at even addresses (8080
MPU).
48
DMND
O
Memor y Dema n d : A HIGH informs other devices on the memory bus that the PT7A6632
will access the external memory one TCLK period after DMND assertion (rising edge).
The DMND will be deasserted at completion of the memory access.
49
ATACK
O
At t en t ion Ack n owled ge: Active HIGH. 6632 responds to the ATTN to access Activation
Memory. After completion of the access, 6632 asserts ATACK. ATACK is deasserted in
response to deassertion of ATTN (falling edge).
50
READ
O
Memor y R ea d : Active LOW. Output to the external memory for data reading. When it
is LOW, data from memory is latched to the PT7A6632 on the rising edge of SYSCLK.
51
WRITE
O
Memor y Wr it e: Active LOW. Output to the external memory for data writing.
56
SYSACC
O
Syst em Access: Active HIGH. A HIGH indicates the PT7A6632 is accessing Activation
Memory locations for channel activation byte or channel buffer pointers.
PT019(05/02)
7
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Table 2. Pin Description (Continued)
P in
Na me
Typ e
Descr ip t ion
57
ATTN
I
At t en t ion : Active HIGH. A HIGH requires PT7A6632 to process the Channel Activation
Byte (CAB) at Activation Memory location xx00H in the shared memory. ATTN will be
deasserted in response to assertion of ATACK.
58
AS
O
Memor y Ad d r ess st r ob e: active LOW. Its falling edge will make a valid memory address
be on the memory address lines.
59
INTR
O
I n t er r u p t : active LOW. A LOW indicates that the buffer status byte is under update. Its
pulse duration is equal to one SYSCLK period.
64
RSER
I
R eceived Ser ia l Da t a : Serial data input line, receiving data bit stream from the T1/E1
Interface.
65
RRED
I
R eceive R ed Ala r m: A HIGH indicates the received data is invalid due to loss of
frame alignment or similar reason. If so, PT7A6632 stops processing in all receive
channels until the reception synchronization restored.
66
RSYNC
I
R eceive Syn ch r on iza t ion : active HIGH. Level or pulse input for receive frame
synchronization.
67
RCLK
I
R eceive C lock : Clock for serial data receiving. Input from the T1/E1 interface / clock
recovery circuit. Frequency is 1.544MHz for T1 or 2.048MHz for CEPT PCM-30.
I
T SE R E n a b le: active HIGH, decides TSER line status along with FILL/MASK bit in
descriptor.
When TSEREN = 1, FILL/MASK = 1, send data on TSER,
FILL/MASK = 0, send a 1 on TSER.
When TSEREN = 0, FILL/MASK = 1, Send data on TSER,
FILL/MASK = 0, high impedance on TSER.
68
PT019(05/02)
TSEREN
8
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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deformats them and adapts data rate, then stores the data into
the external memory.
Functional Description
General Description
The channel operation modes are set up in the external memory
by CPU. PT7A6632 reads the commands from the external
memory and process data channel by channel, totally 64 channels (32 for transmission and 32 for receive). Each channel
mode can be set up in external memory independently by CPU.
The PT7A6632 HDLC Controller is applied between an external memory and T1/E1 trunk interface to perform data transmission and reception. See Figure 1. Its signal attributes are
shown in Figure 4.
PT7A6632 consists of 4 functional blocks as shown in Figure
2. There are:
•
Transmit Bit-Level Processor,
•
Receive Bit-Level Processor,
•
Memory Manager, and
•
State/Control Machine.
PT7A6632 reads the data to be transmitted from the external
memory in 8-bit parallel way, formats them and adapts data
rate, then transmits the data to the T1/E1 trunk interface.
PT7A6632 receives serial data from the T1/E1 trunk interface,
Figure 4. PT7A6632 Interface Signals
16
SYSCLK
A0-A15
8
External
Memory
RSER
D0-D7
RSYNC
READ
RRED
WRITE
RCLK
AS
PT7A6632
T1/E1
Trunk
Interface
TCLK
TSER
DMND
TMAX
ATTN
CPU
TSEREN
5
ATACK
CH0-CH4
SYSACC
Rx/Tx
INTR
Channel
Status
Output
2
RESET UAEN MDFS HCS0-HCS1 T1/CEPT SIS
Device Mode
PT019(05/02)
9
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Transmit Bit-Level Processor
Timing
The block diagram of the Transmit Bit-Level Processor is
shown in Figure 5. The external memory stores data to be transmitted and the channel operation modes in a set of linked
buffers (referred as Transmit Data/Command Buffers) in the
external memory. Refer to Figure 23 and 24 in the External
Memory Organization and Definition.
TCLK clocks data bit stream out at its falling edge. TMAX is
multiframe synchronization signal from the T1/E1 trunk interface. SIS decides the TMAX is sampled in rising or falling
edge of TCLK . PT7A6632 processes data channel by channel
for the data transmission under control of channel counter in
the Transmit Interface. See Figure 7-10.
For transmit, the PT7A6632 reads the data from external
memory, formats it in HDLC format (generates flags, abort and
idle code, inserts zero-bit, counts the Frame Check Sequences),
non-HDLC signaling format or non-HDLC data format, adapts
data rate, and sends the processed data to TSER output via the
Transmit Interface.
Data Rate Adaptation
The PT7A6632 can adapt the data rate of sub-64kb/s (n x 8kb/
s, n = 1 - 8) to the standard 64kb/s bearer rate. A FILL/MASK
byte in the transmit command buffer is applied to the data bit
by bit to perform data rate adaptation. An example is shown in
the Figure 6.
Figure 5. Block Diagram of Transmit Bit-Level Processor
To/From
Memory
Manager
Format
&
Rate Adapt
Transmit
Interface
TSER
TSEREN
(32 Channels)
TMAX
TCLK
State/Control Signals
Figure 6. 32kb/s Subrate Operation - Single Transmit Channel
MSB
LSB
A B C D E F G H
Data Bytes to Be Transmitted
J K L M N O P Q
FILL/MASK Pattern
1 0 1 1 1 0 0 0
FILL/MASK
0 = A fill bit of 1 or high Z (see TSEREN)
1 = Insert bit of data byte starting with LSB
T1/CEPT PCM-30 Serial Output
TS m in Frame n
TS m in Frame n+1
TS m in Frame n+2
1 1 1 H G F 1 E 1 1 1 D C B 1 A 1 1 1 Q P O ...
Transmitted Data
LSB
PT019(05/02)
10
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Figure 7. Transmit Frame Synchronization Timing - T1 Mode, SIS = 1
Channel 24
Bit 7
Channel 1
Bit 8
Bit F
Bit 1
Bit 2
Bit 3
Data
Data
Data
Data
Data
Data
Bit 4
Bit 5
Bit 6
Bit 7
TCLK
TMAX
FILL/MASK*
TSEREN (Low)
TSER
High Z
High Z
Data
High Z
Data
TSEREN (High)
1
TSER
Data
1
Time Fill
1
1
Data
Time Fill
* The F-bit time is processed as if the FILL/MASK = 0. However, this actual FILL/MASK does not apply to the F-bit.
Figure 8. Transmit Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 1
Time-slot 31
Bit 7
Time-slot 0
Bit 8
Bit 1
Bit 2
Bit 3
Bit 4
Data
Data
Bit 5
Bit 6
Bit 7
Bit 8
TCLK
TMAX
FILL/MASK
TSEREN (Low)
TSER
High Z
TSEREN (High)
TSER
PT019(05/02)
High Z
Data
Data
1
Data
Time Fill
1
1
Data
Data
11
Data
High Z
Data
1
Time Fill
Data
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Figure 9. Transmit Frame Synchronization Timing - T1 Mode, SIS = 0
Channel 24
Bit 7
Channel 1
Bit 8
Bit F
Bit 1
Bit 2
Bit 3
Bit 4
Data
Data
Data
Bit 5
Bit 6
Bit 7
Bit 8
TCLK
TMAX
FILL/MASK*
TSEREN (Low)
High Z
TSER
High Z
Data
TSEREN (High)
1
Data
TSER
1
1
Time Fill
Data
Data
Data
High Z
Data
1
Time Fill
Data
* The F-bit time is processed as if the FILL/MASK = 0. However, this actual FILL/MASK does not apply to the F-bit.
Figure 10. Transmit Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 0
Time-slot 31
Bit 7
Time-slot 0
Bit 8
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Data
Data
Bit 6
Bit 7
Bit 8
Bit 1
TCLK
TMAX
FILL/MASK
TSEREN (Low)
TSER
High Z
TSEREN (High)
TSER
PT019(05/02)
High Z
Data
Data
1
Data
Time Fill
1
1
Data
12
Data
Data
High Z
Data
1
Time Fill
Data
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Hyperchannel
Three standard ISDN hyperchannel options (two for T1, one
for CEPT PCM-30) are available by setting HCS0 and HCS1
as well as T1/CEPT pins. See Table 3 and Figure 11.
All channels can also be randomly grouped into flexible
hyperchannel (with HCS0 HCS1 = 00). A hyperchannel can
contains any number of 64kb/s channels. Details is illustrated
in “External Memory Organization and Definition” and Table
10.
Table 3. Hyperchannel Selection
T 1/C E P T
H C S1
H C S0
C h a n n el Select ion
x
0
0
All channels are 64kb/s. (Flexible hyperchannel can be programmed)
1
1
0
Four channels of 384kb/s (H0). Valid for T1 only.
1
0
1
Single channel of 1.538Mb/s (H11). Valid for T1 only.
0
1
0
Single channel of 1.92Mb/s (H12). Time-slots 0 and 16 are 64kb/s. Valid for CEPT
only.
x
1
1
Reserved.
0
0
1
Reserved.
Figure 11. Standard Hyperchannel Provisory
CEPT PCM-30 Mode
Framing Time-Slot (8 bits)
Signaling Channel (8 bits)
64kb/s
F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TS 0,
CH 00000
H12
TS 17, CH 10001
TS 16, CH 10000
Data Channel (8 Bits) (Typ.)
TS 1, CH 00001
F 1
TS 31, CH 11111
1920 kb/s
S 1
TS 1, CH 00001
T1 Mode
64kb/s
F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CH 00001
CH 00010
CH 11000
384 kb/s
H0 F 1
2
3
4
1536 kb/s
H11
F 1
Note:
Grouping of 64kb/s channels into standard hyperchannels is fixed as shown. Time-slot assignments can be
changed (when HCS1 HCS0 = 00) to create flexible hyperchannels by programming command buffers.
PT019(05/02)
13
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Tri-State Serial Data Output TSER
•
The TSER can be set to different state by setting TSEREN pin
and FILL/MASK byte in the transmit command buffer. See
Table 4.
The non-HDLC signaling requires no special consideration in
transmit data processing.
Table 4. Output Selection on TSER
T SE R E N F I L L /MASK
O u t p u t on T SE R
1
0
Send a 1
0
0
High-impedance output
1
1
Send data
0
1
Send data
Non-HDLC Signaling Mode
In non-HDLC signaling mode, CF/P bit of STATUS byte of
allocated data buffer should be reset to ensure uninterrupted
data transmit. The PT7A6632 assumes that no more than 2
linked data buffers are allocated to the signaling channel by
the CPU. Details are shown in Section “External Memory Organization and Definition” and Tables 8 and 14.
•
Loop Mode
Channel Operation Modes
When a transmit channel is specified in Loop Mode, the
PT7A6632 will send the data of this channel into an intermediate buffer in PT7A6632 in channel period while sends the
data to TSER output. The data then will be sent back to the
external memory via a receive channel in Loop Mode. Each
time only one transmit and one receive channel can be specified in Loop Mode. The transmit loop channel number and
receive loop channel number are not necessarily identical. The
Loop Mode does not support hyperchannel.
The transmit channels can be set in the following operation
modes by CPU in transmit command buffer. See MODE byte in
the transmit command buffer for details (Figure 24).
If only a transmit loop channel is defined without a receive
loop channel defined, the loop operation can not be performed.
Reset the device will delete all Loop Mode.
•
•
When TSEREN = 0, and FILL/MASK bit = 0, the TSER output
line is in high impedance. This feature allows to connect up to
eight PT7A6632 devices together to realize subrate TDM transmission.
HDLC Mode
In HDLC mode, the Transmit Processor generates flags, abort
and idle code, inserts zero-bit, count the Frame Check Sequences (FCS) for the data.
In HDLC mode, it is programmable to attach a number of flags
to the end of HDLC frame as time-fill sequence. The number of
flags is specified in the transmit data buffer.
The PT7A6632 counts the intentionally inserted zeroes based
on HDLC format. These intentionally inserted zeroes may be
counted as intraframe time-fill bits. In this case, the programmed
flag number will be adjusted according to the counting result.
Reset the device will make all channels in HDLC mode.
•
Non-HDLC Data Mode
In non-HDLC data mode, the data from memory directly transmit on TSER.
In non-HDLC data channel mode (DMI mode 0 or 1), CF/P bit
of STATUS byte of allocated data buffer should be reset to
ensure uninterrupted data transmit.
PT019(05/02)
Logical Inversion
If a transmit channel is set in inversion mode, data including
flag, ABORT and FCS bits will be inverted bit by bit when
transmit processing. Device reset sets all channel in inversion
mode.
Data Transmission Order
The PT7A6632 transmits data bytes in the same time sequence
as they are arranged in ascending addresses in the external
buffers. For a certain channel, the data at byte address m is
transmitted first, the data at address m+1 is transmitted next,
and so on while the data bytes are in the same buffer. After the
data in a data buffer is exhausted, the PT7A6632 starts to transmit the next byte from the next buffer whose address is specified in the current buffer. The transition to the next buffer is
transparent to the CPU while the flow of actual data is maintained. This natural sequence of data flow is maintained for
flexible hyperchannels, as well.
The PT7A6632 transmits the LSB (D0) of a data byte first;
then the next LSB second; and the MSB (D7) last. The only
exception is that the MSB of the HDLC FCS (CRC-CCITT) is
transmitted first; the LSB transmitted last.
14
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Receive Bit-Level Processor
Receive Mornitor
The block diagram of the Receive Bit-Level Processor is shown
in Figure 12. The receive bit-level processor accept serial data
from the T1/E1 trunk interface, perform HDLC deformat (processes flags, abort, deletes zeroes, checks FCS, filters time-fill
bits), or other non-HDLC functions and assemble the processed
bit, including HDLC header, into bytes and sends them into
the external memory. The CPU sets up the channel operation
in a set of linked buffers (referred as receive command/data
buffer) in the external memory. Refer to Figure 26 and 27 in
the Section “External Memory Organization and Definition”.
The PT7A6632 monitors the Receive Red Alarm (RRED) input. Once the PT7A6632 detects RRED high, it will stop data
processing in all receive channels and reports by writing the
Status byte. The synchronization will be restored by TMAX
and RSYNC signals.
The PT7A6632 performs data validity check (checks CRC) for
the received data. Once the PT7A6632 finds any errors in the
CRC, the receive interface will stop data processing in current
channel until detects a new HDLC flag byte. The situation is
reported to the external memory. Details are shown in Table 11
for STATUS byte, ABRT, FCER and SHER bits in Section “External Memory Organization and Definition”.
Timing
Generally, the starting of a data frame received from the T1/E1
trunk interface is not correlated with that of a transmit frame.
As PT7A6632 uses same 8-bit memory bus for data writing
and reading, an elastic buffer is adopted to coordinate the data
access on the bus.
Hyperchannel
Three standard ISDN hyperchannel options (two for T1, one
for CEPT PCM-30) are available by setting HCS0 and HCS1
as well as T1/CEPT pins. See Table 3 and Figure 11.
The received data stream is clocked into the elastic buffer by
the RCLK and then clocked out to the Deformat and Rate
Adapt circuit by the TCLK. In this way, the data flow on the
memory bus is simple and coordinated. The data is sampled
and processed in rising edge (SIS = 0) or falling edge (SIS = 1)
of the RCLK. See Figure 14-17.
The channels can also be randomly grouped into flexible
hyperchannel (with HCS0 HCS1 = 00). A hyperchannel can
contains any number of 32 64kb/s channels. Details is illustrated in Section “External Memory Organization and Definition” and Table 10.
The RSYNC is used for receive frame synchronization.
Channel Operation Modes
Data Rate Adaptation
See receive command buffer in Section “External Memory Organization and Definition” for details (Figure 27).
Reverse process of data rate adaptation of transmission. Illustrated in Figure 13.
Figure 12. Block Diagram of Receive Bit-Level Processor
To/From
Memory
Manager
Deformat
&
Fill/Mask
Filter
(32 Channels)
Receive
Interface
RRED
Elastic
Buffer
RSER
RCLK
RSYNC
TCLK
State/Control Signal
PT019(05/02)
15
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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•
•
HDLC Mode
In non-HDLC signaling mode, PT7A6632 detects the
multiframe alignment sequence. If the alignment sequence is
valid, the received data will be sent to the external memory; if
not, the data will not be sent to external memory until a valid
alignment sequence is detected. The loss of the multiframe
alignment will be reported to external memory. Any channel(s)
can be specified to receive bit-oriented signaling. This feature
is very useful in central office switching applications.
In HDLC mode, the Receive Processor detects flags, abort,
delete zero-bit, check the Frame Check Sequences (FCS), and
filters the time-fill bits by applying FILL/MASK byte to the
received data.
Reset the device will make all channels in HDLC mode.
•
Non-HDLC Signaling Mode
Non-HDLC Data Mode
In this mode, received data are directly written into external
memory without deformating.
Figure 13. 32kb/s Subrate Operation - Single Receive Channel
T1/CEPT PCM-30 Serial Input
TS m in Frame n+1
TS m in Frame n
Received Data
A 1 B C D 1 1 1 E 1 F G H 1 1 1
1 0 1 1 1 0 0 0
FILL/MASK
A B C D E F G H
MSB
Assembled Data Byte
LSB
Figure 14. Receive Frame Synchronization Timing - T1 Mode, SIS = 1
Proving Period 2
(one full
multiframe)
~
~
~
~
Proving Period 3
(one full
multiframe)
~
~
~
~
Proving Period 1
(≤ one full
multiframe)
~
~
~
~
RSYNC
~
~
~
~
RRED
(One full
multiframe)
From this point, fully
multiframe synchronized
until RRED goes high
RCLK
RSER
Bit 7
Bit 8
Bit F
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
RRED
RSYNC
Channel 24, last
frame of a
multiframe
PT019(05/02)
Channel 1, first frame of the next
multiframe
16
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Figure 15. Receive Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 1
Proving Period 2
(one full
multiframe)
~
~
~
~
Proving Period 3
(one full
multiframe)
~
~
~
~
Proving Period 1
(≤ one full
multiframe)
~
~
~
~
RSYNC
~
~
~
~
RRED
(One full
multiframe)
From this point, fully
multiframe synchronized
until RRED goes high
RCLK
RSER
Bit 7
Bit 8
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
RRED
RSYNC
Time-slot 31, last
frame of a
multiframe
Time-slot 0, first frame of the next
multiframe
~
~
Proving Period 1
(≤ one full
multiframe)
Proving Period 2
(one full
multiframe)
~
~
~
~
Proving Period 3
(one full
multiframe)
~
~
~
~
RSYNC
~
~
~
~
RRED
~
~
Figure 16. Receive Frame Synchronization Timing - T1 Mode, SIS = 0
(One full
multiframe)
From this point, fully
multiframe synchronized
until RRED goes high
RCLK
RSER
Bit 7
Bit 8
Bit F
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
RRED
RSYNC
Channel 24, last
frame of a
multiframe
PT019(05/02)
Channel 1, first frame of the next
multiframe
17
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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~
~
Proving Period 1
(≤ one full
multiframe)
Proving Period 2
(one full
multiframe)
~
~
~
~
Proving Period 3
(one full
multiframe)
~
~
~
~
RSYNC
~
~
~
~
RRED
~
~
Figure 17. Receive Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 0
(One full
multiframe)
From this point, fully
multiframe synchronized
until RRED goes high
RCLK
RSER Bit 6
Bit 7
Bit 8
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
RRED
RSYNC
Time-slot 31, last
frame of a
multiframe
•
Time-slot 0, first frame of the next
multiframe
Loop Mode
When a receive channel is specified in Loop Mode, data to be
sent to the external memory is not from the external T1/E1
trunk interface, instead, it is fetched internally from an intermediate buffer in the PT7A6632, in which the data was from a
loop mode transmit channel. Thus the data from the external
memory is feedback to external memory. Each time only one
transmit and one receive channel can be specified in Loop
Mode to guarantee normal operation. The transmit loop channel No. and receive loop channel No. are not necessarily identical. The Loop Mode does not support hyperchannel.
Reset the device will delete all Loop Mode.
•
Logical Inversion
Data Reception Order
The PT7A6632 writes received data bytes in the external
memory in the same order in which they are received in time.
For a certain channel, the first received byte is written at byte
address m, the second received at byte address m+1, and so on
as long as the buffer is not completely filled or an end-of-frame
is not reached. After the end of the frame or the end of the
buffer (whichever occurs first) is detected, the PT7A6632 writes
the next received data byte at the first allocated address of the
next available buffer.
The PT7A6632 writes the first received data bit of an octet at
the LSB (D0) position of the external buffer byte, the second
received data bit at the next to LSB position, and so on. The
last (8th) received data bit of an octet is written at the MSB
(D7) position of the data byte.
If a receive channel is set in inversion mode, the received data
will be inverted bit by bit when being processed, including
flag, ABORT and FCS bits.
Reset the device will make all channel in inversion mode.
PT019(05/02)
18
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Memory Manager
State/Control Machine
The Memory Manager controls data flow between Transmit
Processor/Receive Processor and the external memory as shown
in Figure 18. CPU assigns the external memory into several
parts for activation information (Activation Memory) and data
processing information (Data Processing Memory) as shown
in Figure 20 in Section “External Memory Organization and
Definition”.
The State/Control Machine processes the device mode and
status. MDFS sets the memory location pattern, i.e., the even
addresses in external memory are for higher bytes (MDFS = 1)
or for lower bytes (MDFS = 0) of the Next Buffer Starting Address, Buffer Size and Data Length respectively.
Figure 19
To Rx and Tx Processors
& Memory Manager
The Data Processing Memory is allocated to each transmit and
receive channel for data, command and status storage. The
CPU allocated enough memory in the buffers for the real-time
operation of transmit and receive with no data underrun or
overrun. The external memory is managed with minimal intervention from the CPU.
5
State / Control Machine
CH0CH4
Rx/Tx
2
The CPU sends out an ATTN signal to command PT7A6632 to
access the Activation Memory that contains channel number
and channel starting address. The SYSACC signal is asserted
by PT7A6632 during accessing the Activation Memory. After
the access, the ATACK will be asserted.
RESET UAEN MDFS HCS0-HCS1 T1/CEPT SIS
UAEN sets the Upper address lines (A8 - A15) in high impedance (UAEN = 1) or in Low state (UAEN = 0) when accessing
Activation Memory. When the upper address lines in high impedance, the CPU can drive them to any state during accessing
activation memory.
The Data Processing Memory contains such information as
next buffer address, operation mode, buffer size, data length,
buffer status and HDLC frame completion status. They are set
up by CPU. PT7A6632 accesses the buffers and processes data
and update the status in the buffers after processing. DMND is
asserted by the PT7A6632 to inform other devices using the
memory bus that PT7A6632 will access the external memory
one TCLK period after rising edge of the DMND. INTR asserted when PT7A6632 updates the status byte in buffers.
HCS0, HCS1 and T1/CEPT select T1 or CEPT PCM-30 mode
and hyperchannel (Table 3). SIS selects trigger edge of RCLK
and TCLK. TSEREN sets TSER output line state, i.e., sending
data, sending “1” or in high impedance (Table 4).
CH0 to CH4 and Rx/Tx are status outputs indicating the current active channel number and direction. CH0 is LSB, CH4 is
MSB.
The memory manager responds to CPU-initiated changes in the
operational modes of a channel or relocation of the allocated
buffers without affecting the operation of the other channels.
The main clock for PT7A6632 is generated by the State/Control Machine from SYSCLK.
The timing for the memory access is generated from SYSCLK.
Figure 18. Diagram of Memory Manager with External Memory and CPU
A0-A15
D0-D7
CPU
External
Memory
READ
WRITE
Memory
Manager
From Rx Bit-Level Processor
/ To Tx Bit-Level Processors
AS
SYSCLK
DMND
3
PT019(05/02)
PT7A6632
ATTN
ATACK, SYSACC, INTR
19
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
and Channel Buffer Pointers, providing PT7A6632 such information as channel activation/deactivation, channel direction (transmit or receive) and channel starting addresses. CPU
allocates the Channel Starting Pointer for each receive and
transmit channel.
External Memory Organization and
Definition
General Structure
The external memory is divided by the CPU into two functional blocks for channel activation and data processing, referred as Activation Memory and Data Processing Memory.
The Activation Memory contains Channel Activation Byte
The Data Processing Memory contains data/command buffers
storing descriptors, user’s data received or to be transmitted,
channel operation mode and status. CPU allocates a set of
linked data/command buffers for each receive and transmit
channel.
Details are shown in Figures 20-22.
Figure 20. External Memory Map - Top Level
External Memory
(Contents)
(Address)
0
1
2
~
~
j
~
~
Channel Activation Byte
~
~
j + 128
to
j + 255
~
~
128 Bytes of System Memory
for Channel Buffer Pointers
~
~
p
p+1
to
p+n 1
~
~
n-Byte Data Buffer
For Tx Channel #m
~
~
x
x+1
to
x+n-1
PT019(05/02)
Activation
Memory
~
~
Data
Processing
Memory
n-Byte Data Buffer
For Rx Channel #k
20
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Activation Memory
Channel Buffer Pointers
The Activation Memory map is shown in the Figure 21.
Channel Buffer Pointers provide PT7A6632 the channel starting address (16-bit) for each channel, 64 channels totally, guiding to a link of buffers containing data and command. The
relative location of the upper and lower bytes of the 16-bit
start address word is determined by the MDFS input (see Figure 17). The upper address lines (A8-A15) are placed in the
high-impedance state or LOW by the PT7A6632 during the
Activation Memory accesses.
Channel Activation Byte
The Channel Activation Byte are illustrated in the following
table 5. The PT7A6632 reads this byte so that gets the channel
number, the channel state (active or inactive) and the channel
direction (transmit or receive). The PT7A6632 asserts SYSACC
when it accesses the Activation Memory.
Table 5. Channel Activation Byte
Bit 7
Bit 6
Bit 5
Act ive b it
Bit 4
R x/T x b it
1
0
The channel
activated
The channel
deactivated
Bit 3
Bit 2
Bit 1
Bit 0
C h a n n el Nu mb er 0 ~ 31 (Bin a r y)
1
0
Receive
Transmit
0 0 0 0 0 - channel 0,
0 0 0 0 1 - channel 1,
0 0 0 1 0 - channel 2,
etc.
Unused
Figure 21a. Activation Memory Map Locations (MDFS = HIGH)
a. MDFS = HIGH (68000 Based)
(Address)
(HEX)
XX00
XX01
XX7F
XX80
XX81
XX82
XX83
~
~
7
Active
6
x
5
Rx/Tx
(Contents)
4
3
2
1
Channel Number
Byte Addresses xx01 Through
xx7F Are Not Used by PT7A6632
Transmit Channels 2 to 30 Start Addresses
XXBE
XXBF
Transmit Channel 31 Start Address (High-Order Byte)
Transmit Channel 31 Start Address (Low-Order Byte)
XXC0
XXC1
Receive Channel 0 Start Address (High-Order Byte)
Receive Channel 0 Start Address (Low-Order Byte)
~
~
PT019(05/02)
Channel Activation Byte
~
~
Transmit Channel 0 Start Address (High-Order Byte)
Transmit Channel 0 Start Address (Low-Order Byte)
Transmit Channel 1 Start Address (High-Order Byte)
Transmit Channel 1 Start Address (Low-Order Byte)
~
~
XXFE
XXFF
0
Receive Channels 1 to 30 Start Address
~
~
Channel Buffer Pointers
~
~
Receive Channel 31 Start Address (High-Order Byte)
Receive Channel 31 Start Address (Low-Order Byte)
21
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure 21b. Activation Memory Map Locations (MDFS = LOW)
b. MDFS = LOW (iAPX 86 Based)
(Address)
(HEX)
XX00
XX01
XX7F
XX80
XX81
XX82
XX83
~
~
6
x
5
Rx/Tx
2
1
Channel Number
Byte Addresses xx01 Through
xx7F Are Not Used by PT7A6632
Transmit Channels 2 to 30 Start Addresses
XXBE
Transmit Channel 31 Start Address (Low-Order Byte)
XXBF
XXC0
XXC1
Transmit Channel 31 Start Address (High-Order Byte)
Receive Channel 0 Start Address (Low-Order Byte)
Receive Channel 0 Start Address (High-Order Byte)
~
~
XXFE
XXFF
0
Channel Activation Byte
~
~
Transmit Channel 0 Start Address (Low-Order Byte)
Transmit Channel 0 Start Address (High-Order Byte)
Transmit Channel 1 Start Address (Low-Order Byte)
Transmit Channel 1 Start Address (High-Order Byte)
~
~
PT019(05/02)
7
Active
(Contents)
4
3
Receive Channels 1 to 30 Start Address
~
~
Channel Buffer Pointers
~
~
Receive Channel 31 Start Address (Low-Order Byte)
Receive Channel 31 Start Address (High-Order Byte)
22
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure 22. Organization and Linking of Data or Command Buffers
Address
i
7
Buffer 1
0
Next Buffer Start Address
Buffer Size
Data length
Status byte
8 Bytes of Buffer Descriptor*
i+7
i+7+1
~
~
~
~
k Bytes of User s Data
or
2 Bytes of Channel Mode
& Rate Definition Data
Data or
Command
i+7+k
7
Buffer 2
0
m
Next Buffer Start Address
Buffer Size
Data length
Status byte
8 Bytes of Buffer Descriptor*
m+7
m+7+1
~
~
~
~
n Bytes of User s Data
or
2 Bytes of Channel Mode
& Rate Definition Data
Data or
Command
m+7+n
7
Buffer N
0
p
Next Buffer Start Address
Buffer Size
Data length
Status byte
8 Bytes of Buffer Descriptor*
p+7
p+7+1
~
~
p+7+r
r Bytes of User s Data
or
2 Bytes of Channel Mode
& Rate Definition Data
~
~
Data or
Command
* Formats are different for Data buffer and Command buffer, and differs with MDFS
PT019(05/02)
23
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
There are 4 kinds of buffers, Transmit Data Buffer and Transmit Command Buffer for transmit channels, and Receive Data
Buffer and Receive Command Buffer for receive channels.
Data Processing Memory
General
The Data Processing Memory refers to Data or Command buffers which are linked each other. The PT7A6632 accesses the
Data Processing Memory for transmit/receive data and operation commands. Each buffer has following configuration (see
Figure 22):
• 8-Byte Descriptors
• Data bytes to be transmitted or received or Command
Transmit Data Buffer
The Transmit Data Buffer contains 8 bytes of descriptors and j
bytes of user’s data as shown in Figure 23. The MDFS pin
decides the most significant byte and least significant byte
locations (in even and odd addresses).
Figure 23. Transmit Data Buffer
i
msb
(Contents)
0
i+1
Not used
i+3
i+4
i+5
Descripto rs
i+2
FC
FO
lsb
Next Buffer
Address
lsb
Buffer
Size (k)
msb
Not used msb
UNDR IVBA
i+7
Not used
i+2
i+3
i+4
i+5
-
(0)
lsb
FC
FO
UNDR IVBA
Not used msb
Not used
(i+7)+2
Second Date Byte
(i+7)+2
Second Date Byte
Data
First Date Byte
~
~
(i+7)+j
Last Date Byte
~
~
(i+7)+k
~
~
(i+7)+k
a. MDFS = 1
Descriptors
The first 8 bytes in the transmit Data Buffer is Descriptors that
specifies Next Buffer Address, Buffer Size, Data Length and
Status respectively. See Table 6 for the definition.
~
~
Flag Count (Optional)
~
~
Last Location in Buffer
Status
Last Date Byte
(i+7)+j+1
Flag Count (Optional)
(0)
Not Used by PT7A6632
(i+7)+1
(i+7)+j+1
-
Data
Length (j)
CF/P CMND MPTY
First Date Byte
~
~
Buffer
Size (k)
msb
(i+7)+1
(i+7)+j
~
~
Last Location in Buffer
b. MDFS = 0
data buffer) or Buffer Size (for partial data buffer). The buffer
may contains last byte of a frame (CF/P = 1) or partial data of a
frame (CF/P = 0) in HDLC mode. The CF/P should be reset for
other modes.
•
•
lsb
Not used
i+7
Status
Next Buffer
Address
msb
i+6
CF/P CMND MPTY
~
~
•
lsb
i+1
Not Used by PT7A6632
i+6
0
i
Data
Length (j)
lsb
(Contents)
7
(Address)
Data
7
Descriptor s
(Address)
Flag Count Byte (Optional)
Data Bytes
Following the Descriptors are the data to be transmitted. The
number of bytes are specified by Data Length (for complete
PT019(05/02)
Specifies the additional flags to be added after “CRC + one
Flag” of a frame. It will be read only when Flag Control bit in
the MS byte of Data Length is set (FC = 1).
24
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Table 6. Descriptors in Transmit Data Buffer
Na me
Descr ip t ion
Next Bu ffer
Ad d r ess
16-bit address word, pointing to next buffer for 6632 to access
Bu ffer Size
12-bit, specifies byte number of memory locations allocated by the CPU for current buffer. The 6632 reads
the Buffer Size only when the Status (CF/P = 0) shows that the data buffer contains partial data. The 6632
will convert the Buffer Size to the actual number of data bytes in this buffer.
FC
FC
F la g C on t r ol: 1-bit, indicates if any additional flags (except the minimum one flag followed CRC for
HDLC format) to be appendixed after the (CRC+1 FLAG) of the HDLC data. If FC is reset by the CPU,
it means no additional flag to be added. If set by the CPU, it means there will be additional flag(s) to be
added to the data. The number of the additional flag(s) is specified in the optional FLAG COUNT byte in
the Tx Data Buffer.
FO
FO
F la g O ffset C ou n t : 1-bit, meaningful only when FC = 1. If FO is set by the CPU, the Tx channel counts
the total number of intentionally inserted zeros based on HDLC protocol, then divides the counted results
by 8.The quotient (called "Flag Offset") represents the number of non-data byte inserted in the data. The
6632 subtracts the Flag Offset from the FLAG COUNT, which was set without knowledge of the inserted
zeros. The resultant is the actual number of additional flags to be added to the data.
Da t a L en gt h
12-bit, specifies the actual number of data bytes to be transmitted in the Tx Data Buffer. The 6632 reads
the Data Length only if the Status shows that the buffer contains the last byte of a frame (CF/P = 1).
MP T Y
E mp t y: 1-bit, if set by the CPU, it means the buffer is empty, i.e., data is not ready for transmission. The
6632 will keep polling this bit until it is reset. The CPU resets this bit when the data is ready. 6632 sets
the bit to 1 once it completes data transmission in the buffer, and the CPU can reuses the empty locations.
C MND
C omma n d : 1-bit, when set by the CPU, it means the buffer is a Command Buffer. If reset by the CPU, it
is a Data Buffer.
C F /P
C omp let e F r a me/Pa r t ia l Da t a Bu ffer : 1-bit, set by the CPU to show that the data buffer contains the last
byte of an HDLC framed data. Actual number of data bytes is specified by the Data Length (Max. Data
Length: 4095).
If it is reset by the CPU, it means the buffer contains partial data of a frame, and the rest data is in succeeding
buffer(s). The 6632 automatically turns to the next successding buffer. Actual number of data bytes is
specified by the Buffer Size (Max. Buffer Size: 4095).
For non-HDLC data, the bit should be 0 for continuously data transmission, otherwise data transmission
will be interrupted.
I VBA
I nva lid Bu ffer Ad d r ess: 1-bit, the 6632 sets the bit if it finds an invalid Next Buffer Address, i.e., such as
address of 16 zeros or in form of FFFx. In this case, the Tx channel will be deactivated and all-one bytes
be transmitted until the channel is re-activated by the CPU.
UNDR
Un d er r u n : 1-bit, the 6632 sets the bit if the current Tx channel runs out of data, e.g., when the 6632 finds
an invalid buffer address, an empty buffer, or a command buffer following a partial data buffer. If so, the
6632 will send out an ABORT code followed by Flags until the condition is cleared (if in HDLC mode),
or the 6632 will send out all-ones bytes repeatedly until the CPU sets up a valid non-empty data buffer (if
in non-HDLC mode).
PT019(05/02)
25
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Transmit Command Buffer
The Transmit Command Buffer contains 8 bytes of descriptors and 2 bytes of Channel Mode & Rate Definition Data (and maybe
the Hyperchannel Configuring Bytes) as shown in Figure 24. The MDFS pin decides the MS byte and LS byte locations (in even
and odd addresses).
Figure 24. Transmit Command Buffer
msb
0
lsb
i+3
i+4
i+5
Descriptor s
i+1
i+2
Next Buffer
Address
i+7
(i+7)+1
0
0
i+3
Not used
i+4
0
- CMND MPTY Status
(i+7)+3
A
x
~
~
(i+7)+j
Mode
(i+7)+1
FILL/MASK
(i+7)+2
Channel Number
~
~
E
A
x
Channel Number
Next Buffer
Address
Not used
msb
lsb Data Length (j)
Not used
x
IVBA
-
CF/P CMND MPTY
(1)
Not used
0
0
0
E
A
x
0
INV LOOP SIG HDLC
Mode
FILL/MASK
Channel Number
~
~
(i+7)+j
Status
Not used
(i+7)+3
a. MDFS = 1
PT019(05/02)
0
Not used
i+7
(1)
INV LOOP SIG HDLC
(i+7)+2
E
i+5
(Contents)
lsb
i+6
CF/P
Not used
0
msb
Not used
Not Used
IVBA
i
i+1
i+2
lsb Data Length (j)
x
7
Not used
msb
i+6
(Address)
~
~
E
A
x
Channel Number
Hyperchannel
Configuring
i
(Contents)
Descriptor s
7
Hyperchannel
Configuring
(Address)
b. MDFS = 0
26
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
•
Descriptors
The first 8 bytes in the Transmit Command Buffer are Descriptors that specify Next Buffer Address, Data Length and Status
respectively. See Table 7 for the definition.
Table 7. Descriptors in Transmit Command Buffer
Na me
Descr ip t ion
Next Bu ffer
Ad d r ess
16-bit address word, pointing to next buffer for 6632 to access
Da t a L en gt h
8-bit, decides the non-flexible-hyperchannel process or flexible hyperchannel process.
Data Length = 0, 1 or 2, only non-hyperchannel process,
Data Length > 2, there is hyperchannel process.
MP T Y
E mp t y: 1-bit, the CPU sets it to show that the buffer is empty, i.e., command data is not ready. In this case
the 6632 will keep polling this bit until it is reset.The CPU resets this bit when the command data is ready.
6632 sets the bit to inform the CPU completion of command processing in the buffer.
C MND
C omma n d : 1-bit, set by the CPU to indicate the buffer is a Command Buffer.
C F /P
C om p let e C om m a n d Bu ffer /P a r t ia l C om m a n d Bu ffer : 1-bit, set by the CPU to indicate that the
command buffer is a Complete Command Buffer. During the Complete Command Buffer processing, the
6632 will transmit an HDLC ABORT if it is in HDLC mode.
The CPU resets the CF/P bit to indicate a Partial Command Buffer (CF/P=0, CMND=1). In this case the
6632 will send HDLC flag or non-HDLC all-ones byte(s), then continue to process next buffer.
I VBA
I nva lid Bu ffer Ad d r ess: 1-bit, the 6632 sets the bit if it finds an invalid Next Buffer Address, such as
address of 16 zeros or in form of FFFx. In this case, the Tx channel will be deactivated and all-one bits be
transmitted until the channel is re-activated by the CPU.
PT019(05/02)
27
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
•
MODE Byte (Channel Mode)
The MODE byte is set up by the CPU to specify channel modes of HDLC, non-HDLC signaling, non-HDLC data, loop, nonloop, inversion or non-inversion.
The details are shown in Table 8.
Table 8. MODE Byte in Transmit Command Buffer
MO DE
Na me
Bits 7 - 4
Bit 3
Bit 2
Descr ip t ion
Not used
1
Invertion
0
Non-invertion
1
Loop channel
0
Non-loop channel
I NV
LOOP
Non -H DL C d a t a ch a n n el mod e: used in modes 0 and 1 of DMI application. CF/P should be reset
00 to get uninterrupted data transmission, otherwise the 6632 will transmit all-one byte repeatedly
following the last byte in the buffer. The channel time fill and the idle codes are the same.
Bit 1, Bit 0
SI G , H DL C
H DL C d a t a ch a n n el m od e: The channel is an HDLC channel or an LAPD message-oriented
01 channel. Information field is in integral bytes, 16-bit CRC-CCITT polynomial is used to calculate
FCS, and ABORT sequence satisfies SDLC and HDLC requirements.
Non -H DL C sign a lin g ch a n n el m od e: The channel carries bit-oriented signaling data. 6632
10 assumes that no more than 2 linked data buffers are allocated to the signaling channel by the CPU.
The last data buffer (even if it is the only buffer) is assumed to be a recirculating buffer.
11 Reserved
PT019(05/02)
28
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
•
FILL/MASK Byte (Rate Definition)
The FILL/MASK byte is used as a masking pattern on the
HDLC-formatted (including FLAG, header, data, CRC, and
ABORT code) or non-HDLC-formatted data in order to adapt
subrates that are multiples of 8kb/s to the 64kb/s rate. The 8-
bit sequence is applied to data on a bit by bit basis to insert 1
(FILL/MASK bit = 0) for time fill, or insert data bit (FILL/
MASK = 1). See an example in Figure 6 in Section “Transmit
Bit-Level Processor” and Table 9.
For bit-oriented signaling mode, the FILL/MASK should be
set as 1111 1111. If not, the PT7A6632 will not override any
other FILL/MASK pattern.
Table 9. Examples of FILL/MASK Options
O p t ion
Nu mb er
Da t a
Rat e
Bit
7
6
5
4
3
2
1
(MSB)
0
R ema r k s
(L SB)
0*
0 kb/s
0
0
0
0
0
0
0
0
No data will be sent. Eight 1s for time fill will
be sent if TSEREN=1.
1
8 kb/s
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
A r b i t r a r y - u s e r d e fi n e d ; a 1 i n a ny o n e b i t
position, but only one 1.
2
16 kb/s
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
0
0
0
0
Us e r d e fi n e d p a t t e r n ; a 1 i n a ny t wo b i t
positions, but only two 1s.
3
24 kb/s
0
0
0
1
0
0
0
1
0
0
1
1
1
0
1
0
A total of three 1s anywhere as defined by user.
4
32 kb/s
0
1
1
0
1
0
0
1
1
0
1
0
1
0
1
1
0
0
1
0
1
1
0
0
A total of four 1s anywhere as defined by user.
5
40 kb/s
0
0
0
1
1
1
1
1
A total of five 1s anywhere as defined by user.
6
48 kb/s
0
0
1
1
1
1
1
1
A total of six 1s anywhere as defined by user.
0
1
1
1
1
1
1
1
Standard rate in digital data service, restricted
version of 64 kb/s.
1
1
1
1
1
1
1
0
A total of seven 1s anywhere as defined by user.
1
1
1
1
1
1
1
1
7
8
56 kb/s
64 kb/s
* A special purpose mode in which the transmitter operates as if it is at 64 kb/s, including when it is fetching data from
the external memory, even though no data is transmitted.
PT019(05/02)
29
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
•
Flexible Hyperchannel Configuring Byte (Optional)
The byte follows the FILL/MASK byte if any. It is used to
configure flexible hyperchannel. Bits 0 - 4 specify number of
a channel to be grouped into or removed from a hyperchannel.
Bits 6 and 7 is for hyperchannel enable and add/delete respectively. See Table 10 for details.
Table 10
Bit 7 (E )
Bit 6 (A)
Descr ip t ion
0
x
Hyperchannel assignment remains
unchanged.
1
0
Delete channel number in bits 0-4
from hyperchannel.
1
1
Add channel number in bits 0-4 to
hyperchannel.
Data Length is used to specify flexible hyperchannel. When
Data Length = 0, 1 or 2, only normal channel process. When
Data Length > 2, there is hyperchannel process.
•
The channel map may be updated in one cycle of channel
counting. In flexible hyperchannel mode, the HCS0 and HCS1
should be set as “0 0”, otherwise the standard hyperchannel
will override the flexible hyperchannel.
•
Partial Command Buffer
If the CPU can not make next buffer ready before the PT7A6632
completes data transmission of a channel, the CPU will reset
the CF/P bit to indicate that it is a Partial Command Buffer
(CF/P=0, CMND=1). In this case the PT7A6632 will read Next
Buffer Address and send a HDLC flag(s) or a non-HDLC octet
all-ones to fill the gap, then the PT7A6632 turns to a new
buffer chain as if it complete a normal buffer process by setting
the MPTY and CF/P bits.
The PT7A6632 sends out flags or all-ones until it is informed
to resume data transmission by the CPU again. One Partial
Command Buffer sends one flag or one all-ones byte, a chain
of Partial Command Buffer sends multiple flags or ones. The
Partial Command Buffer processing will not change the MODE
and FILL/MASK.
If a Partial Command Buffer is processed after a partial data
buffer, the HDLC ABORT or non-HDLC all-ones will be sent.
Flexible Hyperchannel
The Flexible Hyperchannel mode allows the PT7A6632 to
group any number of 32 64kb/s channels into a hyperchannel.
The Data Length (>2) is read to decide the number of additional channels to be added to a hyperchannel. If a previously
activated channel is assigned to a flexible hyperchannel, it
will suspend the original buffer process, and the process will
be restored once the channel is released from the hyperchannel.
It may take one frame time. A channel can be assigned to one
hyperchannel only.
Minimum Number of Data Bytes in a Tx Buffer
For Transmit Data Buffers and Transmit Command Buffers,
minimum number of data bytes is required for buffer maintenance and buffer transition. The minimum numbers depend on
the current buffer type and next buffer type. Refer to Figure 25.
Figure 25. Minimum Data Bytes for Transmit Buffer
Current Buffer
Current Buffer
Partial Data Buffer
(000)*
Complete Data Buffer
(001)*
Next
Buffer
Next
Buffer
Complete Data
Buffer (001)*
3 Bytes
Current Buffer
Partial Data
Buffer (000)*
6 Bytes
Next
Buffer
Partial Data
Buffer (000)*
5 Bytes
Complete Data
Buffer (001)*
2 Bytes
Current Buffer
Next Buffer
Command Buffer
(10x)*
Complete Data
Buffer (001)*
2 Bytes
Partial Data
Buffer (000)*
5 Bytes
Any Buffer
(xxx)*
Command
Buffer (10x)*
2 Bytes
Min. Data Bytes
* Status Bits: CMND, MPTY, CF/P
PT019(05/02)
30
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Receive Data Buffer
•
The Receive Data Buffer contains 8 bytes of descriptors and j
bytes of user’s data as shown in Figure 26. The MDFS pin
decides the MS byte and LS byte locations (in even and odd
addresses).
Following the Descriptors are received data. The number of
data bytes are indicated by Data Length which is written by
the PT7A6632 after it receives the last byte of an HDLC frame
or the HDLC ABORT code, upon the loss of multiframe alignment error from a non-HDLC signaling channel, or when Receiver Bit-Level Processor detects receive synchronization
error caused by RSYN, elastic buffer error or RRED. When it is
a partial data buffer, the number of data bytes is indicated by
the Buffer Size.
•
Descriptors
The first 8 bytes in the Receive Data Buffer are Descriptors
that specify Next Buffer Address, Buffer Size, Data Length and
Status respectively. See Table 11 for the definition.
Data Bytes
Figure 26. Receive Data Buffer
msb
i+1
Not used
i+3
i+4
i+5
Descriptor s
i+2
Not used
lsb
Next Buffer
Address
lsb
Buffer
Size (k)
msb
msb
i+6
Not Used by PT7A6632
i+7
OVER IVBA ABRT FCER SHER CF/P CMND MPTY
-
(0)
lsb
i+1
i+2
i+3
i+4
i+5
Status
lsb
Data
(i+7)+2
(i+7)+j
-
First Date Byte
Second Date Byte
Last Location in Buffer
(i+7)+k
a. MDFS = 1
Data
Length (j)
(0)
Status
~
~
Last Date Byte
~
~
~
~
Buffer
Size (k)
lsb
~
~
Last Date Byte
PT019(05/02)
msb
i+7
First Date Byte
(i+7)+k
Not used
Not Used by PT7A6632
Second Date Byte
~
~
msb
OVER IVBA ABRT FCER SHER CF/P CMND MPTY
(i+7)+2
(i+7)+j
Not used
i+6
(i+7)+1
~
~
Next Buffer
Address
msb
(i+7)+1
~
~
0
i
Data
Length (j)
lsb
(Contents)
7
(Address)
Data
i
0
Descriptor s
(Contents)
7
(Address)
~
~
Last Location in Buffer
b. MDFS = 0
31
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Table 11. Descriptors in Receive Data Buffer
Na me
Descr ip t ion
Next Bu ffer
Ad d r ess
16-bit address word, pointing to next buffer for 6632 to access
Bu ffer Size
12-bit, specifies byte number of memory locations allocated by the CPU for current buffer. The 6632 reads
the Buffer Size when writes data into the buffer.
Da t a L en gt h
12-bit, the actual number of data bytes received by 6632, written by the 6632 after it receives the last byte
of an HDLC frame or the HDLC ABORT code, or upon the loss of multiframe alignment error from a
non-HDLC signaling channel. DATA LENGTH is not written if the end of the allocated buffer is reached
before the last byte is received (i.e., if data frame length is greater than buffer size). In such a case, the
actual data length is equal to the given buffer size. Also, data length may not be written if the ATTN input
is asserted, resulting in the deactivation or reactivation of an active channel.
DATA LENGTH will not exceed the programmed buffer size.
MP T Y
E mp t y: 1-bit, if set by the CPU, it means the buffer is empty, i.e., the buffer is ready for storing received
data. The PT7A6632 resets this bit when the buffer is not empty. The PT7A6632 will keep polling this bit
until it is set. The 6632 resets the bit whenever it updates the status.
C MND
C omma n d : 1-bit, when set by the CPU, it means the buffer is a Command Buffer. If reset by the CPU, it
is a Data Buffer.
C F /P
C omp let e F r a me/Pa r t ia l Da t a Bu ffer : 1-bit, set by the 6632 to show that the data buffer contains the last
byte of an HDLC framed data or that synchronization is wrong. It will also be set by the 6632 if the HDLC
data or non-HDLC data receiving is aborted by re-synchro condition of ABORT, RRED, RSYNC or TMAX.
The 6632 resets this bit when the last byte of an HDLC frame is not in this buffer and 6632 will store more
data to the succeeding buffer. This bit will always be reset for non-HDLC mode or signaling mode.
ABRT
FCER
SH E R
Ab or t , F r a m e C h eck E r r or, Sh or t H DL C F r a m e E r r or : These 3 bits are used to report abnormal
conditions detected by 6632.
ABRT F C E R SH E R = 0 0 0: no errors detected,
0 0 1: short or non-integer HDLC frame error,
0 1 0: CRC error,
0 1 1: CRC error & non-integer error,
1 0 0: HDLC ABORT code received,
1 0 1: non-HDLC multiframe alignment lost,
1 1 0: elastic buffer error & RSYNC error,
1 1 1: RRED alarm.
I VBA
I nva lid Bu ffer Ad d r ess: 1-bit, the 6632 sets the bit if it finds an invalid Next Buffer Address, such as
address of 16 zeros or in form of FFFx. In this case, the Rx channel will be in idle state and not receive
more data until the channel is re-activated by the CPU.
OVE R
O ver r u n : 1-bit, the 6632 sets this bit when the next empty data buffer is not available for received data
before a frame is completed in HDLC data receiving, or when the next empty data buffer is not available
for non-HDLC data receiving.
No overrun reported for signaling channel. New data will be written in place of earlier received signaling
data.
PT019(05/02)
32
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Receive Command Buffer
The Receive Command Buffer contains 8 bytes of descriptors and 2 bytes of Channel Mode & Rate Definition Data (and maybe
Hyperchannel Configuring Bytes) as shown in Figure 27. The MDFS pin decides the MS byte and LS byte locations (in even
and odd addresses).
Figure 27. Receive Command Buffer
msb
0
lsb
i+2
i+3
i+4
i+5
Descriptor s
i+1
Not used
i+2
Not used
i+3
Not used
i+4
msb
(i+7)+1
Not Used
Not used
x
IVBA
0
0
0
0
CMND MPTY
(1)
INV LOOP SIG HDLC
E
A
x
~
~
(i+7)+j
E
A
x
Mode
(i+7)+1
FILL/MASK
(i+7)+2
Not used
msb
Channel Number
lsb Data Length (j)
Not used
x
IVBA
Not used
CMND MPTY
0
0
0
E
A
x
0
INV LOOP SIG HDLC
Mode
FILL/MASK
Channel Number
~
~
(i+7)+j
Status
(1)
Not used
(i+7)+3
a. MDFS = 1
PT019(05/02)
Not used
i+7
~
~
Next Buffer
Address
msb
Status
Channel Number
0
lsb
i+6
(i+7)+2
(i+7)+3
i+5
lsb Data Length (j)
i+6
i+7
i
i+1
Next Buffer
Address
(Contents)
7
(Address)
~
~
E
A
x
Channel Number
Hyperchannel
Configuring
i
(Contents)
Descriptor s
7
Hyperchannel
Configuring
(Address)
b. MDFS = 0
33
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
•
Descriptors
The first 8 bytes in the Receive Command Buffer is Descriptors that specifies Next Buffer Address, Data Length and Status
respectively. See Table 12 for the definition.
Table 12. Descriptors in Receive Command Buffer
Na me
Descr ip t ion
Next Bu ffer
Ad d r ess
16-bit address word pointing to next buffer for 6632 to access
Da t a L en gt h
8-bit, decides the non-flexible-hyperchannel process or flexible hyperchannel process.
Data Length = 0, 1 or 2, only normal channel process,
Data Length > 2, there is hyperchannel process.
In flexible hyperchannel mode, the Data Length is read to decide how many additional channels to be added
to/remove from the hyperchannel, and the bytes contain the additional channel numbers are read to
add/remove the corresponding channels.
MP T Y
E mp t y: 1-b it , the CPU sets it to show that the buffer is empty, i.e., command data is not ready. In this case
the 6632 will keep polling this bit until it is reset.The CPU resets this bit when the command data is ready.
6632 sets the bit to inform the CPU that it completes command processing in the buffer.
C MND
C omma n d : 1-bit, set by the CPU to indicate the buffer is a Command Buffer.
I VBA
PT019(05/02)
I nva lid Bu ffer Ad d r ess: 1-bit, the 6632 sets the bit if it finds an invalid Next Buffer Address, such as
address of 16 zeros or in form of FFFx. In this case, the Rx channel will be deactivated until the channel
is re-activated by the CPU.
34
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
•
MODE Byte (Channel Mode)
The Channel Mode Byte is set up by the CPU to specify channel modes of HDLC, non-HDLC signaling, non-HDLC data, loop,
non-loop, inversion or non-inversion.
The details are shown in Table 13.
Table 13. MODE Byte in Receive Command Buffer
MO DE
Na me
Bits 7 - 4
Bit 3
Bit 2
Descr ip t ion
Not used
1
Invertion
0
Non-invertion
1
Loop channel
0
Non-loop channel
I NV
LOOP
Non -H DL C d a t a ch a n n el mod e: used in modes 0 and 1 of DMI application. The 6632 check the
availability of the allocated buffer and writes received data to the buffer. The 6632 updates the filled
00
buffer status and asserts INTR, then moves to the next data buffer. The data receiving and writing
will continue until it is interrupted by an ATTN signal or no more buffer available.
Bit 1, Bit 0
SI G ,
H DL C
H DL C d a t a ch a n n el m od e: The channel is an HDLC channel or an LAPD message-oriented
channel. The 6632 deformats the HDLC data -- 16-bit CRC-CCITT polynomial is used to calculate
01
FCS, and ABORT, Flags and inserted zeros are recognized, no special processing for the header
(address and control fields).
Non -H DL C sign a lin g ch a n n el mod e: used in DMI or G.732 application to receive the bit-oriented
10 signaling data without HDLC format. The received data are stored into data buffers in the way
shown in Table 14. The 6632 detects the multiframe alignment and reports if any error is found.
11 Reserved
PT019(05/02)
35
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Table 14. Receive Buffer Data Arrangement for Non-HDLC Bit-Oriented Signaling Channel
(Address)
7
(Contents)
i
Next Buffer Address = i or j
i+1
i+2
Remaining Descriptors
i+7
(i+7)+1
0
X
1
X
X
X
B1
A1
A13
X
1
X
X
X
B2
A2
A14
(i+7)+3
X
1
X
X
X
B3
A3
A15
(i+7)+11
X
1
X
X
X
B11
A11
A23
(i+7)+12
X
1
X
X
X
B12
A12
A1
○
○
○
○
(i+7)+2
(i+7)+13
X
1
X
X
X
B13
A13
A1
(i+7)+14
X
1
X
X
X
B14
A14
A2
X
1
X
X
X
B15
A15
A3
X
1
X
X
X
B16
A16
A4
(i+7)+17
X
1
X
X
X
B17
A17
A5
(i+7)+23
X
1
X
X
X
B23
A23
A11
(i+7)+24
1
0
Ys
0
1
1
1
A12
○
○
○
○
(i+7)+15
(i+7)+16
a. T1 Mode
(Address)
7
(Contents)
i
0
Next Buffer Address = i or j
i+1
i+2
Remaining Descriptors
i+7
(i+7)+1
D17
C17
B17
A17
D1
C1
B1
A1
D18
C18
B18
A18
D2
C2
B2
A2
(i+7)+3
D19
C19
B19
A19
D3
C3
B3
A3
D27
C27
B27
A27
D11
C11
B11
A11
○
○
○
○
(i+7)+2
(i+7)+11
(i+7)+12
D28
C28
B28
A28
D12
C12
B12
A12
(i+7)+13
D29
C29
B29
A29
D13
C13
B13
A13
(i+7)+14
C30
C30
B30
A30
D14
C14
B14
A14
(i+7)+15
D31
C31
B31
A31
D15
C15
B15
A15
(i+7)+16
1
1
Ys
1
0
0
0
0
b. CEPT PCM-30 Mode
PT019(05/02)
36
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
•
FILL/MASK Byte (Rate Definition)
The PT7A6632 FILL/MASK byte is used as a masking pattern
on the HDLC-formatted (including FLAG, header, data, CRC,
and ABORT code) or non-HDLC-formatted data in order to
adapt subrates that are multiples of 8kb/s to the 64kb/s rate.
The 8-bit sequence is applied to data on a bit by bit basis to
remove time-fill (FILL/MASK bit = 0) bits. See an example in
Figure 13 in Section “Receive Bit-Level Processor” and Table
9.
Data Length is used to specify flexible hyperchannel. When
Data Length = 0, 1 or 2, only non-hyperchannel process. When
Data Length > 2, there is hyperchannel process, while the Data
Length indicates how many additional channels to be added
to the hyperchannel. See Section “Flexible Hyperchannel” in
Transmit Command Buffer.
Minimum Buffer Size
The size of receive data buffer must ensure normal buffer maintenance and buffer transition without losing data.
For bit-oriented signaling mode, the FILL/MASK should be
set as 1111 1111, otherwise the PT7A6632 will not override
any other FILL/MASK pattern.
•
Table 15
R eceive Da t a Bu ffer
R eceive C omma n d
Bu ffer
8 Bytes (Descriptors)
+ 6 Bytes (Data)
8 Bytes (Descriptors)
+ 2 Bytes (Command)
Flexible Hyperchannel Configuring Byte (Optional)
Min .
Bu ffer
Size
The byte follows the FILL/MASK byte if any. It is used to
configure flexible hyperchannel. Bits 0 - 4 specify number of
a channel to be grouped into or removed from a hyperchannel.
Bits 6 and 7 is for hyperchannel enable and add/delete respectively. See Table 10 for details.
PT019(05/02)
37
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Before asserting the ATTN, the CPU first allocates memory in
the external memory for a Command Buffer containing 8 bytes
of descriptors including Next Buffer Starting Address, Data
Length, Status, and 2 bytes of Mode and Fill/Mask. And a
chain of linked data buffers are set up by the CPU following
the command buffer, containing Next Buffer Start Address,
Buffer Size, Data Length, Status and Data bytes. Then the CPU
set up the Activation Memory containing channel No. to be
activated and channel direction, and Channel Starting Address (pointers) in the external memory. Then the CPU sends
out the ATTN signal.
Device Operation
Device Initialization
The device is initialized by RESET signal. Upon reset, all the
channels are set in the following states:
- the operation mode is HDLC, inversion, non-loop,
- FILL/MASK byte: 0000 0000,
- all channels are inactive,
- Flexible hyperchannels are disabled,
- no data transferred from the external memory or written to the
external memory.
The PT7A6632 receives the ATTN, starting to access the Activation Memory (asserting SYSACC) for the Channel Number
and the channel start address, which will be stored internally
in the PT7A6632. PT7A6632 asserts the ATACK after completion the access, CPU negates the ATTN in response to the
ATACK, and PT7A6632 negates the ATACK in response to
negation of ATTN. The channel initialization is completed.
The process is illustrated in Figure 28.
The PT7A6632 monitors the TMAX, RSYNC and RRED signals and correspondingly reset the Transmit channel counter
and the Receive channel counter to ascertain the framing synchronization.
Channel Initialization
The channels are initialized for preparing data transmission
and reception by CPU asserting the ATTN signal.
This process can be repeated for each channel to be initialized. The PT7A6632 must make three activation memory accesses to complete the channel ATTN processing. The worst
case of time delay from ATTN assertion to ATACK assertion is
three T1/CEPT PCM-30 channel periods. The earliest is 1.5
channel period.
Figure 28. Channel Initialization
ATTN
CPU
"
#
PT7A6632
ATACK
External Memory
Channel Activation
Byte for Channel #m
%
!
Channel #m Start
Address
$
! CPU prepares data buffer and writes to activation byte for a channel.
" CPU asserts ATTN.
% PT7A6632 responds to ATTN, reads channel number, Rx/Tx, Active/Inactive in
channel activation byte.
$ PT7A6632 find out the corresponding channel start address and read the start address
of the first buffer allocated for the channel.
# PT7A6632 informs task completion by asserting ATACK.
PT019(05/02)
38
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Data Transmission and Reception Operation
processes channel by channel in this way. See figure 29 for
example.
In transmission, the PT7A6632 reads the first command buffer
according to the channel start address, judges status of buffer,
fetches the MODE and FILL/MASK information for the channel, then it reads the Next Buffer Start Address in the current
buffer. It goes to the next buffer to get Data Length/Buffer
Size, and data bytes to send the data out in according to mode
specified and update the status if necessary. The PT7A6632
In receiving, the PT7A6632 reads the command buffer of a
channel to locates the CPU-allocated buffers for received data
storage, and stores the processed data into the data buffer and
write the Data Length. It updates the Status of the completed
buffer if necessary. See figure 30 for example.
Figure 29. Typical Linked Buffer Transmit Sequence
Activation
Memory
1: ATTN goes high.
2: PT7A6632 reads activation byte (xx00).
xx00
xx80
xx81
xx82
xx83
xxBE
xxBF
Tx CH0
Tx CH1
3: PT7A6632 reads the first buffer s starting address (command
or data), then sets ATACK, & starts processing that buffer.
4: PT7A6632 resets ATACK after ATTN goes low.
Tx CH31
5: PT7A6632 continues processing command or data buffers as
controlled by the status of each.
Next BF Addr.
Command
Modes
FILL/MASK
Command Buffer
Next BF Addr.
Buffer Size
MPTY=0
CF/P=0
Data Buffer #3
Next BF Addr.
Data Length
MPTY=0
CF/P=1
Data Buffer #1
Next BF Addr.
Data Length
MPTY=0
CF/P=1
Data Buffer #2
Next BF Addr.
Buffer Size
MPTY=0
CF/P=0
Next BF Addr.
Data Length
MPTY=0
CF/P=1
Data Buffer #4
Data Buffer #5
Data Processing Memory
PT019(05/02)
39
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure 30. Typical Linked Buffer Receive Activity
Activation
Memory
1: ATTN goes high.
2: PT7A6632 accesses Activation Memory (xx00).
xx00
xxC0
xxC1
xxC2
xxC3
xxFE
xxFF
Rx CH0
Rx CH1
Rx CH31
3: PT7A6632 reads the first buffer s starting address (command
or data), then sets ATACK, & starts processing that buffer.
4: PT7A6632 resets ATACK after ATTN goes low.
5: PT7A6632 continues processing command or data buffers as
controlled by the status of each.
Next BF Addr.
Command
Modes
FILL/MASK
Command Buffer
Next BF Addr.
Size
Length
MPTY=1
Data Buffer #1
Next BF Addr.
Size
Length
MPTY=1
Data Buffer #2
Data Processing Memory
PT019(05/02)
40
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Channel Period for Memory Access
access external memory for data byte for once, or twice if the
descriptor reading is necessary, even more, three times if an
ATTN signal asserted by the CPU.
The PT7A6632 accesses the external memory for buffer management and data processing.
At the start of each half-channel period, the PT7A6632 first
outputs the channel number CH0 - CH4, and the channel direction Rx/Tx of the current channel. After around half TCLK
period, the PT7A6632 asserts DMND to inform the external
memory that it will access it after 1 TCLK period from the
rising edge of DMND. Then the PT7A6632 asserts the AS strobe,
whose falling edge will make the address valid on the address
bus. The PT7A6632 sends out READ or WRITE strobe to read
data from the memory or write data into the memory during
low of the READ or WRITE. After finish memory access (1, 2
or 3 times access as applicable) and sets the DMND low to
inform end of memory access of this half-channel period. During the process, if the ATTN is asserted and the PT7A6632
accesses the Activation Memory, it will assert SYSACC and
negate it after Activation Memory access completed.
Normally, the T1/CEPT PCM-30 data flow requires that a byte
of data should be supplied for transmission and a byte of data
be taken from the receiving source within a single channel
period. So the PT7A6632 divides a channel period into 2
halves, the first half is Tx memory access period and the second is Rx memory access period, 4 TCLK periods for each. In
the first half of channel period, the PT7A6632 reads command
information, descriptors information and transmission data
from the external memory for Tx channels, and in second half
of channel period, it reads command information, descriptors
information from external memory and write the received data
to the memory for Rx channels.
Typically, the PT7A6632 fetches a data byte from the memory
during Tx channel period m for transmission of the data byte
over channel m in the next appropriate Tx channel m, and the
PT7A6632 takes a data byte from the receiving circuit of channel j and will store the data into the external memory in the
next appropriate Rx channel period j. Then the PT7A6632
moves to process the next Tx channel (m+1) and Rx channel
(j+1). See Figure 31.
Address setup time, address hold time, data setup time and
data hold time are specified such that a wide variety of off-theshelf RAM devices may be used. The READ output from the
PT7A6632 may be used as an Output Enable (OE) input to the
RAM devices. Since the PT7A6632 uses its SYSCLK input to
generate various strobes for memory access, the access time
requirements are automatically scaled depending on the T1/
CEPT PCM-30 application.
In each Tx or Rx memory access period, the PT7A6632 can
Figure 31. Channel Period
One Channel Period for Memory Access
Tx Memory Access
Rx Memory Access
8 TCLK Periods
One Channel Period
for Memory Access
Channel
Period
Channel No.
Served
PT019(05/02)
for Tx for Rx for Tx for Rx
m
j
41
m+1
j+1
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Memory Address
Activation Memory Address
Memory Address Extension
The Activation Memory has 256 byte locations as shown in
Figure 33. The addresses can be decided by the CPU by setting
UAEN and SYSACC output of the PT7A6632. When UAEN =
0, the address output lines A8-A15 of the PT7A6632 is set low,
so the address of the Activation Memory is in 00xx(H). When
UAEN = 1, PT7A6632 sets its outputs of A8-A15 in high impedance and the CPU can drive the addresses A8-A15.
The output of CH0 - CH4 and Rx/Tx of the PT7A6632 can be
used as upper address bits to extend the 16-bit addresses to 22bit addresses. See an example in Figure 32. Or these six bits
can be mapped by an external lookup table to another set of n
bits (where n is specified by the CPU). Since the channel number and Rx/Tx are output by the PT7A6632 well in advance of
the 16-bit address, address translation time is not a concern.
Figure 32. Address Extension
External
Memory
PT7A6632
16
A15-A0
A15-A0
5
A20-A16
CH0 - CH4
1
A21
Rx/Tx
Figure 33. Activation Memory Address
Activation
Memory
xx00
xx80
xx81
xx82
xx83
xxBE
xxBF
xxC0
xxC1
xxC2
xxC3
xxFE
xxFF
Activat Byte
Not used
Tx CH0
Tx CH1
(Addresses xx80,
xx81 and xxB2
through xxBF are not
used in T1 modes.)
Tx CH31
Rx CH0
Rx CH1
(Addresses xxC0,
xxC1 and xxF2
through xxFF are not
used in T1 mode.)
Rx CH31
Upper address lines xx (A8-A15):
When UAEN = 0, xx = 00.
When UAEN = 1, A8 A15 output of PT7A6632 is set in
high impedance, xx are decided by the CPU.
PT019(05/02)
42
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Last byte address in a buffer = buffer start address + 7 (decimal)
of descriptor bytes + 12-bit data length or buffer size <= 65,535.
Memory Address Restrictions
Activation Memory Address -- The PT7A6632 judges the
channel start address for its invalidity immediately after it reads
the Activation Memory for the address in response to the ATTN
assertion. If the 16-bit address is found invalid, the channel
will be deactivated. The channel start address is thought invalid by the PT7A6632 when it is all zero or in form of FFFx.
If the last byte address exceeds the restriction, the PT7A6632
will access memory locations not intended for the channel. All
the external memory addresses should be within one 64k byte
bank.
Interrupt Indication
Data/Command Buffer Address -- The PT7A6632 checks next
buffer address in each buffer. If found a next buffer address is
invalid, the PT7A6632 will set the channel inactive and set
the IVBA bit of the current buffer. The channel can be reactivated only when CPU asserts the ATTN signal.
The 16-bit next buffer address is thought invalid by the
PT7A6632 if it is all zero or in form of FFFx, namely, the
address is valid when it is within 0001 to FFEF.
The PT7A6632 locates a descriptor byte or a data byte by
adding offset to a next buffer address read from last buffer. The
maximum address in a buffer is the address of the last byte. As
for 16-bit address lines, the addresses are restricted in the range
of 216 - 1 (65,535), the last byte address in a buffer should meet
the following condition:
At the rising edge of INTR, channel No. and status contents
can be shifted into the external FIFO. The INTR is asserted by
the PT7A6632 when PT7A6632 updates the status of a buffer.
After update, the PT7A6632 negates the INTR and at its rising
edge the channel No. and status are guaranteed to be valid on
the bus so that external FIFO can take the information, and the
actual address of the status byte is also be placed on the bus.
The PT7A6632 removes the interruption channel No. and buffer
status without waiting for acknowledge from the CPU. See
Figure 34.
The CPU can take the actual status byte address and it can
relocate the completed buffers within the 64k byte bank and
also cross-check against its own list of linked buffer addresses.
If all the buffer start addresses are divisible exactly by 8, they
can be derived from the STATUS byte addresses by setting the
three LSB addresses to zero.
Figure 34. Interrupt Indication
INTR
1/2 TCLK Period
6632 Updates Status
PT019(05/02)
43
Channel No. and Status
are valid on the bus
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure 35. PT7A6632 External Memory Example Interface Waveforms - Single Write Memory Access
SYSCLK
DMND
AS
A0-A15
WRITE
INTR*
D0-D7
Rx/Tx
CH0-CH4
* Activated by status write only.
Figure 36. PT7A6632 External Memory Example Interface Waveforms - Double Write Memory Access
SYSCLK
DMND
AS
A0-A15
WRITE
INTR*
D0-D7
Rx/Tx
CH0-CH4
* Activated by status write only.
PT019(05/02)
44
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure 37. PT7A6632 External Memory Example Interface Waveforms - Single Read Memory Access
SYSCLK
DMND
AS
A0-A15
READ
D0-D7
Rx/Tx
CH0-CH4
Figure 38. PT7A6632 External Memory Example Interface Waveforms - Read Write Double Memory Access
SYSCLK
DMND
AS
A0-A15
READ
WRITE
D0-D7
INTR*
Rx/Tx
CH0-CH4
* Activated by status write only.
PT019(05/02)
45
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure 39. PT7A6632 External Memory Example Interface Waveforms - Write Read Double Memory Access
SYSCLK
DMND
AS
A0-A15
READ
WRITE
D0-D7
INTR*
Rx/Tx
CH0-CH4
Figure 40. PT7A6632 External Memory Example Interface Waveforms - Single Activation Read Memory Access
SYSCLK
DMND
AS
A0-A15
READ
D0-D7
Rx/Tx
CH0-CH4
SYSACC
PT019(05/02)
46
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure 41. PT7A6632 External Memory Example Interface Waveforms - Single Write Memory Access Plus a Single
Activation Read Access
SYSCLK
DMND
AS
A0-A15
WRITE
INTR*
D0-D7
Rx/Tx
CH0-CH4
READ
SYSACC
* Activated by status write only.
Figure 42. PT7A6632 External Memory Example Interface Waveforms - Single Write Memory Access Plus a Double
Activation Read Access
SYSCLK
DMND
AS
A0-A15
WRITE
INTR*
D0-D7
Rx/Tx
CH0-CH4
READ
SYSACC
* Activated by status write only.
PT019(05/02)
47
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure 43. PT7A6632 External Memory Example Interface Waveforms - Write/Read Double Memory Access Plus a
Single Activation Read Access
SYSCLK
DMND
AS
A0-A15
READ
WRITE
D0-D7
INTR*
Rx/Tx
CH0-CH4
SYSACC
* Activated by status write only.
Detailed Specifications
Absolute Maximum Ratings
Storage Temperature ...................................................... -65oC to +150oC
Ambient Temperature with Power Applied ...................... -40oC to +85oC
Supply Voltage to Ground Potential (Inputs & VCC Only) ...... -0.3 to 7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) .. -0.3 to 7.0V
DC Input Voltage .................................................................. -0.3 to 7.0V
DC Output Current ...................................................................... 120mA
Power Dissipation .............................................................................. 2W
Note:
Operation at levels greater than those listed under
“Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or
any other conditions above those indicated in the
Operation Condition tables is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions
Table 16. Recommended Operating Conditions
Sym
Descr ip t ion
Test C on d it ion s
Min
Typ
Ma x
Un it s
VCC
Supply Voltage
4.5
5.0
5.5
V
TA
Operating Temperature
Over Recommended
Operating Conditions
-40
25
85
o
C
Note:
Typical figures are at 25oC and are for design aid only; not production tested.
PT019(05/02)
48
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
DC Electrical, Power Supply and Capacitance Characteristics
Table 17. DC Electrical, Power Supply and Capacitance Characteristics
Sym
Descr ip t ion
Test C on d it ion s
Min
Typ
Ma x
Un it s
ICC
Supply Current
VCC = 5V, all clock sources
are connected to
corresponding pins
4
12
mA
VIH
Input HIGH Voltage
500mV noise margin
VIL
Input LOW Voltage
500mV noise margin
VOL
Output LOW Voltage
IOL = 10mA*
VOH
Output HIGH Voltage (CMOS)
IOH = 10mA*
3.5
4.5
V
IOL
Output LOW Current
VOL = 0.5V
4
12
mA
IOH
Output HIGH Current
VOH = 4.5V
4
10
mA
CIN
Input Pin Capacitance
10
pF
COUT
Output Pin Capacitance
10
pF
2.4
V
0.5
0.8
V
1
V
Note:
Typical figures are at 25oC and are for design aid only; not production tested.
* IOL and IOH are obsolute values.
PT019(05/02)
49
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AC Characteristics
(Note: All output AC timing measurements are referenced to the 0.4V for low level and 2.4V for high level, and all input AC
timing measurements are referenced to the 0.8V for low level and 2.0V for high level.)
Serial Interface
• Transmit Frame Synchronization Timing
Table 18. Transmit Frame Synchronization Timing
Sym
Descr ip t ion
Test C on d it ion s
Min
Typ
Ma x
Un it s
tMS
TMAX Setup Time
50
ns
tMH
TMAX Hold Time
50
ns
Figure 44. Diagram of Transmit Frame Synchronization Timing (SIS = 1)
TCLK
tMS
tMH
TMAX
(From T1/E1 Controller)
TSER
(From PT7A6632)
BIT 8, CH24
F BIT
BIT 1, CH1
a. Transmit Serial Output - T1 Mode, TSEREN=1
TCLK
tMS
tMH
TMAX
(From T1/E1 Controller)
TSER
(From PT7A6632)
BIT 8, CH24
F BIT
BIT 1, CH1
b. Transmit Serial Output - T1 Mode, TSEREN=0
TCLK
tMS
tMH
TMAX
(From T1/E1 Controller)
TSER
(From PT7A6632)
BIT 7, TS31
BIT 8, TS31
BIT 1, TS0
BIT 2, TS0
c. Transmit Serial Output - CEPT PCM-30 Mode, TSEREN=0 or 1
PT019(05/02)
50
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
• Clock Timing
Table 19. Clock Timing
Sym
Descr ip t ion
Test C on d it ion s
Min
Typ
Ma x
Un it s
tTCD
TCLK Delay
0
50
ns
tSCPW
SYSCLK Pulse Width
110
122
ns
tTCPW
TCLK Pulse Width
200
244
ns
tSCP
SYSCLK Period
240
244
tR/tF
Rise Time/Fall Time (SYSCLK)
1000
ns
5
ns
Figure 45. Clock Timing
tSCP
tR
tSCPW
tSCPW
tF
SYSCLK
tTCD
tTCD
TCLK
PT019(05/02)
tTCPW
51
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
• TCLK - RCLK Timing
Table 20. TCLK - RCLK Timing
Sym
Descr ip t ion
Test C on d it ion s
Min
Typ
200
244
Ma x
Un it s
tRCPW
RCLK Pulse Width
tTRCD
TCLK, RCLK Difference
*
ns
tR/tF
Rise Time/Fall Time (RCLK, TCLK)
10
ns
ns
* RCLK is to be centered around TCLK. The summation of RCLK and TCLK periodic differences over any duration of
time must never exceed 14 TCLK periods.
Figure 46. TCLK - RCLK Timing
tR
TCLK
tF
tRCPW
tTRCD
tR
tF
RCLK
tRCPW
PT019(05/02)
52
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
• PT7A6632 Receive Frame Synchronization Timing
Table 29. Receive Frame Synchronization Timing
Sym
Descr ip t ion
Test C on d it ion s
Min
Typ
Ma x
Un it s
tRS
RSYNC Setup Time
50
ns
tRH
RSYNC Hold Time
50
ns
Figure 47. Diagram of Receive Frame Synchronization Timing (SIS=1)
RCLK
tRS
tRH
RSYNC
(From T1/E1 Controller)
RSER
(From PT7A6632)
F BIT
BIT 1, CH1
a. Receive Serial Output - T1 Mode
RCLK
tRS
tRH
RSYNC
(From T1/E1 Controller)
RSER
(From PT7A6632)
BIT 1, TS0
BIT 2, TS0
b. Receive Serial Output - CEPT PCM-30 Mode
PT019(05/02)
53
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
External Memory Interface
• Read Cycle Timing
Table 22. Read Cycle Timing
Sym
Descr ip t ion
Test C on d it ion s
tASD
Address Strobe Delay
tAD
Min
Ma x
Un it s
10
75
ns
Address Delay
10
78
ns
tAF
Address Float Delay
10
75
ns
tRD
Read Enable Delay
10
78
ns
tRDA
Read Data Access Time
*
ns
tRDH
Read Data Hold Time
**
ns
0
Typ
* Read data access time for shared memory = tSCP -125ns.
** Data drive to data bus float = tSCPW - 65ns.
Figure 48. Read Cycle Timing
SYSCLK
AS
tASD
tAF
tAD
tAF
2.0V
0.8V
2.0V
ADDRESS
0.8V
tRD
tRD
READ
tRDH
tRDA
2.0V
0.8V
2.0V
D0-D7
PT019(05/02)
2.0V
0.8V
0.8V
54
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
• Write Cycle Timing
Table 23. Write Cycle Timing
Sym
Descr ip t ion
Test C on d it ion s
tASD
Address Strobe Delay
tAD
Min
Typ
Ma x
Un it s
10
78
ns
Address Delay
10
100
ns
tAF
Address Float Delay
10
90
ns
tWD
Write Delay
10
75
ns
tWP
Write Pulse Width
80
tID
Interrupt Delay
10
tWDD
Write Data Delay
10
120
ns
tWDH
Write Data Hold Time*
10
90
ns
117
ns
ns
* Data drive to data bus float time
Figure 49. Write Cycle Timing
SYSCLK
AS
tASD
2.0V
0.8V
tASD
tAD
2.0V
0.8V
tAF
2.0V
ADDRESS
0.8V
tWD
tWD
WRITE
2.0V
0.8V
tID
tWP
2.0V
0.8V
INTR
tWDD
tID
tWDH
2.0V
D0-D7
PT019(05/02)
0.8V
55
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Channel Activation/Deactivation
Table 24. Channel Activation/Deactivation Timing
Sym
Descr ip t ion
Test C on d it ion s
Min
tATNS
ATTN to ATACK Response Time
20
tATNH
ATTN Hold Time
0
tATKR
ATACK Reset Delay
2
Typ
Ma x
Un it s
48
SYSCLKs
ns
4
SYSCLKs
Figure 50. Channel Activation/DeactivationTiming
SYSCLK
ATTN
ATACK
tATNH
tATNS
PT019(05/02)
tATNH
56
tATKR
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Input Characteristics
Table 25. Input Characteristics
Sign a l Na me
R efer en ce Sign a l
E ffect ive E d ge
Set u p (Min .)
H old (Min .)
Un it s
ATTN
SYSCLK
Rising
50
50
ns
RESET
TCLK
Rising
60
60
ns
D0-D7
SYSCLK
Rising
50
0
ns
TMAX (SIS = 1)
TCLK
Falling
50
50
ns
TMAX (SIS = 0)
TCLK
Rising
50
50
ns
RSER (SIS = 1)
RCLK
Falling
50
50
ns
RSER (SIS = 0)
RCLK
Rising
50
50
ns
RRED (SIS = 1)
RCLK
Falling
50
50
ns
RRED (SIS = 0)
RCLK
Rising
50
50
ns
RSYNC (SIS =1)
RCLK
Falling
50
50
ns
RSYNC (SIS = 0)
RCLK
Rising
50
50
ns
PT019(05/02)
57
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Output Characteristics
Table 26. Output Characteristics
Sign a l Na me
R efer en ce Sign a l
E ffect ive E d ge
Dela y (Ma x.)
H old (Min .)
Un it s
DMND
SYSCLK
Rising
90
10
ns
AS
SYSCLK
Rising/Falling
78
10
ns
A0-A15
SYSCLK
Rising
100
10
ns
SYSACC
SYSCLK
Rising
70
10
ns
READ
SYSCLK
Rising
78
10
ns
WRITE
SYSCLK
Rising/Falling
120
10
ns
D0-D7
SYSCLK
Falling
120
10
ns
INTR
SYSCLK
Falling
120
10
ns
CH0-CH4
SYSCLK
Rising
70
10
ns
Rx/Tx
SYSCLK
Rising
70
10
ns
ATACK
SYSCLK
Rising
75
10
ns
TSER
TCLK
Falling
65
10
ns
PT019(05/02)
58
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Mechanical Specifications
Figure 51. 68-Pin PLCC
PT019(05/02)
59
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Ordering Information
Table 27. Ordering Information
PT019(05/02)
Pa r t Nu mb er
Pa ck a ge
PT7A6632J
68-Pin PLCC
60
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Notes
Pericom Technology Inc.
Email: [email protected]
Web-Site: www.pti.com.cn, www.pti-ic.com
China:
No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China
Tel: (86)-21-6485 0576
Fax: (86)-21-6485 2181
Asia Pacific:
Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong
Tel: (852)-2243 3660
Fax: (852)- 2243 3667
U.S.A.:
2380 Bering Drive, San Jose, California 95131, USA
Tel: (1)-408-435 0800
Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve
design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described
other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from
patent infringement or other rights, of Pericom Technology Incorporation.
PT019(05/02)
61
Ver:2