TI SN74ABT533N

SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
•
•
description
The ′ABT533 are 8-bit transparent D-type latches
with 3-state outputs designed specifically for
driving highly capacitive or relatively lowimpedance loads. They are particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
When the latch-enable (LE) input is high, the
Q outputs follow the complements of the data
(D) inputs. When LE is taken low, the Q outputs
are latched at the inverse of the levels set up at the
D inputs. The ′ABT533 provides inverted data at
its outputs.
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
SN54ABT533 . . . FK PACKAGE
(TOP VIEW)
2D
2Q
3Q
3D
4D
8Q
•
SN54ABT533 . . . J PACKAGE
SN74ABT533 . . . DB, DW, OR N PACKAGE
(TOP VIEW)
1D
1Q
OE
VCC
•
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
High-Drive Outputs (– 32-mA IOH,
64-mA IOL )
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic
Chip Carriers (FK), and Plastic (N) and
Ceramic (J) DIPs
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
LE
5Q
5D
•
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Previously stored data can be retained or new data
can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT533 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT533 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74ABT533 is characterized for operation from – 40°C to 85°C.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright  1994, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
FUNCTION TABLE
(each latch)
INPUTS
LE
D
L
H
H
L
L
H
L
H
L
L
X
Q0
H
X
X
Z
logic symbol†
1
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
11
3
4
OUTPUT
Q
OE
logic diagram (positive logic)
OE
1
EN
LE
C1
1D
1
2
5
7
6
8
9
13
12
14
15
17
16
18
19
11
C1
1Q
1D
3
1Q
1D
2Q
3Q
4Q
C1
2D
4
5Q
C1
7Q
8Q
3D
POST OFFICE BOX 655303
4Q
12
5Q
13
1D
14
17
18
• DALLAS, TEXAS 75265
15
6Q
1D
16
7Q
1D
C1
8D
9
1D
C1
7D
3Q
8
C1
6D
2Q
1D
C1
5D
6
7
C1
4D
5
1D
6Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2–2
2
1D
19
8Q
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . . . – 0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . 0.6 W
DW package . . . . . . . . . . . . . . . . . . . 1.6 W
N package . . . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
SN54ABT533
SN74ABT533
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
– 24
Low-level output current
48
64
mA
∆t /∆v
Input transition rise or fall rate
10
10
ns / V
85
°C
High-level input voltage
2
2
0.8
Input voltage
0
TA
Operating free-air temperature
NOTE 3: Unused or floating inputs must be held high or low.
– 55
125
V
0.8
0
– 40
V
VCC
– 32
V
V
mA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–3
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = – 3 mA
VCC = 5 V,
VCC = 4
4.5
5V
MIN
–1.2
MAX
SN74ABT533
MIN
–1.2
IOH = – 3 mA
IOH = – 24 mA
3
3
3
2
2
IOH = – 32 mA
IOL = 48 mA
2*
VCC = 5.5 V,
VCC = 5.5 V,
IOZL
Ioff
VCC = 5.5 V,
VCC = 0,
ICEX
IO§
VCC = 5.5 V,
VCC = 5.5 V,
ICC
VCC = 5.5
5 5 V,
V
IO = 0,
0
VI = VCC or GND
IOL = 64 mA
VI = VCC or GND
±1
10‡
– 10‡
±150
Outputs high
50
Outputs high
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
0.55
±1
10‡
– 10‡
VO = 2.7 V
VO = 0.5 V
– 50
V
V
0.55
0.55*
VO = 2.5 V
UNIT
2
0.55
VI or VO ≤ 4.5 V
VO = 5.5 V
MAX
–1.2
2.5
II
IOZH
Co
MIN
2.5
VCC = 4
4.5
5V
Ci
SN54ABT533
2.5
VOL
∆ICC¶
TA = 25°C
TYP†
MAX
–140
–180
1
250
50
– 50
–180
– 50
250
V
±1
10‡
– 10‡
µA
±150
µA
µA
µA
50
µA
–180
mA
250
µA
Outputs low
24
30
30
30
mA
Outputs disabled
0.5
250
250
250
µA
Outputs enabled
1.5
1.5
1.5
Outputs disabled
1.5
1.5
1.5
Control inputs
1.5
1.5
1.5
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
mA
3
pF
9
pF
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ This data sheet limit may vary among suppliers.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure1)
VCC = 5 V,
TA = 25°C
MIN
tw
tsu
Pulse duration, LE high
Setup time, data before LE↓
High or low
th
Hold time, data after LE↓
High or low
POST OFFICE BOX 655303
MIN
MAX
SN74ABT533
MIN
UNIT
MAX
3.3
3.3
3.3
ns
2.1
1.5§
2.1
1.5§
2.1
1.5§
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2–4
MAX
SN54ABT533
• DALLAS, TEXAS 75265
ns
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
PARAMETER
VCC = 5 V,
TA = 25°C
SN54ABT533
SN74ABT533
MIN
TYP
MAX
MIN
MAX
MIN
MAX
1.9
4.2
5.4
1.9
6.7
1.9
6.4
3.1
4.9
6.3
3.1
6.9
3.1
6.6
2.7
4.9
6.2
2.7
7.6
2.7
7.3
3.5
5.4
6.8
3.5
7.5
3.5
7.3
1.6
3.7
4.8
1.6
5.8
1.6
5.7
2.4
4.2
6.2
2.4
6.9
2.4
6.7
2.8
5.1
6.2
2.8
7.2
2.8
6.9
2
4.1
6
2
6.9
2
6.5
UNIT
ns
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–5
SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A – FEBRUARY 1991 – REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT FOR OUTPUTS
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
(see Note B)
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note C)
tPLH
tPHL
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
1.5 V
Output
Waveform 2
S1 at Open
(see Note C)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-9584301Q2A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
5962-9584301QRA
ACTIVE
CDIP
J
20
1
TBD
Call TI
Level-NC-NC-NC
1
Lead/Ball Finish
MSL Peak Temp (3)
5962-9584301QSA
ACTIVE
CFP
W
20
TBD
Call TI
Level-NC-NC-NC
SN74ABT533DBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
SN74ABT533DW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74ABT533DWR
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN74ABT533N
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
SNJ54ABT533FK
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ABT533J
ACTIVE
CDIP
J
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ABT533W
ACTIVE
CFP
W
20
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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