SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCES066G – JUNE 1996 – REVISED APRIL 2002 D D D D D D D D D State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C High Drive (–32/64 mA at 3.3-V VCC) Ioff and Power-Up 3-State Support Hot Insertion Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II SN54ALVTH16245 . . . WD PACKAGE SN74ALVTH16245 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR description The ’ALVTH16245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.2 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright 2002, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCES066G – JUNE 1996 – REVISED APRIL 2002 SN74ALVTH16245 . . . GQL PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 1 2 3 4 5 6 A 1DIR NC NC NC NC 1OE B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 1A4 1B6 1B5 VCC GND 1A3 D VCC GND 1A5 1A6 E 1B8 1B7 1A7 1A8 E F 2B1 2B2 2A2 2A1 F G 2B3 2B4 GND GND 2A4 2A3 G H 2B5 2B6 VCC GND 2A6 2A5 2A8 2A7 NC NC 2OE A B C D H J 2B7 2B8 VCC GND J K 2DIR NC NC NC – No internal connection K ORDERING INFORMATION TA –40°C 40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TOP-SIDE MARKING SSOP – DL Tape and reel SN74ALVTH16245DLR ALVTH16245 TSSOP – DGG Tape and reel SN74ALVTH16245GR ALVTH16245 TVSOP – DGV Tape and reel SN74ALVTH16245VR VT245 VFBGA – GQL Tape and reel SN74ALVTH16245QR –55°C to 125°C CFP – WD Tube SNJ54ALVTH16245WD SNJ54ALVTH16245WD † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each 8-bit section) INPUTS 2 OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCES066G – JUNE 1996 – REVISED APRIL 2002 logic diagram (positive logic) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 2OE 36 13 1B1 To Seven Other Channels 2B1 To Seven Other Channels Pin numbers shown are for the DGG, DGV, DL, and WD packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO (see Note 1) . . . . . . . . . –0.5 V to 7 V Output current in the low state, IO: SN54ALVTH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA SN74ALVTH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCES066G – JUNE 1996 – REVISED APRIL 2002 recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3) SN54ALVTH16245 SN74ALVTH16245 MIN MAX MIN 2.7 2.3 VCC VIH Supply voltage 2.3 High-level input voltage 1.7 VIL VI Low-level input voltage IOH High-level output current IOL ∆t/∆v TYP TYP 2.7 1.7 0 VCC 5.5 0.7 0 VCC –6 Low-level output current V V 5.5 V –8 mA 6 8 Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 18 24 Input transition rise or fall rate 10 10 Outputs enabled UNIT V 0.7 Input voltage MAX mA ns/V ∆t/∆VCC Power-up ramp rate 200 200 µs/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3) SN54ALVTH16245 SN74ALVTH16245 MIN MAX MIN 3.6 3 VCC VIH Supply voltage 3 High-level input voltage 2 VIL VI Low-level input voltage IOH High-level output current Low-level output current Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz IOL TYP TYP 3.6 2 0 ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 Outputs enabled VCC UNIT V V 0.8 Input voltage MAX 0.8 V 5.5 V –24 –32 mA 24 32 48 64 5.5 0 10 VCC 10 –40 ns/V µs/V 200 125 mA 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCES066G – JUNE 1996 – REVISED APRIL 2002 electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER VIK VOH VCC = 2.3 V, VCC = 2.3 V to 2.7 V, II = –18 mA IOH = –100 µA 3V VCC = 2 2.3 IOH = –6 mA IOH = –8 mA VCC = 2.3 V to 2.7 V, VOL VCC = 2 2.3 3V Control inputs VCC = 2.7 V, VCC = 0 or 2.7 V, A or B ports VCC = 2.7 V II Ioff IBHL‡ IBHH§ IBHLO¶ IBHHO# IEX|| SN54ALVTH16245 MIN TYP† MAX TEST CONDITIONS SN74ALVTH16245 MIN TYP† MAX –1.2 VCC–0.2 1.8 –1.2 V 1.8 IOL = 100 µA IOL = 6 mA 0.2 0.2 0.4 IOL = 8 mA IOL = 18 mA 0.4 V 0.5 IOL = 24 mA VI = VCC or GND 0.5 ±1 ±1 VI = 5.5 V VI = 5.5 V 10 10 20 20 VI = VCC VI = 0 1 1 –5 –5 VCC = 0, VCC = 2.3 V, VI or VO = 0 to 4.5 V VI = 0.7 V VCC = 2.3 V, VCC = 2.7 V, VI = 1.7 V VI = 0 to VCC VCC = 2.7 V, VCC = 2.3 V, VI = 0 to VCC VO = 5.5 V ±100 µA µA 115 115 µA –10 –10 µA 300 300 µA –300 –300 µA 125 125 µA ±100 ±100 µA IOZ(PU/PD)k VCC = 2.7 V, IO = 0, VI = VCC or GND Outputs high 0.04 0.1 0.04 0.1 ICC Outputs low 2.3 4.5 2.3 4.5 Outputs disabled 0.04 0.1 0.04 0.1 VCC = 2.5 V, VCC = 2.5 V, VI = 2.5 V or 0 VO = 2.5 V or 0 3.5 3.5 8 8 Cio V VCC–0.2 VCC ≤ 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don’t care Ci UNIT mA pF pF † All typical values are at VCC = 2.5 V, TA = 25°C. ‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. § The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCES066G – JUNE 1996 – REVISED APRIL 2002 electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER VIK VOH VCC = 3 V, VCC = 3 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 3 V IOH = –24 mA IOH = –32 mA VCC = 3 V to 3.6 V, VOL VCC = 3 V Control inputs Ioff IBHL‡ IBHH§ IBHLO¶ IBHHO# IEX|| IOZ(PU/PD)k ICC 2 IOL = 100 µA IOL = 16 mA 0.2 IOL = 24 mA IOL = 32 mA 0.5 IOL = 48 mA IOL = 64 mA 0.55 0.5 V 0.55 ±1 ±1 10 10 20 20 1 1 VI = 0 VI or VO = 0 to 4.5 V –5 VI = 0.8 V VI = 2 V VI = 0 to VCC VI = 0 to VCC 75 µA –75 –75 µA 500 500 µA Outputs high Outputs low Outputs disabled Ci VCC = 3.3 V, VCC = 3.3 V, VI = 3.3 V or 0 VO = 3.3 V or 0 µA –500 0.07 VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND µA 75 –500 ∆ICCh µA –5 ±100 VO = 5.5 V VCC ≤ 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don’t care VCC = 3.6 V, IO = 0, VI = VCC or GND 0.2 0.4 VCC = 3.6 V VCC = 3.6 V, VCC = 3 V, V V VI = 5.5 V VI = VCC VCC = 3 V, VCC = 3.6 V, –1.2 UNIT VCC–0.2 VI = VCC or GND VI = 5.5 V VCC = 0, VCC = 3 V, SN74ALVTH16245 MIN TYP† MAX –1.2 VCC–0.2 2 VCC = 3.6 V, VCC = 0 or 3.6 V, II A or B ports SN54ALVTH16245 MIN TYP† MAX TEST CONDITIONS 125 125 µA ±100 ±100 µA 0.1 0.07 0.1 3.2 5 3.2 5 0.07 0.1 0.07 0.1 0.2 3.5 0.2 3.5 mA mA pF Cio 8 8 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. § The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down h This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCES066G – JUNE 1996 – REVISED APRIL 2002 switching characteristics over recommended operating free-air temperature range, CL = 30 pF, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OE A or B OE A or B tPHZ tPLZ SN54ALVTH16245 SN74ALVTH16245 MIN MAX MIN MAX 0.5 3.6 0.5 3.6 0.5 3.4 0.5 3.4 1.5 4.9 1.5 4.9 1 4 1 4 1.5 4.9 1.5 4.9 1 4.2 1 4.2 UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OE A or B OE A or B tPHZ tPLZ SN54ALVTH16245 SN74ALVTH16245 MIN MAX MIN MAX 0.5 3.1 0.5 3.1 0.5 2.9 0.5 2.9 1 4.2 1 4.2 1 3.5 1 3.5 1.5 5.3 1.5 5.3 1.5 5 1.5 5 UNIT ns ns ns skew tps (pin or transition skew), tps = |tPHL – tPHL| tpsmax VCC = 2.5 V TYP VCC = 3.3 V TYP UNIT 438 118 ps tOST = |tpΦm – tpΦn|, where Φ is any edge transition (high to low or low to high) measured between any two outputs (m or n) within any given device (see Note 4) tOST VCC = 2.5 V TYP VCC = 3.3 V TYP A–B 227 248 B–A 223 243 UNIT ps NOTE 4: One output switching, TA = 25°C tOSHL/tOSLH (common edge skew), tOSHL = |tPHLmax – tPHLmin| (output skew for low-to-high transitions), and tOSLH = |tPLHmax – tPLHmin| (output skew for high-to-low transitions) (see Note 4) tOSLH tOSHL A B A–B tOSLH tOSHL B A B–A VCC = 2.5 V TYP VCC = 3.3 V TYP 210 145 243 351 207 136 238 350 UNIT ps ps NOTE 4: One output switching, TA = 25°C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ALVTH16245, SN74ALVTH16245 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCES066G – JUNE 1996 – REVISED APRIL 2002 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND CL 30 pF 50 pF VCC 2.5 V ±0.2 V 3.3 V ±0.3 V LOAD CIRCUIT V∆ 0.15 V 0.3 V RL 500 Ω 500 Ω VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input VCC/2 th VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH Output VCC/2 VOL tPHL VCC/2 tPLZ VCC VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ tPZH VCC/2 VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VOH Output VCC/2 tPZL VOH VCC/2 VCC Output Control VCC/2 VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 4-Oct-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74ALVTH16245GRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVTH16245VRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVTH16245ZQLR ACTIVE VFBGA ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74ALVTH16245DL ACTIVE SSOP DL 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVTH16245DLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVTH16245GR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVTH16245KR ACTIVE VFBGA GQL 56 1000 SNPB Level-1-240C-UNLIM SN74ALVTH16245VR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 25 TBD Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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