TI CDCVF25081

CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
D Phase-Locked Loop-Based Zero-Delay
D PACKAGE (SOIC)
PW PACKAGE (TSSOP)
(TOP VIEW)
Buffer
D Operating Frequency: 8 MHz to 200 MHz
D Low Jitter (Cycle-Cycle): ±100 ps Over the
D
D
D
D
D
D
D
D
D
1
2
3
4
5
6
7
8
CLKIN
1Y0
1Y1
VDD
GND
2Y0
2Y1
S2
Range 66 MHz to 200 MHz
Distributes One Clock Input to Two Banks
of Four Outputs
Auto Frequency Detection to Disable
Device (Power Down Mode)
Consumes Less Than 20 µA in Power Down
Mode
Operates From Single 3.3-V Supply
Industrial Temperature Range –40°C to
85°C
25-Ω On-Chip Series Damping Resistors
No External RC Network Required
Spread Spectrum Clock Compatible (SSC)
Available in 16-Pin TSSOP or 16-Pin SOIC
Packages
16
15
14
13
12
11
10
9
FBIN
1Y3
1Y2
VDD
GND
2Y3
2Y2
S1
description
The CDCVF25081 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a PLL to
precisely align, in both frequency and phase, the output clocks to the input clock signal. The CDCVF25081
operates from a nominal supply voltage of 3.3 V. The device also includes integrated series-damping resistors
in the output drivers that make it ideal for driving point-to-point loads.
Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN. All outputs operate at the same
frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device
automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a
low state. Unlike many products containing PLLs, the CDCVF25081 does not require an external RC network.
The loop filter for the PLL is included on-chip, minimizing component count, space, and cost.
Because it is based on a PLL circuitry, the CDCVF25081 requires a stabilization time to achieve phase lock of
the feedback signal to the reference signal. This stabilization is required following power up and application of
a fixed-frequency signal at CLKIN and any following changes to the PLL reference.
The CDCVF25081 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
S2
S1
1Y0–1Y3
2Y0–2Y3
OUTPUT SOURCE
PLL SHUTDOWN
0
0
Hi-Z
Hi-Z
Yes
0
1
Active
Hi-Z
N/A.
PLL†
1
0
Active
Active
Input clock (PLL bypass)
PLL†
Yes
No
1
1
Active
Active
† CLK input frequency < 2 MHz switches the outputs to low level
No
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001 – 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
Terminal Functions
TERMINAL
2
TYPE
DESCRIPTION
NAME
PIN NO.
1Y[0:3]
2, 3, 14, 15
O
Bank 1Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated
25-Ω series-damping resistor.
2Y[0:3]
6, 7, 10, 11
O
Bank 2Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated
25-Ω series-damping resistor.
CLKIN
1
I
Clock input. CLKIN provides the clock signal to be distributed by the CDCVF25081 clock driver. CLKIN is
used to provide the reference signal to the integrated PLL that generates the output signal. CLKIN must
have a fixed frequency and phase in order for the PLL to acquire lock. Once the circuit is powered up and
a valid signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to
CLKIN.
FBIN
16
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be wired to one of the
outputs to complete the feedback loop of the internal PLL. The integrated PLL synchronizes the FBIN and
output signal so there is nominally zero-delay from input clock to output clock.
GND
5, 12
Ground
S1, S2
9, 8
I
VDD
4, 13
Power
Ground
Select pins to determine mode of operation. See the FUNCTION TABLE for mode selection options.
Supply voltage. The supply voltage range is 3 V to 3.6 V
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CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
functional block diagram
2
25 Ω
FBIN
CLKIN
16
1
PLL
M
U
X
3
25 Ω
14
25 Ω
15
25 Ω
S2
S1
1Y0
1Y1
1Y2
1Y3
8
9
Input
Select
Decoding
6
25 Ω
7
25 Ω
10
25 Ω
11
25 Ω
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2Y0
2Y1
2Y2
2Y3
3
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous total output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147°C/W
D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
Supply voltage, VDD
3
NOM
MAX
3.3
3.6
V
0.8
V
Low level input voltage, VIL
High level input voltage, VIH
2
Input voltage, VI
0
UNIT
V
3.6
V
High-level output current, IOH
–12
mA
Low-level output current, IOL
12
mA
Operating free-air temperature, TA
-40
85
°C
timing requirements over recommended ranges of supply voltage, load and operating free-air
temperature
MIN
Clock frequency,
frequency fclk
4
NOM
MAX
CL = 25 pF
8
100
CL = 15 pF
66
200
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UNIT
MHz
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
II
Input voltage
IPD‡
IOZ
Power down current
CI
Input capacitance at FBIN, CLKIN
CI
Input capacitance at S1, S2
CO
Output capacitance
VOH
VOL
TEST CONDITIONS
Input current
Output 3-state
VDD = 3 V,
VI = 0 V or VDD
II = -18 mA
fCLKIN = 0 MHz,
Vo = 0 V or VDD,
VDD = 3.3 V
VDD = 3.6 V
VI = 0 V or VDD
VI = 0 V or VDD
VI = 0 V or VDD
VDD = min to max,
VDD = 3 V,
VDD = 3 V,
High-level
High
level out
output
ut voltage
VDD = min to max,
VDD = 3 V,
Low-level
output
Low
level out
ut voltage
VDD = 3 V,
VDD = 3 V,
IOH
IOL
MIN
VDD = 3.3 V,
VDD = 3.6 V,
High-level
High
level out
output
ut current
VDD = 3 V,
VDD = 3.3 V,
Low-level output current
VDD = 3.6 V,
IOH = -100 µA
IOH = -12 mA
VDD – 0.2
2.1
IOH = -6 mA
IOL = 100 µA
2.4
TYP†
VO = 3.135 V
VO = 1.95 V
VO = 1.65 V
VO = 0.4 V
UNIT
–1.2
V
±5
µA
20
µA
±5
µA
4
pF
2.2
pF
3
pF
V
0.2
IOL = 12 mA
IOL = 6 mA
VO = 1 V
VO = 1.65 V
MAX
0.8
V
0.55
–24
–30
mA
-15
26
mA
33
14
† All typical values are at respective nominal VDD.
‡ For IDD over frequency see Figure 7.
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CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
t(lock)
t(phoffset)
TEST CONDITIONS
PLL lock time
MIN
f = 100 MHz
Phase offset (CLKIN to FBIN)
tPLH
tPHL
Low-to-high level output propagation delay
tsk(o)
Output skew (Yn to Yn) (see Note 4)
tsk(pp)
Part to part skew
Part-to-part
High-to-low level output propagation delay
TYP†
MAX
UNIT
µs
10
f = 8 MHz to 66 MHz,
Vth = VDD/2 (see Note 5)
–200
200
f = 66 MHz to 200 MHz,
Vth = VDD/2 (see Note 5)
–150
150
2.5
6
ns
150
ps
S2 = High,
f = 1 MHz,
S1 = Low (PLL by
bypass)
ass)
CL = 25 pF
ps
S2 = high,
S1 = high (PLL mode)
600
S2 = high,
S1 = low (PLL bypass)
700
f = 66 MHz to 200 MHz, CL = 15 pF
±100
±150
tjit(cc)
Jitter (cycle-to-cycle)
f = 66 MHz to 100 MHz, CL = 25 pF
f = 8 MHz to 66 MHz (see Figure 6)
odc
Output duty cycle
f = 8 MHz to 200 MHz
tsk(p)
Pulse skew
S2 = High,
f = 1 MHz,
S1 = low (PLL bypass)
CL = 25 pF
0.8
3.3
Rise time rate
CL = 15 pF,
See Figure 4
tr
CL = 25 pF,
See Figure 4
0.5
2
0.8
3.3
Fall time rate
CL = 15 pF,
See Figure 4
tf
CL = 25 pF,
See Figure 4
0.5
2
43%
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ps
57%
0.7
† All typical values are at respective nominal VDD.
NOTES: 4. The tsk(o) specification is only valid for equal loading of all outputs.
5. Similar waveform at CLKIN and FBIN are required. For phase displacement between CLKIN and Y-outputs see Figure 5.
6
ps
ns
V/ns
V/ns
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
VDD
1000 Ω
From Output Under Test
CL = 25 pF at f = 8 MHz to 100 MHz
CL = 15 pF at f = 66 MHz to 200 MHz
1000 Ω
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: ZO = 50 Ω, tr < 1.2 ns, tf < 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Test Load Circuit
VDD
50% VDD
CLKIN
0V
t(phoffset)
VOH
50% VDD
FBIN
VOL
Figure 2. Voltage Thresholds for Measurements, Phase Offset (PLL Mode)
50% VDD
Any Y
50% VDD
50% VDD
Any Y
t1
tsk(0)
t2
tsk(0)
NOTE: odc = t1/(t1 + t2) x 100%
Figure 3. Output Skew and Output Duty Cycle (PLL Mode)
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CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
VDD
50% VDD
CLKIN
0V
tPLH
tPHL
80%
VOH
80%
50% VDD
20%
50% VDD
20%
Any Y
VOL
tr
tf
NOTE: tsk(p)=|tPLH–tPHL|
Figure 4. Propagation Delay and Pulse Skew (Non-PLL Mode)
PHASE DISPLACEMENT
vs
CLOAD
CYCLE-TO-CYCLE JITTER
vs
FREQUENCY
100
500
VDD = 3.3 V
All Outputs Switching
CL(Yn) = 25 pF || 500 Ω
450
VDD = 3 V
400
Cycle-to-Cycle Jitter – ps
Phase Displacement – ps
50
0
VDD = 3.6 V
–50
VDD = 3.3 V
–100
350
300
250
200
150
100
50
–150
–10 –8
–6
–4
–2
0
2
4
6
8
10
0
10
20
Cload Difference Between FBIN and Yn Pins – pF
40
50
60
Figure 5
Figure 6
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f – Frequency – MHz
(CFB + 4 pF) – CYn
8
30
• DALLAS, TEXAS 75265
80
90
100
CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
SUPPLY CURRENT
vs
FREQUENCY
180
VDD = 3 V to 3.6 V
CL(Yn) = 15 pF || 500 Ω
TA = –40°C to 85°C
IDD – Supply current – mA
160
VDD = 3.6 V
TA = 85°C
140
VDD = 3.6 V
TA = –40°C
120
100
VDD = 3 V
TA = –40°C
80
60
VDD = 3 V
TA = 85°C
40
20
0
0
20
40
60
80 100 120 140 160 180 200
f – Frequency – MHz
Figure 7
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CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–ā8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
10
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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