CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638 – DECEMBER 1999 D D D D D D D D D D D D D PW PACKAGE (TOP VIEW) Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible Operating Frequency 50 MHz to 175 MHz Static Phase Error Distribution at 66MHz to 166 MHz is ±125 ps Jitter (cyc – cyc) at 66 MHz to 166 MHz Is |70| ps Advanced Deep Sub-Micron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Ten Outputs External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input 25-Ω On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3 V AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC G FBOUT 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 CLK AVCC VCC 1Y9 1Y8 GND GND 1Y7 1Y6 1Y5 VCC FBIN description The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCVF2510 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDCVF2510 is characterized for operation from 0°C to 85°C. For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638 – DECEMBER 1999 FUNCTION TABLE OUTPUTS INPUTS G CLK 1Y (0:9) X L L L L H L H H H H H FBOUT functional block diagram G 11 3 4 5 8 9 15 16 CLK 24 ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ 17 PLL FBIN AVCC 13 20 21 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 23 12 AVAILABLE OPTIONS PACKAGE 2 1Y0 TA SMALL OUTLINE (PW) 0°C to 85°C CDCVF2510PWR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FBOUT CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638 – DECEMBER 1999 Terminal Functions TERMINAL NAME NO. TYPE DESCRIPTION CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CDCVF2510 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 13 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. G 11 I Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same frequency as CLK. FBOUT 12 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25-Ω series-damping resistor. 1Y (0:9) 3, 4, 5, 8, 9, 15, 16, 17, 20, 21 O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via the G input. These outputs can be disabled to a logic-low state by deasserting the G control input. Each output has an integrated 25-Ω series-damping resistor. AVCC 23 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VCC GND 2, 10, 14, 22 Power Power supply 6, 7, 18, 19 Ground Ground POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638 – DECEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, AVCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVCC < VCC +0.7 V Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.3 V Input voltage range, VI (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any output in the high or low state, VO (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. AVCC must not exceed VCC + 0.7 V. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 4.6 V maximum. 4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. DISSIPATION RATING TABLE PACKAGE PW BOARD TYPE† RθJA TA ≤ 25°C POWER RATNG DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING JEDEC low-K 114.5°C/W 920 mW 8.7 mW/°C 520 mW 390 mW 960 mW 720 mW JEDEC high-K 62.1°C/W 1690 mW 16.1 mW/°C † JECEC high-K board has better thermal performance due to multiple internal copper planes. ‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). recommended operating conditions (see Note 5) VCC, AVCC Supply voltage VIH High-level input voltage VIL VI Low-level input voltage IOH IOL MIN MAX 3 3.6 2 UNIT V V 0.8 V V High-level output current VCC –12 mA Low-level output current 12 mA 85 °C Input voltage 0 TA Operating free-air temperature NOTE 5: Unused inputs must be held high or low to prevent them from floating. 0 timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN fclk Clock frequency Input clock duty cycle Stabilization time† MAX UNIT 50 175 MHz 40% 60% 1 ms † Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638 – DECEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input clamp voltage II = –18 mA IOH = –100 µA VOH High-level output voltage IOH = –12 mA IOH = – 6 mA VOL Low-level output voltage IOL = 100 µA IOL = 12 mA VCC, AVCC 3V MIN MIN to MAX 3V VCC–0.2 2.1 3V 2.4 High-level output current 0.8 3V 0.55 VO = 1.95 V VO = 1.65 V 3V II Input current VO = 0.4 V VI = VCC or GND ICC§ Supply current (static, output not switching) VI = VCC or GND, Outputs: low or high ∆ICC Change in supply current One input at VCC – 0.6 V, Other inputs at VCC or GND Ci Input capacitance 3.3 V IO = 0, V –28 mA –36 3.6 V Low-level output current V 0.2 3.3 V IOL UNIT –1.2 3V 3V VO = 1.65 V VO = 3.135 V MAX V MIN to MAX IOL = 6 mA VO = 1 V IOH TYP‡ –8 30 mA 40 3.6 V 10 3.6 V ±5 µA 0 V, 3.6 V 40 µA 3.3 V to 3.6 V 500 µA VI = VCC or GND VO = VCC or GND 2.5 pF Co Output capacitance 3.3 V 2.8 ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § For dynamic ICC vs Frequency, refer to Figures 8 and 9. pF POST OFFICE BOX 655303 3.3 V • DALLAS, TEXAS 75265 5 CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638 – DECEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Note 6 and Figures 1 and 2)‡ PARAMETER tsk(o) Phase error time – static (normalized) (see Figures 3 – 6) Output skew time§ Phase error time – jitter (see Note 7) Jitter(cycle (cycle-cycle) cycle) (see Figure 7) Duty cycle tr tf Rise time Fall time FROM (INPUT)/CONDITION TO (OUTPUT) CLK↑ = 66 MHz to166 MHz FBIN↑ Any Y Any Y CLK = 66 MHz to 166 MHz Any Y or FBOUT VCC, AVCC = 3.3 V ± 0.3 V MIN TYP –125 –50 UNIT MAX 125 ps 100 ps 50 ps Any Y or FBOUT |70| CLK = 100 MHz to 166 MHz Any Y or FBOUT |65| f(CLK) > 60 MHz VO = 0.4 V to 2 V VO = 0.4 V to 2 V Any Y or FBOUT 45% 55% Any Y or FBOUT 0.5 2.5 ns/V Any Y or FBOUT 0.5 2.5 ns/V ps tPLH(bypass mode) Low-to-high propagation delay time, bypass mode CLK Any Y or FBOUT 0.4 2.3 ns tPHL(bypass mode) High-to-low propagation delay time, bypass mode CLK Any Y or FBOUT 0.4 2.3 ns ‡ These parameters are not production tested. § The tsk(o) specification is only valid for equal loading of all outputs. NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 7. Calculated per PC DRAM SPEC (tphase error, static – jitter(cycle-to-cycle)). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638 – DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION 3V Input 50% VCC 0V tpd From Output Under Test 500 25 pF W Output 2V 0.4 V tr LOAD CIRCUIT FOR OUTPUTS 50% VCC VOH 2V 0.4 V VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns. C. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms CLKIN FBIN tphase error FBOUT Any Y tsk(o) Any Y Any Y tsk(o) Figure 2. Phase Error and Skew Calculations POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638 – DECEMBER 1999 TYPICAL CHARACTERISTICS STATIC PHASE ERROR vs LOAD CAPACITANCE STATIC PHASE ERROR vs LOAD CAPACITANCE 600 200 VCC = 3.3 V fc = 133 MHz C(LY1–n) = 25 pF || 500 Ω TA = 25°C See Notes A, B, and C 400 Static Phase Error – ps 400 Static Phase Error – ps 600 VCC = 3.3 V fc = 100 MHz C(LY1–n) = 25 pF || 500 Ω TA = 25°C See Notes A, B, and C CLK to Y1–n 0 –200 200 CLK to Y1–n 0 –200 CLK to FBOUT CLK to FBOUT –400 –400 –600 –600 3 8 13 18 23 28 33 3 38 C(LF) – Lumped Feedback Capacitance at FBIN – pF 8 23 28 33 38 Figure 4 STATIC PHASE ERROR vs SUPPLY VOLTAGE AT FBOUT STATIC PHASE ERROR vs CLOCK FREQUENCY 0 0 fc = 133 MHz C(LY) = 25 pF || 500 Ω C(LF) = 12 pF || 500 Ω TA = 25°C See Notes A, B, and C –100 –150 CLK to FBOUT –200 –250 –100 –150 –250 –300 –350 –350 –400 3.1 3.2 3.3 3.4 3.5 –400 3.6 CLK to FBOUT –200 –300 3 VCC = 3.3 V C(LY) = 25 pF || 500 Ω C(LF) = 12 pF || 500 Ω TA = 25°C See Notes A, B, and C –50 Static Phase Error – ps –50 Static Phase Error – ps 18 C(LF) – Lumped Feedback Capacitance at FBIN – pF Figure 3 50 VCC – Supply Voltage – V 75 100 125 Figure 6 NOTES: A. Trace length FBOUT to FBIN = 5 mm, ZO = 50 Ω B. C(LY) = Lumped capacitive load Y1–n C. C(LFx) = Lumped feedback capacitance at FBOUT = FBIN POST OFFICE BOX 655303 150 fc – Clock Frequency – MHz Figure 5 8 13 • DALLAS, TEXAS 75265 175 200 CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638 – DECEMBER 1999 TYPICAL CHARACTERISTICS JITTER vs CLOCK FREQUENCY AT FBOUT ANALOG SUPPLY CURRENT vs CLOCK FREQUENCY 140 25 120 AI CC – Analog Supply Current – mA VCC = 3.3 V C(LY) = 25 pF || 500 Ω C(LF) = 12 pF || 500 Ω TA = 25°C See Notes C and D Jitter – ps 100 80 60 Cycle to Cycle 40 20 0 50 75 100 125 150 175 AVCC = VCC = 3.6 V Bias = 0/3 V C(LY) = 25 pF || 500 Ω C(LF) = 12 pF || 500 Ω TA = 25°C See Notes A and B 20 15 10 5 0 200 0 25 fc – Clock Frequency – MHz 50 75 100 125 150 175 200 fc – Clock Frequency – MHz Figure 7 Figure 8 SUPPLY CURRENT vs CLOCK FREQUENCY 250 AVCC = VCC = 3.6 V Bias = 0/3 V C(LY) = 25 pF || 500 Ω C(LF) = 12 pF || 500 Ω TA = 25°C See Notes A and B I CC – Supply Current – mA 200 150 100 50 0 0 25 50 75 100 125 150 175 200 fc – Clock Frequency – MHz Figure 9 NOTES: A. B. C. D. Trace length FBOUT to FBIN = 5 mm, ZO = 50 Ω Total current = ICC + AICC C(LY) = Lumped capacitive load Y1–n C(LFx) = Lumped feedback capacitance at FBOUT = FBIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638 – DECEMBER 1999 MECHANICAL INFORMATION PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° 0,75 0,50 A Seating Plane 1,20 MAX 0,10 0,05 MIN PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B. C. D. 10 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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