TI SN74AHC1GU04

SCLS343Q− APRIL 1996 − REVISED JUNE 2005
D Operating Range 2-V to 5.5-V VCC
D Unbuffered Output
D Latch-Up Performance Exceeds 250 mA Per
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
JESD 17
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
NC
NC
1
A
2
GND
3
5
4
1
DRL PACKAGE
(TOP VIEW)
VCC
5
VCC
A
2
GND
3
Y
4
NC
1
A
2
GND
3
5
VCC
4
Y
Y
NC – No internal connection
See mechanical drawings for dimensions.
description/ordering information
The SN74AHC1GU04 contains a single inverter gate. The device performs the Boolean function Y = A. Internal
circuitry consists of a single-stage inverter that can be used in analog applications, such as crystal oscillators.
ORDERING INFORMATION
SOT (SOT-23) − DBV
−40°C
−40
C to 85
85°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOT (SC-70) − DCK
SOT (SOT-553) − DRL
Reel of 3000
SN74AHC1GU04DBVR
Reel of 250
SN74AHC1GU04DBVT
Reel of 3000
SN74AHC1GU04DCKR
Reel of 250
SN74AHC1GU04DCKT
Reel of 4000
SN74AHC1GU04DRLR
TOP-SIDE
MARKING‡
AU4_
AD_
AD_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
‡ The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram (positive logic)
A
2
4
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2005, Texas Instruments Incorporated
! "#$ %!&
% "! "! '! ! !( !
%% )*& % "!+ %! !!$* $%!
!+ $$ "!!&
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS343Q− APRIL 1996 − REVISED JUNE 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
DRL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
VIL
VI
VO
IOH
Supply voltage
High-level input voltage
MAX
2
5.5
VCC = 2 V
VCC = 3 V
1.7
VCC = 5.5 V
VCC = 2 V
4.4
2.4
Low-level input voltage
Input voltage
Output voltage
VCC = 2 V
VCC = 3.3 V ± 0.3 V
High-level output current
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
Low-level output current
UNIT
V
V
0.3
VCC = 3 V
VCC = 5.5 V
VCC = 5 V ± 0.5 V
VCC = 2 V
IOL
MIN
0.6
V
1.1
0
5.5
V
0
VCC
−50
mA
V
−4
−8
50
mA
mA
4
8
mA
TA
Operating free-air temperature
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS343Q− APRIL 1996 − REVISED JUNE 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −50 mA
VCC
MIN
TA = 25°C
TYP
MAX
MIN
2V
1.8
2
1.8
3V
2.7
3
2.7
4
4.5
4
4.5 V
VOH
IOH = −4 mA
3V
2.58
IOH = −8 mA
4.5 V
3.94
IOL = 50 mA
VOL
IOL = 4 mA
IOL = 8 mA
II
ICC
VI = 5.5 V or GND
VI = VCC or GND,
Ci
VI = VCC or GND
IO = 0
MAX
UNIT
V
2.48
3.8
2V
0.2
0.2
3V
0.3
0.3
4.5 V
0.5
0.5
3V
0.36
0.44
4.5 V
0.36
0.44
0 V to 5.5 V
±0.1
±1
mA
1
10
mA
10
10
pF
5.5 V
5V
2
V
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
OUTPUT
CAPACITANCE
tPLH
tPHL
A
Y
CL = 15 pF
tPLH
tPHL
A
Y
CL = 50 pF
MIN
TA = 25°C
TYP
MAX
MIN
MAX
5
7.1
1
8.5
5
7.1
1
8.5
7.5
10.6
1
12
7.5
10.6
1
12
UNIT
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
OUTPUT
CAPACITANCE
tPLH
tPHL
A
Y
CL = 15 pF
tPLH
tPHL
A
Y
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
MIN
MAX
3.5
5.5
1
6
3.5
5.5
1
6
5
7
1
8
5
7
1
8
UNIT
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
UNIT
7.3
pF
3
SCLS343Q− APRIL 1996 − REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
VCC
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
0V
tPZL
50% VCC
tPLZ
≈VCC
50% VCC
tPZH
tPLH
VOH
50% VCC
VOL
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74AHC1GU04DBVRE4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AHC1GU04DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AHC1GU04DBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AHC1GU04DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AHC1GU04DCKRE4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AHC1GU04DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AHC1GU04DCKTE4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AHC1GU04DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AHC1GU04DRLRG4
ACTIVE
SOT
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC1GU04DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC1GU04DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC1GU04DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC1GU04DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC1GU04DRLR
ACTIVE
SOT
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2007
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AHC1GU04DBVR
DBV
5
SITE 34
180
9
3.23
3.17
1.37
4
8
Q3
SN74AHC1GU04DBVR
DBV
5
SITE 45
0
0
3.23
3.17
1.37
4
8
Q3
SN74AHC1GU04DBVT
DBV
5
SITE 34
180
9
3.23
3.17
1.37
4
8
Q3
SN74AHC1GU04DBVT
DBV
5
SITE 45
330
16
10.6
15.8
4.9
16
24
Q3
SN74AHC1GU04DCKR
DCK
5
SITE 34
180
9
2.24
2.34
1.22
4
8
Q3
SN74AHC1GU04DCKT
DCK
5
SITE 34
180
9
2.24
2.34
1.22
4
8
Q3
SN74AHC1GU04DRLR
DRL
5
SITE 35
180
9
1.78
1.78
0.69
4
8
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
SN74AHC1GU04DBVR
DBV
5
SITE 34
205.0
200.0
33.0
SN74AHC1GU04DBVR
DBV
5
SITE 45
0.0
185.0
220.0
SN74AHC1GU04DBVT
DBV
5
SITE 34
201.0
192.0
26.0
SN74AHC1GU04DBVT
DBV
5
SITE 45
0.0
0.0
0.0
SN74AHC1GU04DCKR
DCK
5
SITE 34
205.0
200.0
33.0
SN74AHC1GU04DCKT
DCK
5
SITE 34
201.0
192.0
26.0
SN74AHC1GU04DRLR
DRL
5
SITE 35
202.0
201.0
28.0
Pack Materials-Page 2
Height (mm)
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