RFM RX5500

RX5500
®
· Designed for Short-Range Wireless Control Applications
· 3 V, Low Current Operation plus Sleep Mode
· Characterized for Automotive Applications
· High EMI Rejection Capability
The RX5500 hybrid receiver is ideal for short-range wireless control applications where robust
operation, small size, low power consumption and low cost are required. The RX5500 employs
RFM’s amplifier-sequenced hybrid (ASH) architecture to achieve this unique blend of characteristics. All critical RF functions are contained in the hybrid, simplifying and speeding design-in.
The RX5500 is sensitive and stable. A wide dynamic range log detector provides robust performance in the presence of on-channel interference or noise. Two stages of SAW filtering provide
excellent receiver out-of-band rejection. The RX5500 generates virtually no RF emissions, facilitating compliance with ETSI I-ETS 300 220 and similar regulations.
433.92 MHz
Hybrid
Receiver
Absolute Maximum Ratings
Rating
Value
Power Supply and All Input/Output Pins
Units
-0.3 to +4.0
Non-Operating Case Temperature
V
-50 to +100
o
C
250
o
C
Soldering Temperature (10 seconds)
Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 oC)
Characteristic
Sym
Operating Frequency
Notes
Minimum
Typical
433.72
fO
Modulation Type
Maximum
Units
434.12
MHz
19.2
kbps
OOK/ASK
Data Rate
Receiver Performance, High Sensitivity Mode
Sensitivity, 1.2 kbps, 10-3 BER, AM Test Method
1
-110.5
dBm
Sensitivity, 1.2 kbps, 10-3 BER, Pulse Test Method
1
-104.5
dBm
Current, 1.2 kbps (RPR = 330 K)
2
2.9
mA
Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method
1
-109
dBm
Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method
1
-103
dBm
Current, 2.4 kbps (RPR = 330 K)
2
3.0
mA
Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method
1
-105
dBm
Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method
1
-99
dBm
3.1
mA
Current, 19.2 kbps
Receiver Performance, Low Current Mode
Sensitivity, 1.2 kbps, 10-3 BER, AM Test Method
1
-104
dBm
Sensitivity, 1.2 kbps, 10-3 BER, Pulse Test Method
1
-98
dBm
Current, 1.2 kbps (RPR = 2000 K)
2
1.65
mA
1
Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 oC)
Sym
Notes
Receiver Out-of-Band Rejection, ±5% fO
Characteristic
R±5%
3
80
dB
Receiver Ultimate Rejection
RULT
3
100
dB
Sleep Mode Current
Minimum
Typical
0.7
IS
Power Supply Voltage Range
Maximum
µA
2.2
VCC
Power Supply Voltage Ripple
Ambient Operating Temperature
TA
Units
-40
3.7
Vdc
10
mVP-P
85
o
C
Notes:
1. Typical sensitivity data is based on a 10-3 bit error rate (BER), using DC-balanced data. There are two test methods commonly used to
measure OOK/ASK receiver sensitivity, the “100% AM” test method and the “Pulse” test method. Sensitivity data is given for both test methods. See Appendix 3.8 in the ASH Transceiver Designer’s Guide for the details of each test method, and for sensitivity curves for a 2.2 to
3.7 V supply voltage range at five operating temperatures. The application/test circuit and component values are shown on the next page and
in the Designer’s Guide.
2. At low data rates it is possible to adjust the ASH pulse generator to trade-off some receiver sensitivity for lower operating current. Sensitivity data and receiver current are given at 1.2 kbps for both high sensitivity operation (RPR = 330 K) and low current operation (RPR = 2000 K).
3. Data is given with the ASH radio matched to a 50 ohm load. Matching component values are given on the next page.
4. See Table 1 on Page 8 for additional information on ASH radio event timing.
A S H T r a n s c e iv e r P in O u t
S M -2 0 L P a c k a g e D r a w in g
0 .3 8 "
(9 .6 5 )
0 .0 8 "
(2 .0 3 )
1
0 .0 2 "
(0 .5 1 )
0 .0 7 5 "
(1 .9 0 )
G N D 3
3
1 8
C N T R L 0
P K D E T
4
1 7
C N T R L 1
B B O U T
5
1 6
V C C 2
C M P IN
6
1 5
P W ID T H
R X D A T A
7
1 4
P R A T E
1 3
T H L D 1
1 2
T H L D 2
L P F A D J
8
9
1 0
G N D 2
2
1 9
A G C C A P
T X M O D
0 .1 3 "
(3 .3 0 )
2 0
2
V C C 1
0 .0 4 "
(1 .0 2 )
0 .4 3 "
(1 0 .9 )
R F IO
G N D 1
0 .1 2 5 "
(3 .2 0 )
1 1
R R E F
A S H R e c e iv e r A p p lic a tio n C ir c u it
O O K C o n fig u r a tio n
+ 3
V D C
C
D C B
+
R /S
1 9
L
G N D
3
R F IO
A T
2 0
L
E S D
1 8
R
1 7
C N T
R L 0
1 6
P W
C N T
R L 1
V C C
2
R
R
T H 1
P R
1 5
1 4
1 3
P
W ID T H
P
R A T E
T H L D
1
1 2
N C
R R E F
1 1
T O P V IE W
1
G N D 1
V C C
1
2
R F
A 1
P K
D E T
B B
O U T
4
5
3
R
+ 3
V D C
C
C M P
IN
6
7
N C
8
R F B 1
C
R
R E F
1 0
9
R
B B O
C
R X
D A T A
G N D 2
L P F
A D J
L P F
B B O
L P F
D a ta O u tp u t
Receiver Set-Up, 3.0 Vdc, -40 to +85 0C
Item
Symbol
OOK
Nominal NRZ Data Rate
DRNOM
1.2
Minimum Signal Pulse
SPMIN
833.33
Maximum Signal Pulse
OOK
OOK
Units
Notes
2.4
19.2
kbps
see pages 1 & 2
416.67
52.08
µs
single bit
SPMAX
3333.33
1666.68
208.32
µs
4 bits of same value
BBOUT Capacitor
CBBO
0.2
0.1
0.015
µF
±10% ceramic
BBOUT Resistor
RBBO
12
12
0
K
±5%
LPFAUX Capacitor
CLPF
0.01
0.0047
-
µF
±5%
LPFADJ Resistor
RLPF
330
300
100
K
±5%
RREF Resistor
RREF
100
100
100
K
±1%
THLD1 Resistor
RTH1
0
0
0
K
±1%, typical values
PRATE Resistor
RPR
330
330
330
K
±5%
PWIDTH Resistor
RPW
270 to GND
270 to GND
270 to GND
K
±5%
DC Bypass Capacitor
CDCB
4.7
4.7
4.7
µF
tantalum
RF Bypass Capacitor 1
CRFB1
100
100
100
pF
±5% NPO
Antenna Tuning Inductor
LAT
56
56
56
nH
50 ohm antenna
Shunt Tuning/ESD Inductor
LESD
220
220
220
nH
50 ohm antenna
CAUTION: Electrostatic Sensitive Device. Observe precautions when handling.
3
ASH Receiver Theory of Operation
that the two amplifiers are coupled by a surface acoustic wave
(SAW) delay line, which has a typical delay of 0.5 µs.
An incoming RF signal is first filtered by a narrow-band SAW filter,
and is then applied to RFA1. The pulse generator turns RFA1 ON
for 0.5 µs. The amplified signal from RFA1 emerges from the SAW
delay line at the input to RFA2. RFA1 is now switched OFF and
RFA2 is switched ON for 0.55 µs, amplifying the RF signal further.
The ON time for RFA2 is usually set at 1.1 times the ON time for
RFA1, as the filtering effect of the SAW delay line stretches the signal pulse from RFA1 somewhat. As shown in the timing diagram,
RFA1 and RFA2 are never on at the same time, assuring excellent
receiver stability. Note that the narrow-band SAW filter eliminates
sampling sideband responses outside of the receiver passband, and
the SAW filter and delay line act together to provide very high receiver ultimate rejection.
Introduction
RFM’s RX5500 amplifier-sequenced hybrid (ASH) receivers are
specifically designed for short-range wireless control and data communication applications. The receivers provide robust operation,
very small size, low power consumption and low implementation
cost. All critical RF functions are contained in the hybrid, simplifying
and speeding design-in. The ASH receiver can be readily configured
to support a wide range of data rates and protocol requirements.
The receiver features virtually no RF emissions, making it easy to
certify to short-range (unlicensed) radio regulations.
Amplifier-Sequenced Receiver Operation
The ASH receiver’s unique feature set is made possible by its system architecture. The heart of the receiver is the amplifiersequenced receiver section, which provides more than 100 dB of
stable RF and detector gain without any special shielding or decoupling provisions. Stability is achieved by distributing the total RF
gain over time. This is in contrast to a superheterodyne receiver,
which achieves stability by distributing total RF gain over multiple
frequencies.
Amplifier-sequenced receiver operation has several interesting characteristics that can be exploited in system design. The RF amplifiers
in an amplifier-sequenced receiver can be turned on and off almost
instantly, allowing for very quick power-down (sleep) and wake-up
times. Also, both RF amplifiers can be off between ON sequences
to trade-off receiver noise figure for lower average current consumption. The effect on noise figure can be modeled as if RFA1 is on
continuously, with an attenuator placed in front of it with a loss
equivalent to 10*log10(RFA1 duty factor), where the duty factor is the
average amount of time RFA1 is ON (up to 50%). Since an
amplifier-sequenced receiver is inherently a sampling receiver, the
overall cycle time between the start of one RFA1 ON sequence and
Figure 1 shows the basic block diagram and timing cycle for an amplifier-sequenced receiver. Note that the bias to RF amplifiers RFA1
and RFA2 are independently controlled by a pulse generator, and
A S H R e c e iv e r B lo c k D ia g r a m
& T im in g C y c le
A n te n n a
S A W
F ilte r
S A W
D e la y L in e
R F A 1
P 1
P 2
P u ls e
G e n e ra to r
R F In p u t
R F D a ta P u ls e
tP
W 1
tP
P 1
tP
R I
R C
R F A 1 O u t
D e la y L in e
O u t
tP
R F A 2
W 2
P 2
Figure 1
4
D e te c to r &
L o w -P a s s
F ilte r
D a ta
O u t
R X 5 5 0 0 S e r ie s A S H R e c e iv e r B lo c k D ia g r a m
R F A 1
C N T R L 1
C N T R L 0
1 8
1 7
V C C
V C C
G N D
G N D
G N D
N C :
R R E
C M P
N C :
N C :
P o w e r
D o w n
C o n tro l
B ia s C o n tr o l
A n te n n a
1 :
P in
P in
P in
P in
P in
P in
F : P in
IN : P in
P in
P in
2 :
1 :
2 :
3 :
2
1 6
1
1 0
1 9
8
1 1
6
4
1 2
L o g
B B O U T
3
R F IO
E S D
C h o k e
2 0
S A W
C R F ilte r
S A W
D e la y L in e
R F A 1
R F A 2
D e te c to r
L o w -P a s s
F ilte r
L P F A D J
9
R
B B
5
C
6
7
D S 1
B B O
R e f
R X D A T A
T h ld
L P F
T h r e s h o ld
C o n tro l
T H L D 1 1 3
1 1 R R E F
R
R
P u ls e G e n e r a to r
& R F A m p B ia s
P R A T E
1 5
1 4
R
P R
T H 1
R E F
P W ID T H
R
P W
Figure 2
the start of the next RFA1 ON sequence should be set to sample
the narrowest RF data pulse at least 10 times. Otherwise, significant
edge jitter will be added to the detected data pulse.
The filter is followed by a base-band amplifier which boosts the detected signal to the BBOUT pin. When the receiver RF amplifiers
are operating at a 50%-50% duty cycle, the BBOUT signal changes
about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV.
For lower duty cycles, the mV/dB slope and peak-to-peak signal
level are proportionately less. The detected signal is riding on a
1.1 Vdc level that varies somewhat with supply voltage, temperature, etc. BBOUT is coupled to the CMPIN pin or to an external data
recovery process (DSP, etc.) by a series capacitor. The correct
value of the series capacitor depends on data rate, data run length,
and other factors as discussed in the ASH Transceiver Designer’s
Guide.
RX5500 Series ASH Receiver Block Diagram
Figure 2 is the general block diagram of the RX5500 series ASH
receiver. Please refer to Figure 2 for the following discussions.
Antenna Port
The only external RF components needed for the receiver are the
antenna and its matching components. Antennas presenting an impedance in the range of 35 to 72 ohms resistive can be satisfactorily
matched to the RFIO pin with a series matching coil and a shunt
matching/ESD protection coil. Other antenna impedances can be
matched using two or three components. For some impedances,
two inductors and a capacitor will be required. A DC path from RFIO
to ground is required for ESD protection.
When the receiver is placed in the power-down (sleep) mode, the
output impedance of BBOUT becomes very high. This feature helps
preserve the charge on the coupling capacitor to minimize data
slicer stabilization time when the receiver switches out of the sleep
mode.
Receiver Chain
Data Slicers
The output of the SAW filter drives amplifier RFA1. The output of
RFA1 drives the SAW delay line, which has a nominal delay of 0.5
µs.
The second amplifier, RFA2, provides 51 dB of gain below saturation. The output of RFA2 drives a full-wave detector with 19 dB of
threshold gain. The onset of saturation in each section of RFA2 is
detected and summed to provide a logarithmic response. This is
added to the output of the full-wave detector to produce an overall
detector response that is square law for low signal levels, and transitions into a log response for high signal levels. This combination
provides excellent threshold sensitivity and more than 70 dB of
The CMPIN pin drives data slicer DS1, which convert the analog
signal from BBOUT back into a digital stream. Data slicer DS1 is a
capacitively-coupled comparator with provisions for an adjustable
threshold. The threshold, or squelch, offsets the comparator’s slicing
level from 0 to 90 mV, and is set with a resistor between the RREF
and THLD1 pins. This threshold allows a trade-off between receiver
sensitivity and output noise density in the no-signal condition. For
best sensitivity, the threshold is set to 0. In this case, noise is output
continuously when no signal is present. This, in turn, requires the
circuit being driven by the RXDATA pin to be able to process noise
(and signals) continuously.
The detector output drives a gyrator filter. The filter provides a
three-pole, 0.05 degree equiripple low-pass response with excellent
group delay flatness and minimal pulse ringing. The 3 dB bandwidth
of the filter can be set from 4.5 kHz to 1.8 MHz with an external resistor.
This can be a problem if RXDATA is driving a circuit that must
“sleep” when data is not present to conserve power, or when it its
necessary to minimize false interrupts to a multitasking processor.
In this case, noise can be greatly reduced by increasing the threshold level, but at the expense of sensitivity. The best 3 dB bandwidth
5
for the low-pass filter is also affected by the threshold level setting of
DS1. The bandwidth must be increased as the threshold is increased to minimize data pulse-width variations with signal amplitude.
tPR = 15 ms + 3*tBBC
Sleep and Wake-Up Timing
The maximum transition time from the receive mode to the
power-down (sleep) mode tRS is 10 µs after CNTRL1 and CNTRL0
are both low (1 µs fall time).
Receiver Pulse Generator and RF Amplifier Bias
The receiver amplifier-sequence operation is controlled by the Pulse
Generator & RF Amplifier Bias module, which in turn is controlled by
the PRATE and PWIDTH input pins, and the Power Down (sleep)
Control Signal from the Bias Control function.
The maximum transition time tSR from the sleep mode to the receive
mode is 3*tBBC, where tBBC is the BBOUT-CMPIN coupling-capacitor
time constant. When the operating temperature is limited to 60 oC,
the time required to switch from sleep to receive is dramatically less
for short sleep times, as less charge leaks away from the BBOUTCMPIN coupling capacitor.
In the low data rate mode, the interval between the falling edge of
one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse
tPRI is set by a resistor between the PRATE pin and ground. The interval can be adjusted between 0.1 and 5 µs. In the high data rate
mode (selected at the PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50% duty cycle. In this case, the start-to-start
period tPRC for ON pulses to RFA1 are controlled by the PRATE resistor over a range of 0.1 to 1.1 µs.
Pulse Generator Timing
In the low data rate mode, the interval tPRI between the falling edge
of an ON pulse to the first RF amplifier and the rising edge of the
next ON pulse to the first RF amplifier is set by a resistor RPR between the PRATE pin and ground. The interval can be adjusted between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K.
The value of the RPR is given by:
In the low data rate mode, the PWIDTH pin sets the width of the ON
pulse tPW1 to RFA1 with a resistor to ground (the ON pulse width
tPW2 to RFA2 is set at 1.1 times the pulse width to RFA1 in the low
data rate mode). The ON pulse width tPW1 can be adjusted between
0.55 and 1 µs. However, when the PWIDTH pin is connected to Vcc
through a 1 M resistor, the RF amplifiers operate at a nominal
50%-50% duty cycle, facilitating high data rate operation. In this
case, the RF amplifiers are controlled by the PRATE resistor as described above.
RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms
In the high data rate mode (selected at the PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50% duty cycle. In
this case, the period tPRC from the start of an ON pulse to the first
RF amplifier to the start of the next ON pulse to the first RF amplifier
is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K to 220 K. In this case RPR is given by:
Both receiver RF amplifiers are turned off by the Power Down Control Signal, which is invoked in the sleep mode.
RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms
In the low data rate mode, the PWIDTH pin sets the width of the ON
pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the
ON pulse width to the second RF amplifier tPW2 is set at 1.1 times
the pulse width to the first RF amplifier in the low data rate mode).
The ON pulse width tPW1 can be adjusted between 0.55 and 1 µs
with a resistor value in the range of 200 K to 390 K. The value of
RPW is given by:
Receiver Mode Control
The receiver operating modes – receive and power-down (sleep),
are controlled by the Bias Control function, and are selected with the
CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and CNTRL0
both high place the unit in the receive mode. Setting CNTRL1 and
CNTRL0 both low place the unit in the power-down (sleep) mode.
CNTRL1 and CNTRL0 are CMOS compatible inputs. These inputs
must be held at a logic level; they cannot be left unconnected.
RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms
Receiver event timing is summarized in Table 1. Please refer to this
table for the following discussions.
However, when the PWIDTH pin is connected to Vcc through a 1 M
resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifiers are controlled by the PRATE resistor as described above.
Turn-On Timing
LPF Group Delay
The maximum time tPR required for the receive function to become
operational at turn on is influenced by two factors. All receiver circuitry will be operational 5 ms after the supply voltage reaches
2.2 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC stabilized in 3 time constants (3*tBBC). The total turn-on time to stable receiver operation for a 10 ms power supply rise time is:
The low-pass filter group delay is a function of the filter 3 dB bandwidth, which is set by a resistor RLPF to ground at the LPFADJ pin.
The minimum 3 dB bandwidth fLPF = 1445/RLPF, where fLPF is in kHz,
and RLPF is in kilohms.
Receiver Event Timing
The maximum group delay tFGD = 1750/fLPF = 1.21*RLPF, where tFGD
is in µs, fLPF in kHz, and RLPF in kilohms.
6
tRS
tPRI
tPW1
tPW2
tPRC
tPWH
tFGD
fLPF
tBBC
RX to Sleep
PRATE Interval
PWIDTH RFA1
PWIDTH RFA2
PRATE Cycle
PWIDTH High (RFA1 & RFA2)
LPF Group Delay
LPF 3 dB Bandwidth
BBOUT-CMPIN Time Constant
range
range
range
max
min
min
1.1*tPW1
0.05 to 0.55 µs
1750/fLPF
1445/RLPF
0.064*CBBO
range
0.55 to 1 µs
0.1 to 1.1 µs
max
range
10 µs
Table 1
max
3*tBBC
tSR
0.1 to 5 µs
max
Sleep to RX
Min/Max
Time
3*tBBC + 15 ms
tPR
Symbol
Turn On to Receive
Event
Receiver Event Timing, 3.0 Vdc, -40 to +85 0C
Test Conditions
tBBC in µs, CBBO in pF
fLPF in kHz, RLPF in kilohms
tFGD in µs, fLPF in kHz
high data rate mode
high data rate mode
low data rate mode
low data rate mode
low data rate mode
1µs CNTRL0/CNTROL1 fall times
1µs CNTRL0/CNTROL1 rise times
10 ms supply voltage rise time
Notes
user selected
user selected
user selected
user selected mode
user selected mode
user selected mode
user selected mode
user selected mode
time until receiver is in power-down mode
time until receiver operational
time until receiver operational
Pin Descriptions
Pin
Name
Description
1
GND1
GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces.
2
VCC1
VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF
capacitor, which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information.
3
RFA1
RFA1 enables the high gain mode of the first RF amplifier. This pin is normally connected to VCC1.
4
NC
This pin should be left unconnected.
BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor CBBO for
internal data slicer operation. The time constant tBBC for this connection is:
tBBC = 0.064*CBBO , where tBBC is in µs and CBBO is in pF
5
BBOUT
6
CMPIN
7
RXDATA
8
NC
A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between tBBC
and 1.8*tBBC with variations in supply voltage, temperature, etc. The optimum time constant in a given circumstance will depend on the data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. A common criteria is to set the time constant for no more than a 20% voltage droop during SPMAX.
For this case:
CBBO = 70*SPMAX, where SPMAX is the maximum signal pulse width in µs and CBBO is in pF
The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output impedance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the
BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles,
the mV/dB slope and peak-to-peak signal level are proportionately less. The signal at BBOUT is riding on a
1.1 Vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recommended. When an external data recovery process is used with AGC, BBOUT must be coupled to the external
data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by
the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the output impedance of this pin
becomes very high, preserving the charge on the coupling capacitor.
This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input
impedance of this pin is 70 K to 100 K.
RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available
from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin
becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite
logic state when this pin is high impedance. If a pull-up resistor is used, the positive supply end should be connected to a voltage no greater than Vcc + 200 mV.
This pin may be left unconnected or may be grounded.
This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor RLPF between this
pin and ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth fLPF from
4.5 kHz to 1.8 MHz. The resistor value is determined by:
RLPF = 1445/ fLPF, where RLPF is in kilohms, and fLPF is in kHz
9
LPFADJ
10
GND2
GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
11
RREF
RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground.
A ±1% resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and
this node to less than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF
through resistor values less that 1.5 K, their node capacitance must be added to the RREF node capacitance and
the total should not exceed 5 pF.
12
NC
13
THLD1
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between fLPF
and 1.3* fLPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree
equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter
bandwidth setting.
This pin shouild be left unconnected.
The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor RTH1 to RREF. The threshold is increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold.
The acceptable range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is
given by:
RTH1 = 1.11*V, where RTH1 is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD1 resistor.
8
Pin
Name
Description
The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON
pulse to the first RF amplifier tPRI is set by a resistor RPR between this pin and ground. The interval tPRI can be adjusted between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of RPR is given by:
RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms
14
PRATE
A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF
amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period
tPRC from start-to-start of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1
to 1.1 µs using a resistor of 11 K to 220 K. In this case the value of RPR is given by:
RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms
A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for
additional amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and
this pin to less than 5 pF to maintain stability.
The PWIDTH pin sets the width of the ON pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the ON
pulse width to the second RF amplifier tPW2 is set at 1.1 times the pulse width to the first RF amplifier). The ON
pulse width tPW1 can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The
value of RPW is given by:
RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms
15
PWIDTH
16
VCC2
VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capacitor, which may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor.
CNTRL1
CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive
mode. CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a
high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input
voltage of Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV
should not be applied to this pin. A logic high requires a maximum source current of 40 µA. Sleep mode requires a
maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left unconnected.
18
CNTRL0
CNTRL0 is used with CNTRL1 to control the receiver modes. CNTRL0 is a high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is
interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic
high requires a maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin
must be held at a logic level; it cannot be left unconnected.
19
GND3
GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
RFIO
RFIO is the receiver RF input pin. This pin is connected directly to the SAW filter transducer. Antennas presenting
an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series matching coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three
components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to
ground is required for ESD protection.
17
20
A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier
ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance
between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation
with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the
sleep mode.
9
.2 3 7 5
.1 7 2 5
.1 9 7 5
.2 1 2 5
.4 6 0 0
.3 8 2 5
.3 5 7 5
.3 1 7 5
.2 7 7 5
.2 3 7 5
.1 9 7 5
.1 5 7 5
.4 1 0
.2 7 0
.1 4 0
0 .0 0 0
.1 1 7 5
.1 0 2 5
.0 7 7 5
0 .0 0 0
D im e n s io n s in in c h e s
S M -2 0 L P C B P a d L a y o u t
Note: Specifications subject to change without notice.
file: rx5500w.vp, 2003.07.20 rev
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