SA2532
sames
SA2532 A/C/U
VERSATILE SINGLE CHIP TELEPHONE
FEATURES
n Speech circuit, LD/MF Dialler and Tone
Ringer on one 28 pin CMOS chip
n Soft clip to avoid harsh distortion
n Line Loss Compensation selectable by
pin option
n Power down mode
n Versatile applications for different PTT
demands
n 31 digit last number redial
n Sliding Cursor protocol with comparison
n 2 Flash keys, 100 ms and 280 ms (option
600 ms)
n Pause key for 3 sec Auto Pause or Wait
Function
GENERAL DESCRIPTION
The SA2532 is a CMOS integrated circuit that
contains all the functions needed to form a
high performance electronic telephone.
The device incorporates LD/MF dialling,
melody generation, ring frequency discrimination and a high quality speech circuit.
A RAM is on chip for a 31 digit last number
redial. The sliding cursor procedure makes
Last Number Redial easy behind a PABX.
The versatility of the circuit is provided by on
chip programmability and a few external components. This allows easy adaption to different PTT requirements without changing the
PCB of the telephone.
n
n
n
n
n
n
n
Ring frequency discrimination
Operating range from 13 to 100 mA
(down to 5 mA with reduced performance)
Low noise (max. -72dBmp)
Real or Complex impedance on chip programmable
LD/MF switchable dialling
On chip MF filter (CEPT CS 203 compatible)
3-tone melody generator with selectable
repetition rates
PACKAGE
Available in 28 pin DIP and SOIC
LS
1
28
RI
RO2
RO1
LI
V DD
A GND
CS
V SS
M2
M1
STB
CI
MODE
SA2532
MO
FCI
R1
LLC
HS DP
R2
OSC
RR
R3
R4
C4
C3
C1
C2
14
15
DR-00975
1/22
1/22
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4153
PDS039-SA2532-001
Rev. C
23-10-1995
SA2532
PIN DESCRIPTION
Pin#
23
24
3
2
Symbol
M1
M2
RO1
RO2
5
AGND
28
RI
6
STB
1
LS
27
LI
25
CS
4
VDD
26
8
VSS
MO
21
FCI
10
HS/DP
11
OSC
9
LLC
12
RR
22
MODE
20
19
18
17
16
15
14
13
7
R1
R2
R3
R4
C1
C2
C3
C4
CI
2/22
Function
Microphone Inputs
Differential inputs for the microphone (electret).
Receiver Outputs
These are the outputs for driving a dynamic earpiece with an impedance
of 100 to 300Ω
Analog Ground
This is the analog ground for the amplifiers.
Receive Input
This is the input for the receive signal.
Side Tone Balance Input
This is the input for side tone cancellation.
Line Current Sense Input
This is the input for sensing the line current.
Line Input
This input is used for power extraction and line current sensing.
Current Shunt Control Output
This N-channel open drain output controls the external high power shunt
transistor for the modulation of the line voltage and for shorting the line
during make period of pulse dialling.
Positive Voltage Supply
This is the supply pin for the circuit.
Negative Power Supply
Melody Output
Pulse Density Modulated output of the melody generator for tone ringer. At
high impedance when not active.
Frequency Comparator Input
This is a Schmitt trigger input for ring frequency discrimination. Disabled
during off-hook.
Hook Switch Input and Dial Pulse Output
This is an I/O that is pulled high by the hook switch when off- hook. An open
drain pulls it low during break periods of pulse dialling and flash.
Oscillator Input
Oscillator pin for Xtal or ceramic resonator (3.58 MHz).
Line Loss Compensation
Select pin for line loss compensation.
Repetition Rate
Select pin for repetition rate of melody.
Signalling Mode Select Input
Mode pin
Function
High
LD default mode, make/break = 33/66 ms
Open
MF only
Low
LD default mode, make/break = 40/60 ms
Keyboard Rows
Keyboard Columns
Complex Impedance Input
Input pin for the capacitor in the complex impedance
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SA2532
FUNCTIONAL DESCRIPTION
Power On Reset
The on chip power on reset circuit monitors the supply voltage (V DD). When VDD rises above
approx. 1.2V, a power on reset occurs to assure correct start-up and the RAM is cleared.
DC Conditions
The normal operating range is from 13mA to 100 mA. Operating range with reduced
performance is from 5mA to 13mA. In the operating range all functions are operational.
In the line hold range from 0 to 5 mA the device is in a power down mode and the voltage at
LI is reduced to maximum 3.5V.
The dc characteristic (excluding diode bridge and Pulsing transistors) is determined by the
voltage at LI and the resistor R1 as follows:
VLS = VLI + ILine.R1
The voltage at LI is 4.5V.
During pulse dialling the speech circuit and other parts of the device not required are in a
power down mode to save current. The CS pin is pulled to VSS in order to turn the external
shunt transistor on to keep a low voltage drop at the LS pin during make periods.
AC Impedance
The Characteristic or Output impedance of the SA2532 is set within the IC and adjusted by
Mask Options. Available options are for 600Ω and 1000Ω. When the 1000Ω option is selected
then a capacitor may be added to the circuit at pin CI to add a reactive element and make the
output impedance complex.
Oscillator
All the Timing Functions of the SA2532 are based on a Clock Frequency of 3.58MHz. A crystal
or ceramic resonator of this frequency should be connected to the OSC pin. In practise minor
deviations from the nominal frequency may occur due to the characteristics of the frequency
reference device used and so it is recommended that care is taken in the selection of
components.
In some cases a small value capacitor ( ≤47pF) may have to be connected in parallel with the
Frequency Reference to ensure start-up and/or operation at the nominal frequency.
Speech Circuit
The speech circuit consists of a transmit and a receive path with soft clip, mute, line loss
compensation and side tone cancellation.
Transmit
The gain of the transmit path is 35 dB for M1/M2 to LS (see test circuit figure 5). The
microphone input is differential with an input impedance of 25 kΩ.
The soft clip circuit limits the output voltage at LI to 2.0VPEAK. The attack time is 30µs/6dB
and the decay time is 20 ms/6 dB. When mute is active, during dialling or after pressing
the MUTE key, the gain is reduced by > 60 dB.
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3/22
SA2532
Receive
The receive input is the differential signal of RI and STB. The gain of the receive path is
2 dB (test circuit figure 5) with differential outputs, RO1/RO2 (0dB on SA2532C/U). When
mute is active during dialling the gain is reduced by > 60dB. During DTMF dialling a MF
comfort tone is applied to the receiver. The comfort tone is the DTMF signal with a level
that is -30dB relative to the line signal.
Side Tone
Side Tone is controlled along with Return Loss by a Double Balance Bridge as shown in
RETURN LOSS
LINE
SIDE TONE
R1
RI
LI
R2
SYN
R5
E
ZB
A
ZR
L
STB
F
VS S
ONE COMMON GROUND
DR-00708
Fig. 1.
Figure 1
Double balance bridge (return loss and side tone) with one common ground
A good side tone cancellation is achieved by using the following equation:
ZBAL
ZLINE
=
R5
R1
The side tone cancellation signal is applied to the STB input.
Line Loss Compensation
When Line Loss Compensation is active the gain of the Transmit and Receive amplifiers
are changed by 6dB in accord with the DC conditions as measured at Pins LI and LS.
When the LLC Pin is Low this adjustment in gain occurs over the range I LINE = 20 to 50 mA.
When LLC is High the range is 45 to 75mA. Note that these figures apply for R1 = R30Ω.
When the LLC Pin is open the amplifier gains remain fixed regardless of the Line Current.
4/22
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SA2532
Dialling Functions
Valid Keys
The keypad of the SA2532 comprises a maximum of 20 keys (of which 3 have no function).
A Bi-polar scan technique is used so that the 20 keys are scanned in a 4 x 5 matrix using
only 8 pins.
A valid key is detected when one and only one contact closure is detected between a Row
and Column Pin. Key contacts are debounced to avoid incorrect detection.
Dial Mode Selection
The default mode (LD or MF) can be selected by the Mode pin. When default LD mode
is selected, a temporary change to MF can be invoked by pressing the * key. The circuit
will revert to LD by pressing the R (or R2) key or by next on-hook.
When MF mode is selected by the mode pin, the circuit can not be changed temporarily
to LD but will remain in MF.
Last Number Redial
LNR is a facility that allows resignalling of the last manually dialled number without keying
in all the digits again. The LNR is repeatable.
The current contents of the RAM are overwritten by new entries.
A manually entered number is automatically stored in the LNR RAM. The capacity of the
RAM is 31 digits. If a number greater than 31 digits is entered, the LNR facility will be
inhibited (Until new entries < 32 digits) and further entries will be buffered in a First In First
Out Memory (FIFO).
Post dialled digits, i.e. digits manually entered after LNR has been invoked, are not stored
in RAM but buffered in FIFO.
During dialling, one or more pauses can be inserted by pressing the PAUSE KEY. Each
pause is 3 secs (optionally 6 secs) when inserted within the first 5 digits. Otherwise a Wait
Function will halt dialling until the LNR Key is pressed.
Recall Function
A Recall (R key or R2 key) activation will invoke a Flash (Timed Loop Break).
If Recall is the first entry in a digit string, it will be stored in LNR RAM when digit(s) are
entered after the Recall.
If the recall key is depressed after a digit string has been entered or dialled out, the recall
will not be stored but buffered in the FIFO together with subsequently entered digits.
If pressing the recall key is not followed by digit entries, the LNR RAM remains intact.
After a recall, a 3 second pause will automatically be executed.
Mute Function
The MUTE key is enabled in speech mode only. Depressing the MUTE key mutes the
microphone amplifier. Repressing the MUTE key deactivates the mute (toggle function).
Any key entry overwrites a mute activated by the MUTE key and mute will be deactivated.
When privacy mute is activated a reminder tone is applied to the earpiece every 3
seconds.
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5/22
SA2532
Sliding Cursor Procedure
To accommodate easy and uncomplicated redialling (LNR) behind a PABX, a sliding
cursor protocol is implemented. If new entries match the previous RAM contents,
pressing the LNR key will dial out the remaining digits.
If there is an error in matching, the LNR will be inhibited until next on-hook, and the RAM
will contain the new number.
Tone Generator
The tone generator incorporates the DTMF tones and 3 basic frequencies for the tone
ringer.
DTMF Tones
The DTMF Tone Generator creates 12 Tones in compliance with CCITT Recommendation Q23. Signal levels are altered by Mask Option. High group frequencies have a level
2.6dB higher than those of the Low Group.
Details of the DTMF Tones are:
Low group
Digit 1-2-3
Digit 4-5-6
Digit 7-8-9
Digit *-0-#
697Hz
770Hz
852Hz
941Hz
(Error = -.074%)
(Error = -.679%
(Error = -.621%)
(Error = +.139%)
Digit 1-4-7-*
Digit 2-5-8-0
Digit 3-6-9-#
1209Hz
1336 Hz
1477Hz
High group
(Error = +.533%)
(Error = +.176%)
(Error = -.141%)
Errors are calculated with reference to a base clock of 3.58MHz and at ambient
temperature of 24°C. They exclude tolerance errors in the base frequency.
KEYBOARD ARRANGEMENT
C1
C2
C3
C4
R1
MUTE
1
2
3
R2
4
5
6
7
R3
8
9
0
*
R4
#
PAUSE
R
R2
LNR/CONT.
DR-00709
Figure 2
6/22
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SA2532
Microcontroller Interface
The keypad Row and Column Pins can readily be driven by a Microcontroller Interface. When
configured in this way the SA2532 inputs and dials the corresponding digits in either LD or
DTMF. The LNR store can be used to buffer digits to allow high speed data entry. See
Application Note AN3002A for details.
Tone Ringer
The Tone Ringer of the SA2532 incorporates a Discriminator Circuit and adjustable Melody
Generator
Ring Frequency Discrimination
The Ring Frequency Discriminator assures that only signals with a frequency between
20Hz and 60Hz (option 13 Hz to 60 Hz) are regarded as valid ring signals.
When a valid ring signal is present for 73ms continuously, the melody generator is
activated and remains active as long as the ring signal is present.
Once the melody generator has been started, the ring signal is continuously monitored
and the melody generator is instantly turned on or off according to the momentary
presence of a valid or unvalid ring signal respectively (until next POR or off-hook).
Melody Generator
When a Valid Ring Signal is detected the Melody generator is activated and creates a
ringing Signal comprising 3 frequencies F1 (1065Hz), F2 (1420Hz) and F3 (1734Hz).
These frequencies are repeated in a sequence of 6 time slots constructed by the
frequencies
F1
F2
F3
F1
F2
F3
This sequence is repeated 1, 4, 7 or 10 times per second as indicated by the connection
of the RR Pin to one of the four rows of the keyboard.
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7/22
SA2532
TYPICAL APPLICATION
Only the components necessary for presenting the complete functions of the SA2532 are
included.
FIGURE 3
8/22
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SA2532
FEATURE PHONE APPLICATION
Only the components necessary for presenting the complete functions of the SA2532 are
included.
FIGURE 4
sames
9/22
SA2532
OPERATING PROCEDURES
Procedure Principles
The procedures for utilizing the features of the SA2532 are optimized out of consideration for
the human factor in order to:
- meet the user’s expectations
- be easy to learn and relearn
- not invoke any automatic functions which the user doesn’t expect
- protect the user from committing critical errors, e.g. dialling wrong numbers, deleting stored
numbers, etc.
- be consistent, simple and usable
SYMBOLS
10/22
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SA2532
Privacy Mute
sames
11/22
SA2532
Temporary MF
FIFO
Pressing any other
key does not
change the state.
EXIT FIFO
12/22
sames
SA2532
TIMING DIAGRAMS
LD Dialling
LD Dialling with Access Pause
MF Dialling
sames
13/22
SA2532
Flash
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Positive Supply Voltage ....................................................................................... -0.3V≤VDD≤7V
Input current .................................................................................................................. ±25mA
Input Voltage (LS) .............................................................................................. -0.3V≤VIN≤10V
Input Voltage (LI, CS) ........................................................................................... -0.3V≤VIN≤8V
Input Voltage (STB, RI) .............................................................................. -2V≤VVIN≤VDD+0.3V
Input Voltage (MO) ............................................................................................. -0.3V≤VIN≤35V
Digital Input Voltage ................................................................................... -0.3V≤VIN≤VDD+0.3V
Electrostatic Discharge ................................................................................................... ±800V
Storage Temperature ...................................................................................... -65°C to +125°C
Recommended Operating Conditions
≤VDD≤5V
Supply Voltage * (Speech Mode).......................................................................... 4V≤
Oscillator Frequency (Resonator: Murata CSA 3.58M G312AM).......................... 3.58 MHz
Operating Temperature ................................................................................... -25°C to +70°C
* This voltage is generated internally
DC Characteristics (ILINE = 15 mA unless otherwise specified)
Symbol
IDD
Parameter
Operating Current
IDDO
Retention Current
VLI
IOL
Line Voltage (default)
Output Current, Sink
CS,HS/DP,MO
14/22
sames
Conditions
Speech mode
MF dialling
LD dialling VDD = 2.5V
Ring mode V DD = 2.5V
Idle mode V DD = 2V,
TAMB = 25°C
13mA≤ILINE ≤100mA
VOL = 0.4V
Min
Typ
3
4
200
300
0.05
4.5
1.5
Max
5
Units
mA
mA
µA
µA
µA
V
mA
SA2532
AC Characteristics (ILINE=15mA;f=800Hz unless otherwise specified)
Symbol Parameter
TX
Transmit
ATX
Gain (M1/M2)
Conditions
Test Circuit Fig.5
Min
Typ
Max
Units
ZRL=600Ω
34
35
36
dB
ZRL = 1000Ω
36.5
Variation with Frequency
f=500Hz to 3.4kHz
±0.8
THD
Distortion
VLI≤0.5VRMS
VAGC
Soft Clip Level
VLI =
ASCO
ATX/F
dB
2
%
2
VPEAK
Soft Clip Overdrive
20
dB
tATTACK
Attack Time
30
µs/6dB
tDECAY
Decay Time
20
ms/6dB
ZIN
Input Impedance (M1/M2)
20
kΩ
AMUTE
Mute Attenuation
VNO
Noise Output Voltage
VFC
Unwanted Frequency
Components
Mute activated
60
dB
-72
dBmp
50...300 Hz
-43
dBm
4.3...28 kHz
note 1
above 28 kHZ
VIN MAX
Input Voltage Range
(M1/M2)
-70
dBm
Differential
±1
VPEAK
Single Ended
±0.5
VPEAK
BJT
Output Driver
VIN MAX
Input Voltage Range (LI)
±2
VPEAK
VTX
Dynamic Range
±2
VPEAK
RL
Return Loss
ZRL = 600Ω SA2532A
18
dB
ZRL = 1000Ω SA2532C/U
Note 1: -37 dBm at 4.3 kHz and decreasing 12 dB/octave till 28 kHz.
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15/22
SA2532
AC Characteristics (cont’d) (ILINE = 15 mA;f=800Hz unless otherwise specified)
Symbol Parameter
RX
ARX
Conditions
Receive
Test Circuit Fig.5
Receive Gain (RO1/RO2) ZRL=600Ω
Min
Typ
1
2
ZRL=1000Ω
-0.2
±0.8
∆ARX/F
Variation with Frequency
f=500 Hz to 3.4 kHz
THD
Distortion
VRI≤0.5VRMS
VAGC
Soft Clip Level
VRI=
ASCO
Soft Clip Overdrive
tATTACT
Attact Time
tDECAY
Decay Time
VNO
Noise Output Voltage
VFC
Unwanted Frequency
Max Units
3
dB
2
VRI>0.8V
dB
%
1
VPEAK
10
dB
30
µs/6dB
20
ms/6dB
50 Hz...20 kHz
-72
dBmp
-60
dBm
Components
ZIN
Input Impedance (RI)
8
kΩ
VIN RI
Input Voltage Range(RI)
±2
VPEAK
ST
AST
Sidetone
Sidetone Cancellation
VIN ST
Input Voltage Range (STB)
±2
VPEAK
ZIN
Input Impedance (STB)
80
kΩ
tD
Keyboard
Key Debounce Time
15
ms
tHS-L
HS Input
Low to High Debounce
Going off-hook
15
ms
tHS-H
High to Low Debounce
Line breaks/on-hook
240
ms
∆F
VMF
DTMF
Frequency deviation
Note 5
MF Tone Level(Low group) Optionally
VL-H
Test Circuit Fig.5
VRI≤0.5VRMS
Preemphasis Low to High
THD
Distortion
Note 3
tTD
tITP
Tone Duration
Inter Tone Pause
Note 1
16/22
sames
26
-.679
-12.5
-9.5
2.0
80
80
dB
-11
-8
2.6
82.3
82.3
+.533
-9.5
-6.5
3.0
%
dB
dB
dB
-30
dBr
85
85
ms
ms
SA2532
AC Characteristics Cont'd
Symbol Parameter
Conditions
Min
Typ
Max
Units
tTR
Tone Rise Time
Note 2
5
ms
tTF
Tone Fall Time
Note 2
5
ms
LD
tDR
Dial Rate
±5%
tM/B
Make/Break Period
±5%, MODE=low
±5%, MODE=high
tPDP
Pre-Digit Pause
tIDP
Inter Digit Pause
tMO
Mute Overhang
tFD
Flash Duration 1
Flash Duration 2
Flash Duration 2
tPFP
Post Flash Pause
tAP
Access Pause Period
VMO
tMD
F1
F2
F3
tDT
tTO
fMIN
fMIN
fMAX
VRT
tRTD
tRTI
VCT
Tone Ringer
Melody Output Level
Melody Delay
Frequency 1
Frequency 2
Frequency 3
Detection Time
Detection Time-out
Min. Detection Frequency
Min. Detection Frequency
Max. Detection Frequency
Reminder Tone
Level (RO1/RO2)
Duration
Interval
Comfort Tone (DTMF)
Level (RO1/RO2)
sames
800
10
pps
40.8/61.2
33/66
ms
ms
35
ms
840
880
ms
102
300
650
ms
ms
ms
tM
SA2532A/C
SA2532U
100
270
600
2.9
3.0
3.1
sec.
SA2532A/U
2.9
3.0
3.1
sec
SA2532C
5.8
6.0
6.2
sec
10
1107
1477
1803
80
ms
Hz
Hz
Hz
ms
ms
Hz
Hz
Hz
PDM
Initial
Optionally
1020
1363
1665
70
19
12
58
1064
1420
1734
note 4
20
13
59
21
14
60
Relative to LS
-30
82.3
3
dBr
ms
sec
Relative to LS
-30
dBr
17/22
SA2532
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
18/22
The values are valid during automatic dialling and are minimum values during
manual dialling, i.e. the tones will continue as long as the key is depressed.
The rise time is the time from 10% of final value until the tone amplitude has reached
90% of its final value.
Relative to high group.
The FCI circuit is reset by POR and HS/DP pulled high (off-hook). After a reset the
FCI circuit is in a standby state. A positive edge on FCI will start a 73ms timer and
the frequency discrimination is initiated. Whenever a period of the ring signal is
missing, the timer is reset. When a valid ring signal is present for ≥ 73ms, the
melody generator is started and is directly controlled by the ring signal. This
condition will remain until a new reset.
This does not include the frequency deviation of the ceramic resonator.
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SA2532
Test Circuit
Figure 5
sames
19/22
SA2532
Ordering Information:
Versions
ZRL
(ohm)
DTMF
Level
R2
Period
Access
Pause
Package
SA2532A P
600
-6/-8dBm
280ms
3s
28 pin DIP
SA2532A S
600
-6/-8dBm
280ms
3s
28 pin SOIC
SA2532C P
1000
-6/-8dBm
280ms
6s
28 pin DIP
SA2532C S
1000
-6/-8dBm
280ms
6s
28 pin SOIC
SA2532U P
1000
-9/-11dBm
600ms
3s
28 pin DIP
SA2532U S
1000
-9/-11dBm
600ms
3s
28 pin SOIC
20/22
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SA2532
NOTES:
sames
21/22
SA2532
Disclaimer: The information contained in this document is confidential and proprietary to South African MicroElectronic Systems (Pty) Ltd ("SAMES) and may not be copied or disclosed to a third party, in whole or in part,
without the express written consent of SAMES. The information contained herein is current as of the date of
publication; however, delivery of this document shall not under any circumstances create any implication that
the information contained herein is correct as of any time subsequent to such date. SAMES does not undertake
to inform any recipient of this document of any changes in the information contained herein, and SAMES
expressly reserves the right to make changes in such information, without notification,even if such changes would
render information contained herein inaccurate or incomplete. SAMES makes no representation or warranty that
any circuit designed by reference to the information contained herein, will function without errors and as intended
by the designer.
South African Micro-Electronic Systems (Pty) Ltd
P O Box 15888,
33 Eland Street,
Lynn East,
Koedoespoort Industrial Area,
0039
Pretoria,
Republic of South Africa,
Republic of South Africa
Tel:
Fax:
22/22
012 333-6021
012 333-8071
Tel:
Fax:
sames
Int +27 12 333-6021
Int +27 12 333-8071