TI SN74HC645DWRE4

 SCLS304B – JANUARY 1996 – REVISED DECEMBER 2002
D Wide Operating Voltage Range of 2 V to 6 V
D High-Current 3-State Outputs Can Drive Up
D
D
D
D
To 15 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
Typical tpd = 12 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
True Logic
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
A2
A1
DIR
VCC
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
A3
A4
A5
A6
A7
4
3 2 1 20 19
18
5
17
6
16
7
15
14
8
B1
B2
B3
B4
B5
9 10 11 12 13
A8
GND
B8
B7
B6
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
OE
SN54HC645 . . . FK PACKAGE
(TOP VIEW)
SN54HC645 . . . J OR W PACKAGE
SN74HC645 . . . DW, N, OR NS PACKAGE
(TOP VIEW)
description/ordering information
These octal bus transceivers are designed for asynchronous two-way communication between data buses.
These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the
level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the
buses are effectively isolated.
ORDERING INFORMATION
PDIP – N
–40°C
40°C to 85°C
–55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
Tube
SN74HC645N
Tube
SN74HC645DW
Tape and reel
SN74HC645DWR
SOP – NS
Tape and reel
SN74HC645NSR
HC645
CDIP – J
Tube
SNJ54HC645J
SNJ54HC645J
CFP – W
Tube
SNJ54HC645W
SNJ54HC645W
SOIC – DW
SN74HC645N
HC645
LCCC – FK
Tube
SNJ54HC645FK
SNJ54HC645FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
! " #$%! " &$'(# ! ) !%*
)$#!" # ! "&%## !" &% !+% !%" %, " "!$%!"
"! ) ) - !.* )$#! &#%""/ )%" ! %#%"" (. #($)%
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$(%"" !+%-"% !%)* (( !+% &)$#!" &)$#!
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POST OFFICE BOX 655303
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1
SCLS304B – JANUARY 1996 – REVISED DECEMBER 2002
logic diagram (positive logic)
OE
DIR
A1
19
1
2
18
B1
To Seven Other Transceivers
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC645
VCC
Supply voltage
VIH
High-level
High
level in
input
ut voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
Low-level
Low
level in
input
ut voltage
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
VCC = 4.5 V
VCC = 6 V
VI
VO
Input voltage
0
Output voltage
0
∆t/∆v
Input
In
ut transition rise/fall time
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
TA
2
Operating free-air temperature
–55
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SN74HC645
• DALLAS, TEXAS 75265
0.5
0.5
1.35
1.8
1.8
0
0
VCC
VCC
1000
1000
500
500
400
400
125
–40
V
V
1.35
VCC
VCC
UNIT
85
V
V
V
ns
°C
SCLS304B – JANUARY 1996 – REVISED DECEMBER 2002
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20
20 µA
VOH
VI = VIH or VIL
IOH = –6 mA
IOH = –7.8 mA
IOL = 20 µA
VOL
VI = VIH or VIL
IOL = 6 mA
IOL = 7.8 mA
II
IOZ
DIR or OE
A or B
ICC
Ci
VI = VCC or 0
VO = VCC or 0
VI = VCC or 0,
IO = 0
VCC
MIN
TA = 25°C
TYP
MAX
MIN
MAX
SN74HC645
MIN
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
µA
8
160
80
µA
10
10
10
pF
6V
DIR or OE
SN54HC645
2 V to 6 V
3
V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
d
ten
tdis
tt
FROM
(INPUT)
A or B
OE
OE
TA = 25°C
MIN
TYP
MAX
SN54HC645
SN74HC645
TO
(OUTPUT)
VCC
2V
40
105
160
130
B or A
4.5 V
15
21
32
26
6V
12
18
27
22
A or B
A or B
A or B
MIN
MAX
MIN
MAX
2V
125
230
340
290
4.5 V
23
46
68
58
6V
20
39
58
49
2V
74
200
300
250
4.5 V
25
40
60
50
6V
21
34
51
43
2V
20
60
90
75
4.5 V
8
12
18
15
6V
6
10
15
13
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• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
3
SCLS304B – JANUARY 1996 – REVISED DECEMBER 2002
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
SN54HC645
SN74HC645
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
54
135
200
170
tpd
d
A or B
B or A
4.5 V
18
27
40
34
6V
15
23
34
29
ten
tt
OE
A or B
A or B
MIN
MIN
MAX
MIN
MAX
2V
150
270
405
335
4.5 V
31
54
81
67
6V
25
46
69
56
2V
45
210
315
265
4.5 V
17
42
63
53
6V
13
36
53
45
UNIT
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
TEST CONDITIONS
Power dissipation capacitance per transceiver
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No load
• DALLAS, TEXAS 75265
TYP
40
UNIT
pF
SCLS304B – JANUARY 1996 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
VCC
PARAMETER
Test
Point
From Output
Under Test
S1
tPZH
ten
RL
CL
(see Note A)
1 kΩ
tPZL
tPHZ
tdis
S2
RL
tPLZ
tpd or tt
1 kΩ
––
LOAD CIRCUIT
CL
S1
S2
50 pF
or
150 pF
Open
Closed
Closed
Open
Open
Closed
Closed
Open
Open
Open
50 pF
50 pF
or
150 pF
VCC
Input
50%
50%
0V
tPLH
In-Phase
Output
50%
10%
tPHL
90%
VOH
50%
10% V
OL
tf
90%
tr
tPHL
Out-of-Phase
Output
90%
tPLH
50%
10%
50%
10%
90%
tf
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
Output
Control
(Low-Level
Enabling)
VCC
50%
50%
0V
tPZL
Output
Waveform 1
(See Note B)
tPLZ
≈VCC
50%
10%
tPZH
Input
50%
10%
90%
VCC
50%
10% 0 V
90%
tr
Output
Waveform 2
(See Note B)
≈VCC
VOL
tPHZ
50%
90%
VOH
≈0 V
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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5
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN54HC645J
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
SN74HC645DW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
SN74HC645DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC645DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC645DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC645DWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC645DWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC645N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74HC645NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74HC645NSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC645NSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC645NSRG4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54HC645FK
ACTIVE
LCCC
FK
20
1
TBD
SNJ54HC645J
ACTIVE
CDIP
J
20
1
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2008
TAPE AND REEL BOX INFORMATION
Device
SN74HC645DWR
Package Pins
DW
20
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
SITE 41
330
24
10.8
13.0
2.7
12
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
24
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2008
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74HC645DWR
DW
20
SITE 41
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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