SCLS005D − MARCH 1984 − REVISED AUGUST 2003 D Operating Voltage Range of 4.5 V to 5.5 V D High-Current 3-State True Outputs Can D D D D D D D SN54HCT374 . . . J OR W PACKAGE SN74HCT374 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) Drive Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 22 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible Eight D-Type Flip-Flops in a Single Package Full Parallel Access for Loading OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND description/ordering information These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK 1D 1Q OE VCC 8Q SN54HCT374 . . . FK PACKAGE (TOP VIEW) 2D 2Q 3Q 3D 4D 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND CLK 5Q 5D The eight flip-flops of the ’HCT374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs. 4 An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION PDIP − N SN74HCT374N Tube of 25 SN74HCT374DW Reel of 2000 SN74HCT374DWR SOP − NS Reel of 2000 SN74HCT374NSR HCT374 SSOP − DB Reel of 2000 SN74HCT374DBR HT374 Tube of 70 SN74HCT374PW Reel of 2000 SN74HCT374PWR TSSOP − PW −55°C −55 C to 125 125°C C TOP-SIDE MARKING Tube of 20 SOIC − DW −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SN74HCT374N HCT374 HT374 Reel of 250 SN74HCT374PWT CDIP − J Tube of 20 SNJ54HCT374J SNJ54HCT374J CFP − W Tube of 85 SNJ54HCT374W SNJ54HCT374W LCCC − FK Tube of 55 SNJ54HCT374FK SNJ54HCT374FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* &)$#!" #&(! ! 01 (( &%!%" % !%"!%) $(%"" !+%-"% !%)* (( !+% &)$#!" &)$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS005D − MARCH 1984 − REVISED AUGUST 2003 description/ordering information (continued) OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z logic diagram (positive logic) OE CLK 1 11 C1 1D 3 1D 2 1Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS005D − MARCH 1984 − REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HCT374 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO ∆t/∆v Output voltage 0 High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V SN74HCT374 2 2 Input transition rise/fall time V V 0.8 VCC VCC UNIT 0 0 500 0.8 V VCC VCC V 500 ns V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = −20 µA IOH = −6 mA 4.5 V VOL VI = VIH or VIL IOL = 20 µA IOL = 6 mA 4.5 V II IOZ VI = VCC or 0 VO = VCC or 0 ICC VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC 5.5 V ∆ICC† MIN SN54HCT374 MIN MAX SN74HCT374 MIN 4.4 4.499 4.4 4.4 3.98 4.3 3.7 3.84 MAX UNIT V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 5.5 V ±0.1 ±100 ±1000 ±1000 nA 5.5 V ±0.01 ±0.5 ±10 ±5 µA 8 160 80 µA 1.4 2.4 3 2.9 mA 3 10 10 10 pF 5.5 V 4.5 V to 5.5 V Ci TA = 25°C TYP MAX V † This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. timing requirements over recommended operating free-air temperature range (unless otherwise noted) fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time, data before CLK↑ th Hold time, data after CLK↑ POST OFFICE BOX 655303 TA = 25°C MIN MAX SN54HCT374 VCC 4.5 V 31 21 25 5.5 V 36 23 28 MIN MAX SN74HCT374 MIN 4.5 V 16 24 20 5.5 V 14 22 18 4.5 V 20 30 25 5.5 V 17 27 23 4.5 V 10 10 10 5.5 V 10 10 10 • DALLAS, TEXAS 75265 MAX UNIT MHz ns ns ns 3 SCLS005D − MARCH 1984 − REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLK Any Q ten OE Any Q tdis OE Any Q tt Any Q TA = 25°C TYP MAX SN54HCT374 SN74HCT374 VCC MIN 4.5 V 31 36 21 25 5.5 V 36 40 23 28 MIN MAX MIN MAX UNIT MHz 4.5 V 30 36 54 45 5.5 V 25 32 49 41 4.5 V 26 30 45 38 5.5 V 23 27 41 34 4.5 V 23 30 45 38 5.5 V 22 27 41 34 4.5 V 10 12 18 15 5.5 V 9 11 16 14 ns ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd CLK Any Q ten OE Any Q tt Any Q VCC MIN TA = 25°C TYP MAX SN54HCT374 MIN MAX SN74HCT374 MIN MAX 4.5 V 40 46 69 58 5.5 V 35 41 62 52 4.5 V 34 40 60 50 5.5 V 29 36 54 45 4.5 V 18 42 63 53 5.5 V 16 38 57 48 UNIT ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance per flip-flop POST OFFICE BOX 655303 No load • DALLAS, TEXAS 75265 TYP 85 UNIT pF SCLS005D − MARCH 1984 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC S1 Test Point From Output Under Test PARAMETER ten RL tdis CL (see Note A) S2 tPZH 1 kΩ tPZL tPHZ tPLZ tpd or tt CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open RL 1 kΩ 50 pF 50 pF or 150 pF −− LOAD CIRCUIT 3V High-Level Pulse 1.3 V 3V Reference Input 1.3 V 0V 1.3 V tsu 0V tw Data Input 1.3 V 0.3 V 3V Low-Level Pulse 1.3 V 1.3 V Output Control (Low-Level Enabling) 3V 1.3 V 0V tPLH In-Phase Output 1.3 V 10% tPHL 90% 90% tr Out-ofPhase Output tPHL 90% VOH 1.3 V 10% V OL tf tPLH 1.3 V 10% 1.3 V 10% tf 2.7 V 3V 1.3 V 0.3 V 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 2.7 V tr 0V Input th 3V 1.3 V 1.3 V 0V tPZL Output Waveform 1 (See Note B) tPLZ ≈VCC 1.3 V 10% tPZH 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES Output Waveform 2 (See Note B) VOL tPHZ 1.3 V 90% VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type 5962-8550701VRA ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type 5962-8550701VSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 85507012A ACTIVE LCCC FK 20 1 TBD 8550701RA ACTIVE CDIP J 20 1 TBD POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type JM38510/65652BRA ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type 1 TBD A42 SNPB N / A for Pkg Type SN54HCT374J ACTIVE CDIP J 20 SN74HCT374DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374N ACTIVE PDIP N 20 CU NIPDAU N / A for Pkg Type 20 Pb-Free (RoHS) TBD Call TI 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HCT374N3 OBSOLETE PDIP N 20 SN74HCT374NE4 ACTIVE PDIP N 20 SN74HCT374NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374NSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374NSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374PWT ACTIVE TSSOP PW 20 250 CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Green (RoHS & Call TI PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74HCT374PWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HCT374PWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54HCT374FK ACTIVE LCCC FK 20 1 TBD SNJ54HCT374J ACTIVE CDIP J 20 1 TBD Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2008 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HCT374DBR DB 20 SITE 41 330 16 8.2 7.5 2.5 12 16 Q1 SN74HCT374DWR DW 20 SITE 60 330 24 10.8 13.1 2.65 12 24 Q1 SN74HCT374DWR DW 20 SITE 41 330 24 10.8 13.0 2.7 12 24 Q1 SN74HCT374PWR PW 20 SITE 41 330 16 6.95 7.1 1.6 8 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 4-Jan-2008 Package Pins Site Length (mm) Width (mm) Height (mm) SN74HCT374DBR DB 20 SITE 41 346.0 346.0 33.0 SN74HCT374DWR DW 20 SITE 60 346.0 346.0 41.0 SN74HCT374DWR DW 20 SITE 41 346.0 346.0 41.0 SN74HCT374PWR PW 20 SITE 41 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265