TI SN74AHC1G00

SN74AHC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCLS313G – MARCH 1996 – REVISED JANUARY 2000
D
D
D
D
EPIC  (Enhanced-Performance Implanted
CMOS) Process
Operating Range 2-V to 5.5-V VCC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic
Small-Outline Transistor (DBV, DCK)
Packages
DBV OR DCK PACKAGE
(TOP VIEW)
A
B
GND
1
5
VCC
4
Y
2
3
description
The SN74AHC1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.
The SN74AHC1G00 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
B
H
H
L
L
X
H
X
L
H
logic symbol†
A
B
1
&
4
2
Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
A
B
1
2
4
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74AHC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCLS313G – MARCH 1996 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 3 V
High-level input voltage
VCC = 5.5 V
VCC = 2 V
MIN
MAX
2
5.5
UNIT
V
1.5
V
2.1
3.85
0.5
VIL
Low-level input voltage
VI
VO
Input voltage
0
5.5
V
Output voltage
0
VCC
–50
V
IOH
High-level output current
VCC = 3 V
VCC = 5.5 V
VCC = 2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 2 V
IOL
∆t/∆v
Low-level output current
Input transition rise or fall rate
0.9
V
1.65
–4
–8
50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
4
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
100
8
20
mA
mA
mA
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
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SN74AHC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCLS313G – MARCH 1996 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
MIN
TA = 25°C
TYP
MAX
MIN
2V
1.9
2
1.9
3V
2.9
3
2.9
4.5 V
4.4
4.5
4.4
IOH = –4 mA
3V
2.58
2.48
IOH = –8 mA
4.5 V
3.94
3.8
PARAMETER
TEST CONDITIONS
VCC
IOH = –50 mA
VOH
IOL = 50 mA
VOL
IOL = 4 mA
II
ICC
Ci
IOL = 8 mA
VI = VCC or GND
VI = VCC or GND,
VI = VCC or GND
IO = 0
MAX
UNIT
V
2V
0.1
0.1
3V
0.1
0.1
4.5 V
0.1
0.1
3V
0.36
0.44
4.5 V
0.36
0.44
0 V to 5.5 V
±0.1
±1
mA
1
10
mA
10
10
pF
5.5 V
5V
2
V
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tPLH
tPHL
A or B
Y
CL = 15 pF
tPLH
tPHL
A or B
Y
CL = 50 pF
MIN
TA = 25°C
TYP
MAX
MIN
MAX
5.5
7.9
1
9.5
5.5
7.9
1
9.5
8
11.4
1
13
8
11.4
1
13
UNIT
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tPLH
tPHL
A or B
Y
CL = 15 pF
tPLH
tPHL
A or B
Y
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
MIN
MAX
3.7
5.5
1
6.5
3.7
5.5
1
6.5
5.2
7.5
1
8.5
5.2
7.5
1
8.5
UNIT
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
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f = 1 MHz
TYP
UNIT
9.5
pF
3
SN74AHC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCLS313G – MARCH 1996 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
From Output
Under Test
Test
Point
From Output
Under Test
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
VCC
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
0V
tPZL
VOH
50% VCC
VOL
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
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