SHARP LH543611

LH543611/21
512 × 36 × 2 / 1024 × 36 × 2
Synchronous Bidirectional FIFO
FEATURES
FUNCTIONAL DESCRIPTION
• Pin-Compatible and Functionally
The LH543611 and LH543621 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but
in opposite directions, for bidirectional data buffering.
FIFO #1 and FIFO #2 each are organized as 512 or 1024
by 36 bits. The LH543611 and LH543621 are ideal either
for wide unidirectional applications or for bidirectional
data applications; component count and board area are
reduced.
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Upwards-Compatible with Sharp LH5420 and
LH543601, but Deeper
Expanded Control Register that is Fully
Readable as well as Writeable
Fast Cycle Times: 18/20/25/30/35 ns
Improved Input Setup and Flag Out Timing
Two 512 × 36-bit FIFO Buffers (LH543611) or
Two 1024 × 36-bit FIFO Buffers (LH543621)
Full 36-bit Word Width
Selectable 36/18/9-bit Word Width on Port B;
Selection May be Changed Without Resetting
the BiFIFO
Programmable Byte-Order Reversal –
‘Big-Endian ↔ Little-Endian Conversion’
Independently-Synchronized (‘Fully-Asynchronous’)
Operation of Port A and Port B
‘Synchronous’ Enable-Plus-Clock Control at
Both Ports
R/W, Enable, Request, and Address Control Inputs
are Sampled on the Rising Clock Edge
Synchronous Request/Acknowledge ‘Handshake’
Capability; Use is Optional
Device Comes Up Into a Known Default State at
Reset; Programming is Allowed, but is not Required
Asynchronous Output Enables
Five Status Flags per Port: Full, Almost-Full,
Half-Full, Almost-Empty, and Empty
All Flags are Independently Programmable for
Either Synchronous or Asynchronous Operation
Almost-Full Flag and Almost-Empty Flag Have
Programmable Offsets
Mailbox Registers with Synchronized Flags
Data-Bypass Function
Data-Retransmit Function
Automatic Byte Parity Checking with
Programmable Parity Flag Latch
Programmable Byte Parity Generation
Programmable Byte, Half-Word, or Full-Word
Oriented Parity Operations
8 mA-IOL High-Drive Three-State Outputs with
Built-In Series Resistor
TTL/CMOS-Compatible I/O
Space-Saving PQFP and TQFP Packages
The LH543611 and LH543621 have two 36-bit ports,
Port A and Port B. Each port has its own port-synchronous clock, but the two ports may operate asynchronously relative to each other. Data flow is initiated at a port
by the rising edge of the appropriate clock; it is gated by
the corresponding edge-sampled enable, request, and
read/write control signals. At the maximum operating
frequency, the clock duty cycle may vary from 40% to
60%. At lower frequencies, the clock waveform may be
quite asymmetric, as long as the minimum pulse-width
conditions for clock-HIGH and clock-LOW remain satisfied; the LH543611 and LH543621 are fully-static parts.
Conceptually, the port clocks CKA and CKB are freerunning, periodic ‘clock’ waveforms, used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that these ‘clock’ waveforms must be periodic. An ‘asynchronous’ mode of operation is possible, in one or both directions,
independently, if the appropriate enable and request inputs are continuously asserted, and enough aperiodic
‘clock’ pulses of suitable duration are generated by external logic to cause all necessary actions to occur.
A synchronous request/acknowledge handshake
facility is provided at each port for FIFO data access. This
request/ acknowledge handshake resolves FIFO full and
empty boundary conditions, when the two ports are operated asynchronously relative to each other.
FIFO status flags monitor the extent to which each
FIFO buffer has been filled. Full, Almost-Full, Half-Full,
Almost-Empty, and Empty flags are included for each
FIFO. Each of these flags may be independently programmed for either synchronous or asynchronous operation. Also, the Almost-Full and Almost-Empty flags are
programmable over the entire FIFO depth, but are automatically initialized to eight locations from the respective
FIFO boundaries at reset. A data block of 512 (LH543611)
or 1024 (LH543621) or fewer words may be retransmitted
any desired number of times.
BOLD = Additions over the 5420/3601 feature set
1
LH543611/21
Two mailbox registers provide a separate path for
passing control words or status words between ports.
Each mailbox has a New-Mail-Alert Flag, which is synchronized to the reading port’s clock. This mailbox function facilitates the synchronization of data transfers
between asynchronous systems.
Data-bypass mode allows Port A to directly transfer
data to or from Port B at reset. In this mode, the device
acts as a registered transceiver under the control of
Port A. For instance, a master processor on Port A can
use the data bypass feature to send or receive initialization or configuration information directly, to or from a
peripheral device on Port B, during system startup.
A word-width-select option is provided on Port B for
36-bit, 18-bit, or 9-bit data access. This feature allows
word-width matching between Port A and Port B, with no
additional logic needed. It also ensures maximum utilization of bus band widths. Subject to meeting timing requirements, the word-width selection may be changed at any
time during the operation of an LH543611 or LH543621,
without the need either for a reset operation or for passing
dummy words through Port B immediately after the
2
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
change; except that if the change is not made at a
full-word boundary, at least one dummy word must be
passed through Port B before any actual data words
are transmitted.
A Byte Parity Check Flag at each port monitors data
integrity. Control-Register bit 00 (zero) selects the parity
mode, odd or even. This bit is initialized for odd data parity
at reset; but it may be reprogrammed for even parity, or
back again to odd parity, as desired. The parity flags may
be programmed to operate either in a latched mode or in
a flowthrough mode. The parity checking may be performed over 36-bit full-words, over 18-bit half-words, or
over 9-bit single bytes.
Parity generation may be selected as well as parity
checking, and may likewise be performed over full-words
or half-words or single bytes. In any case, a parity bit of
the proper mode is generated over the least-significant
eight bits of a byte, and then is stored in the most-significant bit position of the byte as it passes through the
LH543611/21, overwriting whatever bit was present in
that bit position previously.
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
PIN CONNECTIONS
TOP VIEW
CHAMFERED
EDGE
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
VCCO
D24A
D25A
D26A
VSSO
D27A
D28A
D29A
VCCO
D30A
D31A
D32A
VSSO
D33A
D34A
D35A
RT2
VSS
D35B
D34B
VSSO
D33B
D32B
D31B
VCCO
D30B
D29B
D28B
VSSO
D27B
D26B
D25B
VCCO
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
D12B
D13B
D14B
D15B
VSSO
D16B
D17B
MBF1
AE1
EF1
ACKB
VSS
REQB
ENB
R/WB
CKB
A0B
WS0
WS1
OEB
VCC
FF2
AF2
HF2
PFB
D18B
D19B
D20B
VSSO
D21B
D22B
D23B
D24B
VCCO
D10A
D9A
D8A
VSSO
D7A
D6A
D5A
VCCO
D4A
D3A
D2A
VSSO
D1A
D0A
RS
RT1
D0B
D1B
D2B
VSSO
D3B
D4B
D5B
VCCO
D6B
D7B
D8B
VSSO
D9B
D10B
D11B
VCCO
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Pin 1
Pin 132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
D11A
D12A
D13A
D14A
VSSO
D15A
D16A
D17A
PFA
HF1
AF1
FF1
VCC
OEA
A2A
A1A
A0A
CKA
R/WA
ENA
REQ
A
VSS
ACKA
EF2
AE2
MBF2
D18A
D19A
VSSO
D20A
D21A
D22A
D23A
132-PIN PQFP
543611-1
Figure 1. Pin Connections for 132-Pin PQFP Package
(Top View)
3
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TOP VIEW
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VSSO
D23A
D22A
D21A
D20A
VSSO
D19A
D18A
MBF2
AE2
EF2
ACKA
VSS
REQA
ENA
R/WA
CKA
VSS
A0A
A1A
A2A
OEA
VCC
FF1
AF1
HF1
PFA
D17A
D16A
D15A
VSSO
D14A
D13A
D12A
D11A
VSSO
144-PIN TQFP
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VCCO
VCCO
D10A
D9A
D8A
VSSO
D7A
D6A
D5A
VCCO
D4A
D3A
D2A
VSSO
D1A
D0A
RS
RT1
VSSO
D0B
D1B
D2B
VSSO
D3B
D4B
D5B
VCCO
D6B
D7B
D8B
VSSO
D9B
D10B
D11B
VCCO
FR2
VSSO
D24B
D23B
D22B
D21B
VSSO
D20B
D19B
D18B
PFB
HF2
AF2
FF2
VCC
OEB
WS1
WS0
VSS
A0B
CKB
R/WB
ENB
REQB
VSS
ACKB
EF1
AE1
MBF1
D17B
D16B
VSSO
D15B
D14B
D13B
D12B
VSSO
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
FR1
VCCO
D24A
D25A
D26A
VSSO
D27A
D28A
D29A
VCCO
D30A
D31A
D32A
VSSO
D33A
D34A
D35A
RT2
VSSO
VSS
D35B
D34B
VSSO
D33B
D32B
D31B
VCCO
D30B
D29B
D28B
VSSO
D27B
D26B
D25B
VCCO
VCCO
543611-2
Figure 2. Pin Connections for 144-Pin TQFP Package
(Top View)
4
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
PIN LIST
SIGNAL
NAME
A0A
A1A
A2A
OEA
FF1
AF1
HF1
PFA
D17A
D16A
D15A
D14A
D13A
D12A
D11A
D10A
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
RS
RT1
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B
D12B
D13B
D14B
D15B
D16B
D17B
MBF1
AE1
PQFP
PIN NO.
TQFP
PIN NO.
SIGNAL
NAME
PQFP
PIN NO.
TQFP
PIN NO.
1
2
3
4
6
7
8
9
10
11
12
14
15
16
17
19
20
21
23
24
25
27
28
29
31
32
33
34
35
36
37
39
40
41
43
44
45
47
48
49
51
52
53
54
56
57
58
59
126
125
124
123
121
120
119
118
117
116
115
113
112
111
110
106
105
104
102
101
100
98
97
96
94
93
92
91
89
88
87
85
84
83
81
80
79
77
76
75
71
70
69
68
66
65
64
63
EF1
ACKB
REQB
ENB
R/WB
CKB
A0B
WS0
WS1
OEB
FF2
AF2
HF2
PFB
D18B
D19B
D20B
D21B
D22B
D23B
D24B
D25B
D26B
D27B
D28B
D29B
D30B
D31B
D32B
D33B
D34B
D35B
RT2
D35A
D34A
D33A
D32A
D31A
D30A
D29A
D28A
D27A
D26A
D25A
D24A
D23A
D22A
D21A
60
61
63
64
65
66
67
68
69
70
72
73
74
75
76
77
78
80
81
82
83
85
86
87
89
90
91
93
94
95
97
98
100
101
102
103
105
106
107
109
110
111
113
114
115
117
118
119
62
61
59
58
57
56
55
53
52
51
49
48
47
46
45
44
43
41
40
39
38
34
33
32
30
29
28
26
25
24
22
21
18
17
16
15
13
12
11
9
8
7
5
4
3
143
142
141
SIGNAL
NAME
D20A
D19A
D18A
MBF2
AE2
EF2
ACKA
REQA
ENA
R/WA
CKA
VCC
VSSO
VSSO
VCCO
VCCO
VSSO
VCCO
VSSO
VSSO
VSSO
VCCO
VSSO
VCCO
VCCO
VSSO
VSSO
VSS
VSS
VCC
VSSO
VSSO
VCCO
VCCO
VSSO
VCCO
VSSO
VSS
VSSO
VSSO
VCCO
VSSO
VCCO
VCCO
VSSO
VSSO
VSS
VSS
PQFP
PIN122 NO.
TQFP
PIN NO.
120
122
123
124
125
126
127
129
130
131
132
5
13
140
138
137
136
135
134
133
131
130
129
128
122
114
109
108
107
103
99
95
90
86
82
78
74
73
72
67
60
54
50
42
37
36
35
31
27
23
20
19
14
10
6
2
1
144
139
132
127
18
22
26
30
38
42
46
50
55
62
71
79
84
88
92
96
99
104
108
112
116
121
128
NOTE:
PINS
VCC
VCCO
COMMENTS
Supply internal logic. Connected to each other.
Supply output drivers only. Connected to each
other.
PINS
VSS
VSSO
COMMENTS
Supply internal logic. Connected to each other.
Supply output drivers only. Connected to each
other.
5
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
WRITE
PORT A
I/O
READ
READ
FIFO 1
WRITE
FIFO 2
PORT A
CONTROL
PORT B
I/O
PORT B
CONTROL
543611-3
Figure 3a. Simplified LH543611/21 Block Diagram
BYPASS
FR1
RS
MBF1
FR2
RESET
LOGIC
MAILBOX
REGISTER
#1
MBF2
A2A
A1A
A0A
COMMAND
PORT AND
REGISTER
MAILBOX
REGISTER
#2
COMMAND
PORT AND
REGISTER
A0B
PORT B
SYNCHRONOUS
CONTROL
LOGIC
CKB
R/WB
ENB
REQB
ACKB
FIFO #1
MEMORY ARRAY
512 x 36 / 1024 x 36
CKA
R/WA
ENA
REQA
ACKA
PORT A
SYNCHRONOUS
CONTROL
LOGIC
FF1
AF1
WRITE
POINTER
READ
POINTER
FIXED AND
PROGRAMMABLE
STATUS FLAGS
HF1
EF1
AE1
RT1
RT2
OEA
READ
POINTER
WRITE
POINTER
OEB
PORT B
I/O
PORT A
I/O
D0A - D35A
PFA
FF2
AF2
HF2
FIXED AND
PROGRAMMABLE
STATUS FLAGS
EF2
AE2
WS0, WS1
FIFO #2
MEMORY ARRAY
512 x 36 / 1024 x 36
PARITY
CHECKING
AND
GENERATION
RESOURCE
REGISTERS
D0B - D35B
PARITY
CHECKING
AND
GENERATION
PFB
543611-4
Figure 3b. Detailed LH543611/21 Block Diagram
6
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
PIN DESCRIPTIONS
PIN
PIN TYPE 1
DESCRIPTION
GENERAL
VCC, VSS
V
Power, Ground
RS
I
Reset
PORT A
CKA
I
Port A Free-Running Clock
R/WA
I
Port A Edge-Sampled Read/Write Control
ENA
I
Port A Edge-Sampled Enable
A0A, A1A, A2A
I
Port A Edge-Sampled Address Pins
OEA
I
Port A Level-Sensitive Output Enable
REQA
I
Port A Request/Enable
RT2
I
FIFO #2 Retransmit
D0A – D35A
I/O/Z
Port A Bidirectional Data Bus
FF1
O
FIFO #1 Full Flag (Write Boundary)
AF1
O
FIFO #1 Programmable Almost-Full Flag (Write Boundary)
HF1
O
FIFO #1 Half-Full Flag
AE2
O
FIFO #2 Programmable Almost-Empty Flag (Read Boundary)
EF2
O
FIFO #2 Empty Flag (Read Boundary)
MBF2
O
New-Mail-Alert Flag for Mailbox #2
PFA
O
Port A Parity Flag
ACKA
O
Port A Acknowledge
PORT B
CKB
I
Port B Free-Running Clock
R/WB
I
Port B Edge-Sampled Read/Write Control
ENB
I
Port B Edge-Sampled Enable
A0B
I
Port B Edge-Sampled Address Pin
OEB
I
Port B Level-Sensitive Output Enable
WS0, WS1
I
Port B Word-Width Select
REQB
I
Port B Request/Enable
RT1
I
FIFO #1 Retransmit
D0B – D35B
I/O/Z
Port B Bidirectional Data Bus
FF2
O
FIFO #2 Full Flag (Write Boundary)
AF2
O
FIFO #2 Programmable Almost-Full Flag (Write Boundary)
HF2
O
FIFO #2 Half-Full Flag
AE1
O
FIFO #1 Programmable Almost-Empty Flag (Read Boundary)
EF1
O
FIFO #1 Empty Flag (Read Boundary)
MBF1
O
New-Mail-Alert Flag for Mailbox #1
PFB
O
Port B Parity Flag
ACKB
O
Port B Acknowledge
NOTE:
1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
7
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
ABSOLUTE MAXIMUM RATINGS 1
PARAMETER
RATING
Supply Voltage to VSS Potential
–0.5 V to 7 V
Signal Pin Voltage to V SS Potential 3
–0.5 V to VCC + 0.5 V
DC Output Current
± 40 mA
2
Storage Temperature Range
–65oC to 150oC
Power Dissipation (Package Limit)
2 Watts (Quad Flat Pack)
NOTES:
1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for
transient conditions only. Functional operation of the device at these or any other conditions outside those indicated in the ‘Operating Range’
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
3. Negative undershoot of 1.5 V in amplitude is permitted for up to 10 ns, once per cycle.
OPERATING RANGE
SYMBOL
PARAMETER
TA
Temperature, Ambient
Vcc
Vss
Supply Voltage
Supply Voltage
Logic LOW
1
Input Voltage
Logic HIGH
Input Voltage
VIL
VIH
MIN
MAX
0
70
UNIT
4.5
0
5.5
0
C
V
V
– 0.5
0.8
V
2.2
Vcc + 0.5
V
o
NOTE:
1. Negative undershoot of 1.5 V in amplitude is permitted
for up to 10 ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS (OVER OPERATING RANGE)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ILI
Input Leakage Current
VCC = 5.5 V, VIN = 0 V To VCC
–10
–
10
µA
ILO
I/O Leakage Current
OE ≥ VIH, 0 V ≤ V OUT ≤ VCC
–10
–
10
µA
VOL
Logic LOW Output Voltage
IOL = 8.0 mA
–
–
0.4
V
VOH
Logic HIGH Output Voltage
IOH = –8.0 mA
2.4
–
–
V
Measured at fCC = MAX
–
180
280
mA
1, 2
ICC
Average Supply Current
ICC2
Average Standby Supply
Current 1, 3
All Inputs = VIHMIN (Clocks idle)
–
13
25
mA
ICC3
Power-Down Supply
Current 1
All Inputs = VCC – 0.2 V (Clocks idle)
–
0.002
1
mA
ICC4
Power-Down Supply
Current 1, 3
All Inputs = VCC – 0.2 V
(Clocks running at fCC = MAX)
–
10
25
mA
NOTES:
1. ICC, ICC2, ICC3, and ICC4 are dependent upon actual output loading, and ICC, ICC4 are also dependent on cycle rates. Specified values are with
outputs open (for ICC: CL = 0 pF); and, for ICC and I CC4, operating at minimum cycle times.
2. ICC (MAX.) using VCC = MAX = 5.5 V and ‘worst case’ data pattern. ICC (TYP.) using VCC = 5 V and ‘average’ data pattern.
3. ICC2 (TYP.) and I CC4 (TYP.) using VCC = 5 V and TA = 25°C.
8
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
+5 V
RATING
Input Rise and Fall Times
(10% to 90%)
5 ns
Output Reference Levels
1.5 V
Input Timing Reference Levels
1.5 V
Output Load, Timing Tests
DEVICE
UNDER
TEST
240 Ω
30 pF *
Figure 5
NOTE: * = Includes jig and scope capacitances
CAPACITANCE 1,2
PARAMETER
470 Ω
VSS to 3 V
543611-14
Figure 4. Output Load Circuit
RATING
CIN (Input Capacitance)
8 pF
COUT (Output Capacitance)
8 pF
NOTES:
1. Sample tested only.
2. Capacitances are maximum values at 25oC, measured at 1.0 MHz, with VIN = 0 V.
9
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
AC ELECTRICAL CHARACTERISTICS 1 (VCC = 5 V ± +10%, TA = 0°C to 70°C)
SYMBOL
fCC
tCC
tCH
tCL
tDS
tDH
tES
tEH
tRWS
tRWH
tRQS
tRQH
tAS
tAH
tWSS
tWSH
tA
tACK
tOH
tZX
tXZ
tEF
tFF
tHF
tAE
tAF
tMBF
tPF
tRS
tRSS
tRSH
tRF
tFRL
tFWL
tBS
tBH
tBA
tSKEW1
tSKEW2
DESCRIPTION
Clock Cycle Frequency
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Read/Write Setup Time
Read/Write Hold Time
Request Setup Time
Request Hold Time
Address Setup Time 2
Address Hold Time 2
Width Select Setup Time
Width Select Hold Time 3
Data Output Access Time
Acknowledge Access Time
Output Hold Time
Output Enable Time, OE LOW to
3
D0 – D35 Low-Z
Output Disable Time, OE HIGH
to D0 – D35 High-Z 3
Clock to EF Flag Valid
Clock to FF Flag Valid
Clock to HF Flag Valid
Clock to AE Flag Valid
Clock to AF Flag Valid
Clock to MBF Flag Valid
Data to Parity Flag Valid 4
Reset/Retransmit Pulse Width 5
Reset/Retransmit Setup Time 6
Reset/Retransmit Hold Time 6
Reset LOW to Flag Valid
First Read Latency 7
First Write Latency 8
Bypass Data Setup
Bypass Data Hold
Bypass Data Access
Skew Time Read-to-Write Clock
Skew Time Write-to-Read Clock
–18
–20
–25
–30
–35
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
—
18
7
7
7.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
7.5
0.5
5.5
0.5
—
—
4
55
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
9.5
—
—
20
8
8
7.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
7.5
0.5
5.5
0.5
—
—
4
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13.8
9.5
—
—
25
10
10
9
0.5
7.5
0.5
7.5
0.5
7.5
0.5
9
0.5
7.5
0.5
—
—
4
40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16
13
—
—
30
12
12
10
0.5
8.5
0.5
8.5
0.5
8.5
0.5
10
0.5
8.5
0.5
—
—
4
33
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20
16
—
—
35
15
15
12
0.5
10.5
0.5
10.5
0.5
10.5
0.5
12
0.5
10.5
0.5
—
—
4
28.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25
18
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
—
1.5
—
2
—
3
—
3
—
ns
—
9
—
9
—
12
—
15
—
20
ns
—
—
—
—
—
—
—
18
15
7.2
—
18
18
8.5
2
—
14
14
14
14
14
14.5
14.5
10
14
—
—
—
21
—
—
—
—
15.5
—
—
—
—
—
—
—
—
—
20
16
8
—
20
20
8.5
2
—
14.5
14.5
14.5
14.5
14.5
15
15
10
14
—
—
—
21
—
—
—
—
16
–
—
—
—
—
—
—
—
—
25
20
10
—
25
25
10
3
—
19
19
19
19
19
19
19
13
17
—
—
—
25
—
—
—
—
18
—
—
—
—
—
—
—
—
—
30
25
15
—
30
30
13
4
—
22
22
22
22
22
22
22
18
20
—
—
—
30
—
—
—
—
23
—
—
—
—
—
—
—
—
—
35
30
20
—
35
35
15
5
—
27
27
27
27
27
27
27
23
25
—
—
—
35
—
—
—
—
28
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Timing measurements performed at ‘AC Test Condition’ levels.
2. tAS, tAH address setup times and hold times need only be satisfied at clock edges which occur while the corresponding enables are being asserted.
3. Values are guaranteed by design; not currently production tested.
4. Measured with Parity Flag operating in flowthrough mode.
5. When CKA or CKB is enabled; t RS = tRSS + t CH + t RSH.
6. tRSS and/or tRSH need not be met unless a rising edge of CKA occurs while ENA is being asserted, or else a rising edge of CKB occurs while
ENB is being asserted.
7. tFRL is the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data.
8. tFWL is the minimum first-read-to-first-write delay, following a full condition, which is required to assure successful writing of data.
10
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
Table 1. Resource-Register Addresses
OPERATIONAL DESCRIPTION
Reset
The device is reset whenever the asynchronous Reset
(RS) input is taken LOW, and at least one rising edge and
one falling edge of both CKA and CKB occur while RS is
LOW. A reset operation is required after power-up, before
the first write operation may occur. The LH543611/21 is
fully ready for operation after being reset. No device
programming is required if the default states described
below are acceptable.
A reset operation initializes the read-address and
write-address pointers for FIFO #1 and FIFO #2 to those
FIFO’s first physical memory locations. If the respective
outputs are enabled, the initial contents of these first
locations appear at the outputs. FIFO and mailbox status
flags are updated to indicate an empty condition. In
addition, the programmable-status-flag offset values are
initialized to eight. Thus, the AE1/AE2 flags get asserted
within eight locations of an empty condition, and the
AF1/AF2 flags likewise get asserted within eight locations
of a full condition, for FIFO #1/FIFO #2 respectively.
Bypass Operation
During reset (whenever RS is LOW) the device acts
as a registered transceiver, bypassing the internal FIFO
memories. Port A acts as the master port. A write or read
operation on Port A during reset transfers data directly to
or from Port B. Port B is considered to be the slave, and
cannot perform write or read operations independently on
its own during reset.
The direction of the bypass data transmission is determined by the R/WA control input, which does not get
overridden by the RS input. Here, a ‘write’ operation
means passing data from Port A to Port B, and a ‘read’
operation means passing data from Port B to Port A.
The bypass capability may be used to pass initialization or configuration data directly between a master processor and a peripheral device during reset.
Address Modes
Address pins select the device resource to be
accessed by each port. Port A has three resource-register-select inputs, A0A, A 1A, and A2A, which select between
FIFO access, mailbox-register access, control-register
access, and programmable flag-offset-value-register access. Port B has a single address input, A0B, to select
between FIFO access or mailbox-register access.
The status of the resource-register-select inputs is
sampled at the rising edge of an enabled clock (CKA or
CK B). Resource-register select-input address definitions
are summarized in Table 1.
A2A
A1A
A0A
RESOURCE
PORT A
H
H
H
FIFO
H
H
L
Mailbox
H
L
H
H
L
L
L
H
H
AE1 Flag Offset Register
L
H
L
AF1 Flag Offset Register
L
L
H
AE2 Flag Offset Register
L
L
AF2 Flag Offset Register
L
AF2, AE2, AF1, AE1 Flag Offsets
Register (36-Bit Mode)
Control Register FlagSynchronization and Parity
Operating Mode
A0B
RESOURCE
PORT B
H
FIFO
L
Mailbox
Control Register
The eighteen Control-Register bits govern the synchronization mode of the fullness-status flags at each
port, the choice of odd or even parity at both ports, the
enabling of parity generation for data flow at each port,
the optional latching behavior of the parity-error flags at
each port, and the selection of a full-word or half-word or
single-byte field for parity checking. A reset operation
initializes the LH543611/21 Control Register for
LH5420/LH543601-compatible operation, but it may be
reprogrammed at will at any time during LH543611/21
operation.
FIFO Write
Port A writes to FIFO #1, and Port B writes to FIFO #2.
A write operation is initiated on the rising edge of a clock
(CKA or CKB) whenever: the appropriate enable (ENA or
ENB) is held HIGH; the appropriate request (REQA or
REQB) is held HIGH; the appropriate Read/Write control
(R/WA or R/WB) is held LOW; the FIFO address is
selected for the address inputs (A2A – A0A or A0B); and
the prescribed setup times and hold times are observed
for all of these signals. Setup times and hold times must
also be observed on the data-bus pins (D0A – D35A or
D0B – D35B).
Normally, the appropriate Output Enable signal (OEA
or OEB) is HIGH, to disable the outputs at that port, so
that the data word present on the bus from external
sources gets stored. However, a ‘loopback’ mode of
operation also is possible, in which the data word supplied
by the outputs of one internal FIFO is ‘turned around’ at
the port and read back into the other FIFO. In this mode,
the outputs at the port are not disabled. To remain within
specification for all timing parameters, the Clock Cycle
Frequency must be reduced slightly below the value
11
LH543611/21
OPERATIONAL DESCRIPTION (cont’d)
which otherwise would be permissible for that speed
grade of LH543611/21.
When a FIFO full condition is reached, write operations
are locked out. Following the first read operation from a
full FIFO, another memory location is freed up, and the
corresponding Full Flag is deasserted (FF = HIGH). The
first write operation should begin no earlier than a First
Write Latency (tFWL) after the first read operation from a
full FIFO, to ensure that correct read data are retrieved.
(See Figures 33 and 34.)
FIFO Read
Port A reads from FIFO #2, and Port B reads from FIFO
#1. A read operation is initiated on the rising edge of a
clock (CKA or CKB) whenever: the appropriate enable
(ENA or ENB) is held HIGH; the appropriate request
(REQA or R EQ B) is held HIGH; the appropriate
Read/Write control (R/WA or R/WB) is held HIGH;
the FIFO address is selected for the address inputs
(A2A – A0A or A0B); and the prescribed setup times and
hold times are observed for all of these signals. Read data
becomes valid on the data-bus pins (D0A – D35A or
D0B – D35B) by a time tA after the rising clock (CKA or
CK B) edge, provided that the data outputs are enabled.
OEA and OEB are assertive-LOW, asynchronous, Output Enable control input signals. Their effect is only to
enable or disable the output drivers of the respective port.
Disabling the outputs does not disable a read operation;
data transmitted to the corresponding output register will
remain available later, when the outputs again are enabled, unless it subsequently is overwritten.
When an empty condition is reached, read operations
are locked out until a valid write operation(s) has loaded
additional data into the FIFO. Following the first write to
an empty FIFO, the corresponding empty flag (EF) will be
deasserted (HIGH). The first read operation should begin
no earlier than a First Read Latency (tFRL) after the first
write to an empty FIFO, to ensure that correct read data
words are retrieved. (See Figures 31 and 32.)
Dedicated FIFO Status Flags
Six dedicated FIFO status flags are included for Full
(FF1 and FF2), Half-Full (HF1 and HF2), and Empty (EF1
and EF2). FF1, HF1, and EF1 indicate the status of FIFO
#1; and FF2, HF2, and EF2 indicate the status of FIFO #2.
A Full Flag is asserted following the first subsequent
rising clock edge for a write operation which fills the FIFO.
A Full Flag is deasserted following the first subsequent
falling clock edge for a read operation to a full FIFO. A
Half-Full Flag is updated following the first subsequent
rising clock edge of a read or write operation to a FIFO
which changes its ‘half-full’ status. An Empty Flag is
asserted following the first subsequent rising clock edge
for a read operation which empties the FIFO. An Empty
Flag is deasserted following the falling clock edge for a
write operation to an empty FIFO.
12
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
Programmable Status Flags
Four programmable FIFO status flags are provided,
two for Almost-Full (AF1 and AF2), and two for AlmostEmpty (AE1 and AE2). Thus, each port has two programmable flags to monitor the status of the two internal FIFO
buffer memories. The offset values for these flags are
initialized to eight locations from the respective FIFO
boundaries during reset, but can be reprogrammed over
the entire FIFO depth.
An Almost-Full Flag is asserted following the first subsequent rising clock edge after a write operation which
has partially filled the FIFO up to the ‘almost-full’ offset
point. An Almost-Full Flag is deasserted following the first
subsequent falling clock edge after a read operation
which has partially emptied the FIFO down past the
‘almost-full’ offset point. An Almost-Empty Flag is
asserted following the first subsequent rising clock edge
after a read operation which has partially emptied
the FIFO down to the ‘almost-empty’ offset point. An
Almost-Empty Flag is deasserted following the first subsequent falling clock edge after a write operation which
has partially filled the FIFO up past the ‘almost-empty’
offset point.
Flag offsets may be written or read through the Port A
data bus. All four programmable FIFO status flag offsets
can be set simultaneously through a single 36-bit status
word; or, each programmable flag offset can be set individually, through one of four nine-bit (LH543611) or ten-bit
(LH543621) status words. Tables 3a and 3b illustrate the
data format for flag-programming words. Note that when
all four offsets are set simultaneously in an LH543621,
the settings are limited to magnitudes expressible in nine
bits; for larger offset values, the individual setting option
must be used. (See Figure 3b.)
Also, Tables 4a and 4b define the meaning of each of
the five flags, both the dedicated flags and the programmable flags, for the LH543611 and LH543621 respectively.
NOTE: Control inputs which may affect the computation
of flag values at a port generally should not change while
the clock for that port is HIGH, since some updating of
flag values takes place on the falling edge of the clock.
Mailbox Operation
Two mailbox registers are provided for passing system
hardware or software control/status words between ports.
Each port can read its own mailbox and write to the other
port’s mailbox. Mailbox access is performed on the rising
edge of the controlling FIFO’s clock, with the mailbox
address selected and the enable (ENA or ENB) HIGH.
That is, writing to Mailbox Register #1, or reading from
Mailbox Register #2, is synchronized to CKA; and writing
to MailboxRegister #2, or reading from Mailbox Register
#1, is synchronized to CKB.
The R/WA/B and OEA/B pins control the direction and
availability of mailbox-register accesses. Each mailbox
register has its own New-Mail-Alert Flag (MBF1 and
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
OPERATIONAL DESCRIPTION (cont’d)
MBF2), which is synchronized to the reading port’s clock.
These New-Mail-Alert Flags are status indicators only,
and cannot inhibit mailbox-register read or write operations.
Request Acknowledge Handshake
A synchronous request-acknowledge handshake feature is provided for each port, to perform boundary synchronization between asynchronously-operated ports.
The use of this feature is optional. When it is used, the
Request input (REQA/B) is sampled at a rising clock edge.
With REQA/B HIGH, R/WA/B determines whether a FIFO
read operation or a FIFO write operation is being requested. The Acknowledge output (ACKA/B) is updated
during the following clock cycle(s). ACKA/B meets the
setup and hold time requirements of the Enable input
(ENA or ENB). Therefore, ACKA/B may be tied back to the
enable input to directly gate FIFO accesses, at a slight
decrease in maximum operating frequency.
The assertion of ACKA/B signifies that REQA/B was
asserted. However, ACKA/B does not depend logically on
EN A/B; and thus the assertion of ACKA/B does not prove
that a FIFO write access or a FIFO read access actually
took place. While REQA/B and ENA/B are being held
HIGH, ACKA/B may be considered as a synchronous,
predictive boundary flag. That is, ACKA/B acts as a
synchronized predictor of the Almost-Full Flag AF for write
operations, or as a synchronized predictor of the AlmostEmpty Flag AE for read operations.
Outside the ‘almost-full’ region and the ‘almost-empty’
region, ACKA/B remains continuously HIGH whenever
REQA/B is held continuously HIGH. Within the ‘almost-full’
region or the ‘almost-empty’ region, ACKA/B occurs only
on every third cycle, to prevent an overrun of the FIFO’s
actual full or empty boundaries and to ensure that the tFWL
(first write latency) and tFRL (first read latency) specifications are satisfied before ACKA/B is received.
The ‘almost-full region’ is defined as ‘that region, where
the Almost-Full Flag is being asserted’; and the ‘almostempty region’ as ‘that region, where the Almost-Empty
Flag is being asserted.’ Thus, the extent of these ‘almost’
regions depends on how the system has programmed the
offset values for the Almost-Full Flags and the AlmostEmpty Flags. If the system has not programmed them,
then these offset values remain at their default values,
eight in each case.
If a write attempt is unsuccessful because the corresponding FIFO is full, or if a read attempt is unsuccessful
because the corresponding FIFO is empty, ACKA/B is not
asserted in response to REQA/B.
LH543611/21
If the REQ/ACK handshake is not used, then the
REQA/B input may be used as a second enable input, at
a possible minor loss in maximum operating speed. In this
case, the ACKA/B output may be ignored.
WARNING: Whether or not the REQ/ACK handshake is
being used, the REQA/B input for a port must be asserted
for that port to function at all – for FIFO, mailbox, or databypass operation.
Data Retransmit
A retransmit operation resets the read-address pointer of
the corresponding FIFO (#1 or #2) back to the first FIFO
physical memory location, so that data may be reread. The
write pointer is not affected. The status flags are updated;
and a block of up to 512 or 1024 data words, which
previously had been written into and read from a FIFO, can
be retrieved. The block to be retransmitted is bounded by
the first FIFO memory location, and the FIFO memory
location addressed by the write pointer. FIFO #1 retransmit
is initiated by strobing the RT1 pin LOW. FIFO #2 retransmit
is initiated by strobing the RT2 pin LOW. Read and write
operations to a FIFO should be stopped while the corresponding Retransmit signal is being asserted.
Parity Checking
The Parity Check Flags, PFA and PFB, are asserted
(LOW) whenever there is a parity error in the data word
present on the Port A data bus or the Port B data bus
respectively. The inputs to the parity-evaluation logic
come directly (via isolation transistors) from the data-bus
bonding pads, in each case. Thus, PFA and PFB provide
parity-error indications for whatever 36-bit words are
present at Port A and Port B respectively, regardless of
whether those words originated within the LH543611/21
or in the external system.
The four bytes of a 36-bit data word are grouped as
D0 – D8, D9 – D17, D18 – D26, and D27 – D35. The parity of
each nine-bit byte is individually checked, and the four
single-bit parity indications are logically ORed and inverted
to produce the Parity-Flag output.
If the Parity Policy bit (Control-Register bit 09) is HIGH,
then parity at Port B will be computed over the field
defined by the Word-Width Selection control inputs WS0
and WS1, and then may be for full-words, for half-words,
or for single bytes. Otherwise, parity will be computed
over full-words regardless of the setting of WS0 and WS1.
Parity checking is initialized for odd parity at reset, but
can be reprogrammed for even parity or for odd parity
during operation. Control-Register bit 00 (zero) selects
the parity mode, odd or even. (See Tables 3, 5, and 6, and
Figure 10.)
13
LH543611/21
All nine bits of each byte are treated alike by the parity
logic. The byte parity over the nine bits is compared with
the Parity Mode bit in the Control Register, to generate a
byte-parity-error indication. Then, the four byte-parityerror signals are NORed together, to compute the assertive-LOW parity-flag value. This value may pass through
to the output pin on a flowthrough basis, or it may be
latched, according to the setting of the Control-Register
latching bit for that port (bit 02 or bit 11). (See Figure 6 for
an example of parity checking.)
Parity Generation
Unlike parity checking, parity generation at a port
operates only when it is explicitly invoked by setting the
corresponding Control-Register bit for that port (bit 01 or
bit 10) HIGH. The presumed division of words into bytes
still remains the same as for parity checking. However, it
is no longer true that all nine bits of each byte are treated
alike; now, the most-significant bit of each byte is explicitly
designated as the parity bit for that byte. The parity-generation process records a new value into that bit position
for each byte passing through the port. (See Figure 6 for
an example of parity generation.)
If the Parity Policy bit (Control Register bit 09), is HIGH,
parity at Port B will be generated for full-words, for halfwords, or for single bytes according to the setting of the
Word-Width Selection control inputs WS 0 and WS1. Otherwise, parity will be generated for full-words regardless
of the setting of WS0 and WS1.
The parity bits generated may be even or odd, according to the setting of Control-Register bit 00, which is the
same bit that governs their interpretation during parity
checking.
Word-Width Selection and Byte-Order Reversal on
Port B
The word width of data access on Port B is selected
by the WS0 and WS1 control inputs. WS0 and WS 1 both
are tied HIGH for 36-bit access; they both are tied LOW
for single-byte access. For double-byte access, WS1 is
tied LOW; WS0 is tied HIGH for straight-through transmission of 36-bit words, or tied LOW for on-the-fly byte-order
reversal of the four bytes in the word (‘big-endian ↔
little-endian conversion’). (See Table 2a and 2b.)
In the single-byte-access or double-byte-access modes,
FIFO write operations on Port B essentially pack the data to
form 36-bit words, as viewed from Port A. Similarly, singlebyte or double-byte FIFO read operations on Port B essentially unpack 36-bit words through a series of shift
operations. FIFO status flags are updated following the last
access which forms a complete 36-bit transfer.
14
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
Since the values for each status flag are computed by
logic directly associated with one of the two FIFO-memory
arrays, and not by logic associated with Port B, the flag
values reflect the array fullness situation in terms of complete 36-bit words, and not in terms of bytes or double bytes.
However, there is no such restriction for switching from
writing to reading, or from reading to writing, at Port B. As
long as tRWS, tDS, and tA are satisfied, R/WB may change
state after any single-byte or double-byte access, and not
only after a full 36-bit-word access.
Also, WS0 and WS1 may be changed between fullwords during FIFO operation, without the need for any
reset operation, or for passing any dummy words on
through in advance of real data. If such a change is made
other than at a full-word boundary, however, at least one
dummy word should be used.
Also, the word-width-matching feature continues to
operate properly in ‘loopback’ mode.
Note that the programmable word-width-matching feature is only supported for FIFO accesses. Mailbox and
Data Bypass operations do not support word-width
matching between Port A and Port B. Tables 2a and 2b
and Figures 7, 8, and 9, summarize word-width selection
for Port B.
Table 2a. Port B Word-Width Selection
WS1
WS0
PORT B DATA WIDTH
H
H
36-Bit
H
L
36-Bit with
Byte-Order Reversal
L
H
18-Bit
L
L
9-Bit
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
PARITY CHECKING
DA/B35
DA/B0
Output word:
100111100
Odd parity:
Parity of Bytes = 0110; (1 = Byte Parity Error) PF = L
Even parity:
Parity of Bytes = 1001; (1 = Byte Parity Error) PF = L
000111100
100111000
000111000
PARITY GENERATION
DA/B35
DA/B0
Input word:
100111100
000111100
100111000
000111000
Output, odd parity:
100111100
100111100
000111000
000111000
Output, even parity:
000111100
000111100
100111000
100111000
Figure 6. Example of Parity Checking and Generation
Table 2b. Bus Funneling/Defunneling *
DA[35:0]
0
1
B3
B7
B2 B1
B6 B5
B0
B4
0
1
2
3
4
WS = 3 (HH)
WS = 2 (HL)
WS = 1 (LH)
DB[35:0]
DB[35:0]
DB[35:18] DB[17:0]
B3 B2 B1 B0 B0 B1
B7 B6 B5 B4 B4 B5
B2 B3 B3
B6 B7 B1
B7
B5
B2
B0
B6
B4
B1
B3
B5
B7
WS = 0 (LL)
B0
B2
B4
B6
DB[35:9]
DB[8:0]
B3 B2 B1
B0 B3 B2
B1 B0 B3
B2 B1 B0
B7 B6 B5
B0
B1
B2
B3
B4
* NOTE: B0, B1, . . ., represent data bytes.
0
1
2
...
DA26
DB26
...
...
DB27
DA18
DB18
DA17
DB17
...
B4
BYTE #5
DA27
DA9
DB9
DA8
DB8
...
B0
BYTE #1
B5
BYTE #6
DB35
...
B1
BYTE #2
B6
BYTE #7
DA35
...
B2
BYTE #3
B7
BYTE #8
...
Bus Example: Intel, DEC, etc.
B3
BYTE #4
OUTPUT: WS[1:0]= 2 (HL)
LH543611/21
DA0
DB0
B0
BYTE #1
B4
BYTE #5
B1
BYTE #2
B5
BYTE #6
B2
BYTE #3
B6
BYTE #7
B3
BYTE #4
B7
BYTE #8
0
1
CKA
Bus Example: IBM, Motorala, etc.
INPUT
2
3
CKB
543611-52
Figure 7. Example of 36-to-36 Byte Order Reversal
15
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
PORT B WORD-WIDTH SELECTION
36-Bit Data Stream
18-Bit Data Streams
Bits 18-35
(2nd Halfword)
D35A
18
D18A
Bits
(2n 18-35
dH
alfw
ord
D35B
2nd Halfword, then 1st Halfword
18
D18B
7
0-1 ord)
Bits Halfw
t
s
(1
)
PORT
A
PORT
B
D17A
D17B
18
1st Halfword, then 2nd Halfword
18
Bits 0-17
(1st Halfword)
D0A
D0B
543611-15
Figure 8a. 36-to-18 Funneling Through FIFO #1
36-Bit Data Stream
D35A
9
9-Bit Data Streams
Bits 27-35
(4th Byte)
D35B
9
D27A
4th Byte, then 1st Byte, then 2nd Byte, then 3rd Byte
D27B
D26A
9
Bits 18-26
(3rd Byte)
D26B
9
D18A
3rd Byte, then 4th Byte, then 1st Byte, then 2nd Byte
D18B
PORT
A
D17A
9
Bits 9-17
(2nd Byte)
D17B
9
D9A
PORT
B
2nd Byte, then 3rd Byte, then 4th Byte, then 1st Byte
D9B
D8A
9
Bits 0-8
(1st Byte)
D0A
D8B
9
1st Byte, then 2nd Byte, then 3rd Byte, then 4th Byte
D0B
543611-16
Figure 8b. 36-to-9 Funneling Through FIFO #1
NOTES:
1. The heavy black borders on register segments indicate the main
data path, suitable for most applications. Alternate paths feature
a different ordering of bytes within a word, at Port B.
2. The funneling process does not change the ordering of bits within
a byte. Halfwords (Figure 8a) or bytes (Figure 8b) are transferred in parallel form from Port A to Port B.
16
3.
The word-width setting may be changed during system operation;
however, two clock intervals should be allowed for these signals
to settle, before again attempting to read D0B – D35B. Also, incomplete data words may occur, when the word width is
changed from shorter to longer at an inappropriate point in the
data block passing through the FIFO.
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
PORT B WORD-WIDTH SELECTION
36-Bit Data Stream
18-Bit Data Stream
D35A
D35B
Bits
(2n 18-35
dH
alfw
ord
18
D18A
18
D18B
)
PORT
A
PORT
B
D17A
D17B
18
1st Halfword, then 2nd Halfword
18
Bits 0-17
(1st Halfword)
D0A
D0B
543611-17
Figure 9a. 18-to-36 Defunneling Through FIFO #2
36-Bit Data Stream
9-Bit Data Stream
D35A
D35B
9
Bits 27-35
(4th Byte)
9
D27A
D27B
D26A
D26B
9
Bits 18-26
(3rd Byte)
9
D18A
D18B
PORT
A
D17A
D17B
9
Bits 9-17
(2nd Byte)
9
D9A
D9B
D8A
D8B
9
Bits 0-8
(1st Byte)
9
D0A
PORT
B
1st Byte, then 2nd Byte, then 3rd Byte, then 4th Byte
D0B
543611-18
Figure 9b. 9-to-36 Defunneling Through FIFO #2
NOTES:
1. The heavy black borders on register segments indicate the only
data paths used. The other byte segments of Port B do not participate in the data path during defunneling.
2. The defunneling process does not change the ordering of bits
within a byte. Halfwords (Figure 9a) or bytes (Figure 9b) are
transferred in parallel form from Port B to Port A.
3.
The word-width setting may be changed during system operation;
however, two clock intervals should be allowed for these signals
to settle, before again attempting to send data. Also, incomplete
data words may occur, when the word width is changed from
shorter to longer at an inappropriate point in the data block passing through the FIFO.
17
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
Table 3a. LH543611 Resource-Register Programming
RESOURCEREGISTER
ADDRESS
A2A
A1A
RESOURCE-REGISTER CONTENTS
A0A
NORMAL FIFO OPERATION
H
H
H
D35A
D0A
X...
...X
MAILBOX
H
H
L
D35A
D0A
X...
...X
AF2, AE2, AF1, AE1 FLAG REGISTER (36-BIT MODE)
D35A . . . D27A
H
L
H
AF2 Offset
1
D26A . . . D18A
AE2 Offset
D17A . . . D9A
1
AF1
D8A . . . D0A
Offset 1
AE1 Offset 1
CONTROL REGISTER: FLAG SYNCHRONIZATION, PARITY CONFIGURATION
H
L
L
D35A
D18A
X...
...X
D17A
D9A
Port B Control 3
D8A
D1A
Port A Control 3
9-BIT AE1 FLAG OFFSET REGISTER
L
H
H
D35A
D9A
D8A . . . D0A
X...
...X
AE1 Offset 1
D35A
D9A
D8A . . . D0A
X...
..X
AF1 Offset 1
D35A
D9A
D8A . . . D0A
X...
...X
AE2 Offset 1
D35A
D9A
D8A . . . D0A
X...
...X
AF2 Offset 1
9-BIT AF1 FLAG OFFSET REGISTER
L
H
L
9-BIT AE2 FLAG OFFSET REGISTER
L
L
H
9-BIT AF2 FLAG OFFSET REGISTER
L
L
L
NOTES:
1. All four programmable-flag-offset values are initialized to eight (8) during a reset operation.
2. Parity Mode: Odd parity = HIGH; even parity = LOW. The parity mode is initialized to odd during a reset operation.
3. See Tables 5 and 6 and Figure 10 for the detailed format of the Control Register word.
18
D0A
PM 2
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
Table 3b. LH543621 Resource-Register Programming
RESOURCEREGISTER
ADDRESS
A2A
A1A
RESOURCE-REGISTER CONTENTS
A0A
NORMAL FIFO OPERATION
H
H
H
D35A
D0A
X...
...X
MAILBOX
H
H
L
D35A
D0A
X...
...X
AF2, AE2, AF1, AE1 FLAG REGISTER (36-BIT MODE) 4
H
L
H
D35A . . . D27A
D26A . . . D18A
D17A . . . D9A
D8A . . . D0A
AF2 Offset 1
AE2 Offset 1
AF1 Offset 1
AE 1 Offset 1
CONTROL REGISTER: FLAG SYNCHRONIZATION, PARITY CONFIGURATION
H
L
L
D35A
D18A
X...
...X
D17A
D9A
Port B Control 3
D8A
D1A
Port A Control 3
D0A
PM 2
10-BIT AE1 FLAG OFFSET REGISTER
L
H
H
D35A
D10A
D9A . . . D0A
X...
...X
AE1 Offset 1
D35A
D10A
D9A . . . D0A
X...
...X
AF1 Offset 1
D35A
D10A
D9A . . . D0A
X...
...X
AE 2 Offset 1
D35A
D10A
D9A . . . D0A
X...
...X
AF2 Offset 1
10-BIT AF1 FLAG OFFSET REGISTER
L
H
L
10-BIT AE2 FLAG OFFSET REGISTER
L
L
H
10-BIT AF2 FLAG OFFSET REGISTER
L
L
L
NOTES:
1. All four programmable-flag-offset values are initialized to eight (8) during a reset operation.
2. Parity Mode: Odd parity = HIGH; even parity = LOW. The parity mode is initialized to odd during a reset operation.
3. See Tables 5 and 6 and Figure 10 for the detailed format of the Control Register word.
4. For 36-bit Flag Register Control word, with only only 9 bits to program per flag offset:
Offset is limited to a value of 511. If a greater value is desired, individual flag offset register programming is required.
19
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
Table 4a. LH543611 Flag Definition Table
VALID READ CYCLES REMAINING
FLAG
FLAG = LOW
VALID WRITE CYCLES REMAINING
FLAG = HIGH
FLAG = LOW
FLAG = HIGH
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
FF
512
512
0
511
0
0
1
512
AF
512-p
512
0
511-p
0
p
p+1
512
HF
257
512
0
256
0
255
256
512
AE
0
q
q+1
512
512-q
512
0
511-q
EF
0
0
1
512
512
512
0
511
NOTE:
q = Programmable-Almost-Empty Offset value. (Default value: q = 8.)
p = Programmable-Almost-Full Offset value. (Default value: p = 8.)
Table 4b. LH543621 Flag Definition Table
VALID READ CYCLES REMAINING
FLAG
FLAG = LOW
VALID WRITE CYCLES REMAINING
FLAG = HIGH
FLAG = HIGH
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
FF
1024
1024
0
1023
0
0
1
1024
AF
1024-p
1024
0
1023-p
0
p
p+1
1024
HF
513
1024
0
512
0
511
512
1024
AE
0
q
q+1
1024
1024-q
1024
0
1023-q
EF
0
0
1
1024
1024
1024
0
1023
NOTE:
q = Programmable-Almost-Empty Offset value. (Default value: q = 8.)
p = Programmable-Almost-Full Offset value. (Default value: p = 8.)
20
FLAG = LOW
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
Table 5. Control-Register Format
COMMAND
PORT REGISTER
BITS
CODE
VALUE
FLAG
AFTER AFFECTED,
RESET
IF ANY
A correct 9-bit byte has an even
number of ones.
H
ODD parity in effect.
A correct 9-bit byte has an odd number
of ones.
L
Disable Port A parity generation.
No overwriting of parity bits.
Enable Port A parity generation.
Parity bit over eight least-significant bits
of each byte is overwritten into the
most-significant bit of that byte.
Port A parity-error flag operates
’flowthrough.’
PFA is subject to transient glitches
while data bus is changing.
Port A parity-error flag is latched
by CKA.
PFA is subject to transient glitches
while data bus is changing.
00
A
01
H
H
L
PFA, PFB
–
L
02
L
PFA
H
03
L
L
EF2
H
04
L
L
H
AE2
LL
05, 06
LH
LL
HF1
HL, HH
07
08
L
H
L
L
L
AF1
FF1
Asynchronous flag clocking.
Set and reset by ↑ CKB.
Synchronous flag clocking.
Set by ↑ CKA, reset by ↑ CKB.
Asynchronous flag clocking.
Set and reset by ↑ CKB.
Synchronous flag clocking by
Port B clock.
Set and reset by ↑ CKA.
Synchronous flag clocking by
Port A clock.
Set by ↑ CKA, reset by ↑ CKB.
Asynchronous flag clocking.
Set and reset by ↑ CKA.
Synchronous flag clocking.
Set by ↑ CKA, reset by ↑ CKB.
Asynchronous flag clocking.
H
Parity check computed over halfword or single-byte according to
WS1 – WS0 setting.
Full-word, half word, or single-byte
parity-error indication according to
WS1 – WS0 setting.
L
Disable Port B parity generation.
No overwriting of parity bits.
Enable Port B parity generation.
Parity bit over eight least-significant bits
of each byte is overwritten into the
most-significant bit of that byte.
Port B parity-error flag operates
’flowthrough’.
PFB is subject to transient glitches
while data bus is changing.
Port B parity-error flag is latched
by CKB.
PFB remains steady until its value
should change.
Set by ↑ CKB, reset by ↑ CKA.
Asynchronous flag clocking.
Set and reset by ↑ CKB.
Synchronous flag clocking.
Set by ↑ CKB, reset by ↑ CKA.
Asynchronous flag clocking.
Set and reset by ↑ CKA.
Synchronous flag clocking.
Set and reset by ↑ CKA.
Asynchronous flag clocking.
Set and reset by ↑ CKA.
Synchronous flag clocking by Port A
clock.
Set and reset by ↑ CKA.
Synchronous flag clocking by Port B
clock.
L
H
11
L
PFB
–
L
PFB
H
L
L
H
L
L
H
EF1
AE1
LL
14, 15
Set by ↑ CKA, reset by ↑ CKB.
Synchronous flag clocking.
L
13
Synchronous flag clocking.
Full-word parity-error indication
regardless of WS1 – WS0 setting.
09
12
Asynchronous flag clocking.
Set and reset by ↑ CKA.
Parity check computed over all
four bytes of each word.
L
B
Set by ↑ CKA, reset by ↑ CKB.
Set and reset by ↑ CKA.
H
10
NOTES
EVEN parity in effect.
L
A, B
DESCRIPTION
LH
HL, HH
LL
HF2
21
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
Table 5. Control-Register Format (cont’d)
COMMAND
PORT REGISTER
BITS
16
CODE
L
VALUE
FLAG
AFTER AFFECTED,
RESET
IF ANY
AF2
L
H
B
17
L
FF2
L
H
DESCRIPTION
NOTES
Set by ↑ CKB, reset by ↑ CKA.
Asynchronous flag clocking.
Set and reset by ↑ CKB.
Synchronous flag clocking.
Set by ↑ CKB, reset by ↑ CKA.
Asynchronous flag clocking.
Set and reset by ↑ CKB.
Synchronous flag clocking.
Table 6. Controllable Functions
TYPE
CONTROL-REGISTER BIT
DESCRIPTION
PORT A
Even/Odd
Parity
Flag Synchronization
0
PORT B
1
01
Policy for 9/18-Bit Word-Width Selection
–
9
Generation: Enable/Disable
1
10
Flag Behavior: Latched/Flowthrough
2
11
EF Synchronous/Asynchronous
3
12
AE Synchronous/Asynchronous
4
13
5–6
14–15
AF Synchronous/Asynchronous
7
16
FF Synchronous/Asynchronous
8
17
HF Synchronous-With-Write/Synchronous-With-Read
NOTE:
1. LH5420/LH543601 also have this Control-Register function. The same Control-Register bit, bit 00, controls both Port A and Port B functionality.
A
B
PARITY
E
V
E
N
O
D
D
35
0
1
LH5420/LH543601 CONTROL REGISTER (WRITE-ONLY)
(FOR COMPARISON PURPOSES)
PORT B
FLAG
SYNCHRONIZATION
35
18
17
16
HF2
15
14
P
G
E
N
P
O
L
I
C
Y
AE1 EF1 PFB
B
B
13
10
9
12
11
B
FLAG
SYNCHRONIZATION
PARITY
L
A
T
C
H
FF2 AF2
A
PORT A
PARITY
L
A
T
C
H
FF1 AF1
8
7
AE2 EF2 PFA
HF1
6
5
4
3
2
P
G
E
N
E
V
E
N
A
O
D
D
1
0
LH543611/21 CONTROL REGISTER (READ/WRITE)
543611-12
Figure 10. LH5420/LH543601 and LH543611/21
Control-Register Formats
22
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS
t RS
RS, FR1, FR2
t RSS
t RSH
t RSS
CKA
t ES
t EH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
EN A
REQA
t RSS
t RSH
t RSS
CK B
t ES
t EH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
EN B
REQB
t RF
EF, AE
t RF
HF, AF, FF, MBF
NOTES:
1. RS overrides all other input signals, except for R/WA, ENA, and REQA. It operates
asynchronously. RS, FR1, and FR2 operates whether or not ENA and/or ENB are asserted.
At least one rising edge and one falling edge of both CKA and CKB must occur while
RS is being asserted (is LOW), with timing as defined by tRSS and tRSH.
2. Otherwise, tRSS, tRSH need not be met unless the rising edge of CKA and/or CKB
occurs while that clock is enabled.
3. The parity-check even/odd selection (Control Register bit 00) is initialized to odd byte
parity at reset (HIGH). All other Control Register bits are initialized LOW. FR1 and FR2
do not alter the configuration, flags reflect the absence of data.
4. The AE and AF flag offsets are initialized to eight locations from the boundary at reset
controlled by RS.
543611-19
Figure 11. Reset Timing
23
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
RS
t RSS
t RSH
CKA
tRWS
t RWH
tRWS
t RWH
t ES
t EH
t ES
t EH
t RQS
t RQH
tRQS
tRQH
t BS
t BH
R/WA
ENA
REQ A
OEB
D0B - D35B
tA
t BA
t ZX
t OH
BYPASS DATA OUT
BYPASS IN
OEA
t BA
t OH
D0A - D35A
PREVIOUS DATA
t BS
tBH
t XZ
BYPASS
OUT
BYPASS
IN
NOTES:
1. tRSS, tRSH need not be met unless the rising edge of CKA or CKB occurs while that clock is enabled.
2. Port A is considered the master port for bypass operation. Thus, CKA, R/WA, ENA, and REQA control
the transmission of data between ports at reset.
543611-20
Figure 12. Data Bypass Timing
24
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
READ FROM
FIFO #2
READ FROM
FIFO #2
tCC
tCL
tCH
WRITE TO
FIFO #1
tCC
tCL
tCH
CKA
tRWS
t RWH
tRWS
t RWH
tRWS
t RWH
t ES
t EH
tES
tEH
t ES
t EH
t RQS
t RQH
tRQS
tRQH
tRQS
tRQH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tDS
t DH
R/WA
ENA
REQA
A2A
A1A
A0A
OEA
tA
tA
tZX
t OH
DATA OUT
N3
DATA OUT N2
t PF
t PF
VALID PF
FOR N1
t PF
DATA IN N4
t PF
VALID PF
FOR N3
VALID PF FOR N2
t PF
SYNCHRONOUS
PFA
t XZ
t OH
PREVIOUS
DATA N1
D0A - D35A
ASYNCHRONOUS
PFA
tA
t PF
VALID PF FOR N1
VALID PF
FOR N4
t PF
VALID PF FOR N2
NOTES:
1. The Port A Parity Error Flag (PFA) reflects the parity status of data present
on the data bus, after a delay tPF, when operated asynchronously.
2. The Port A Parity Error Flag (PFA) reflects the parity status of data present
on the data bus during the previous clock cycle, and meeting the setup
time at CKA, when operated synchronously.
3. The status of OEA does not gate read or write operations.
4. If OEA is left LOW during a write operation, then the previous data held in
the output latch is written back into FIFO #1.
VALID PF FOR N4
543611-21
Figure 13. Port A FIFO Read/Write
25
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
READ FROM
FIFO #1
READ FROM
FIFO #1
tCC
tCL
tCH
WRITE TO
FIFO #2
tCC
tCL
tCH
CKB
tRWS
tRWH
tRWS
t RWH
tRWS
t RWH
tES
tEH
tES
tEH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
tRQS
tRQH
tAS
tAH
tAS
tAH
tAS
tAH
tDS
tDH
R/WB
ENB
REQB
A0B
OEB
tA
tA
tZX
t OH
DATA OUT
N3
DATA OUT N2
t PF
t PF
VALID PF
FOR N1
t PF
VALID PF FOR N2
t PF
SYNCHRONOUS
PFB
tXZ
tOH
PREVIOUS
DATA N1
D0B - D35B
ASYNCHRONOUS
PFB
tA
t PF
VALID PF
FOR N3
t PF
VALID PF FOR N1
NOTES:
1. The Port B Parity Error Flag (PFB) reflects the parity status of data present
on the data bus, after a delay tPF, when operated asynchronously.
2. The Port B Parity Error Flag (PFB) reflects the parity status of data present
on the data bus during the previous clock cycle, and meeting the setup
time at CKB, when operated synchronously.
3. The status of OEB does not gate read or write operations.
4. If OEB is left LOW during a write operation, then the previous data held in
the output latch is written back into FIFO #2.
Figure 14. Port B FIFO Read/Write
26
DATA IN N4
VALID PF
FOR N4
t PF
VALID PF FOR N2
VALID PF FOR N4
543611-22
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
WRITE TO
MAILBOX #1
READ FROM
MAILBOX #2
CK A
tRWS
t RWH
tRWS
t RWH
t ES
t EH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
t AS
t AH
t AS
t AH
t AS
t AH
t AS
t AH
t AS
t AH
t AS
t AH
R/WA
EN A
REQA
A2A
A1A
A0A
t MBF
MBF2
MAXIMUM OF 2 CK B
CYCLES LATENCY
CK B
t MBF
MBF1
OEA
tA
tA
t DS
D0A - D35A
t DH
t ZX
t OH
MAILBOX IN
MAILBOX OUT
NOTES:
1. Both edges of MBF2 are synchronized to the Port A clock, CKA.
2. Both edges of MBF1 are synchronized to the Port B clock, CKB.
3. There is a maximum of two CKB clock cycles of synchronization latency before MBF1
is asserted to indicate valid new mailbox data.
4. The status of mailbox flags does not prevent mailbox read or write operations.
543611-23
Figure 15. Port A Mailbox Access
27
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
WRITE TO
MAILBOX #2
READ FROM
MAILBOX #1
CKB
tRWS
t RWH
tRWS
t RWH
t ES
t EH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
R/WB
ENB
REQB
t AS
t AH
t AS
t AH
A0B
t MBF
MBF1
MAXIMUM OF 2 CKA
CYCLES LATENCY
CKA
t MBF
MBF2
OEB
tA
t DS
D0B - D35B
t DH
t ZX
tA
t OH
MAILBOX IN
MAILBOX OUT
NOTES:
1. Both edges of MBF2 are synchronized to the Port A clock, CKA.
2. Both edges of MBF1 are synchronized to the Port B clock, CKB.
3. There is a maximum of two CKA clock cycles of synchronization latency before MBF2
is asserted to indicate valid new mailbox data.
4. The status of mailbox flags does not prevent mailbox read or write operations.
543611-24
Figure 16. Port B Mailbox Access
28
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
LOAD FLAG
POSITIONS
READ FLAG
POSITIONS
CK A
tRWS
t RWH
tRWS
t RWH
t ES
t EH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
t AS
t AH
t AS
t AH
t AS
t AH
tAS
t AH
t AS
t AH
t AS
t AH
R/WA
EN A
REQA
A2A
A1A
A0A
OEA
tA
t DS
D0A - D35A
t DH
tZX
tA
tOH
FLAG DATA IN
FLAG DATA OUT
t RF
AE1, AE2, AF1, AF2
NOTES:
1. For valid flag address codes and data formats, see Table 3.
2. If flag status is altered by flag programming, the updated flags will be valid within a time tRF.
3. The Control Register may be loaded or read back as shown here, with A2A, A1A, A0A = HLL.
543611-25
Figure 17. Flag Programming
29
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKA (CKB )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WA (R/WB )
ENA (EN B)
REQA (REQB)
t EF
t EF
EF2 (EF1)
CKB (CK A)
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WB (R/WA)
ENB (ENA )
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Empty Flags is controlled by rising clock
edges; whereas, deassertion of the Empty Flags is controlled
by falling clock edges.
543611-26
Figure 18. Empty Flag Timing, When Asynchronous
30
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CKA (CKB)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WA (R/WB)
ENA (ENB)
REQA (REQB)
tEF
tSKEW2 (4)
tEF
EF2 (EF1)
CKB (CKA)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WB (R/WA)
ENB (ENA)
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Empty Flags is controlled by rising clock
edges; whereas, internal deassertion of the Empty Flags
is controlled by falling clock edges, and their external deassertion
is controlled by rising clock edges.
4. tSKEW2 is the minimum time between a falling CKB (CKA) edge
and a rising CKA (CKB) edge for EF to change predictably during
the current clock cycle. If the time between the falling edge of
CKB (CKA) and the rising edge of CKA (CKB) is less than tSKEW2,
then it is not guaranteed that EF will change state until the next
following CKA (CKB) edge.
543611-44
Figure 19. Empty Flag Timing, When Synchronous
31
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKA (CKB )
tRWS
t RWH
t ES
t EH
t RQS
t RQH
R/WA (R/WB )
ENA (ENB )
REQA (REQB )
t AE
t AE
AE2 (AE1)
CKB (CKA )
tRWS
t RWH
t ES
t EH
t RQS
t RQH
R/WB (R/WA )
ENB (ENA )
REQ B (REQA )
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Almost-Empty Flags is controlled by rising clock
edges; whereas, deassertion of the Almost-Empty Flags is controlled
by falling clock edges.
Figure 20. Almost-Empty Flag Timing, When Asynchronous
32
543611-27
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CKA (CKB)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WA (R/WB)
ENA (ENB)
REQA (REQB)
tEF
tSKEW2 (4)
tEF
AE2 (AE1)
CKB (CKA)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WB (R/WA)
ENB (ENA)
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Almost-Empty Flags is controlled by rising clock
edges; whereas, internal deassertion of the Almost-Empty Flags
is controlled by falling clock edges, and their external deassertion
is controlled by rising clock edges.
4. tSKEW2 is the minimum time between a falling CKB (CKA) edge
and a rising CKA (CKB) edge for AE to change predictably during
the current clock cycle. If the time between the falling edge of
CKB (CKA) and the rising edge of CKA (CKB) is less than tSKEW2,
then it is not guaranteed that AE will change state until the next
following CKA (CKB) edge.
543611-45
Figure 21. Almost-Empty Flag Timing, When Synchronous
33
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKA (CKB )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WA (R/WB )
ENA (ENB )
REQA (REQB)
t FF
t FF
FF1 (FF2)
CKB (CKA )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WB (R/WA )
ENB (ENA )
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Full Flags is controlled by rising clock
edges; whereas, deassertion of the Full Flags is controlled
by falling clock edges.
Figure 22. Full Flag Timing, When Asynchronous
34
543611-28
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CKA (CKB)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WA (R/WB)
ENA (ENB)
REQA (REQB)
tFF
tSKEW1 (4)
tFF
FF1 (FF2)
CKB (CKA)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WB (R/WA)
ENB (ENA)
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Full Flags is controlled by rising clock edges;
whereas, internal deassertion of the Full Flags is controlled by
falling clock edges, and their external deassertion is controlled
by rising clock edges.
4. tSKEW1 is the minimum time between a falling CKB (CKA) edge
and a rising CKA (CKB) edge for FF to change predictably during
the current clock cycle. If the time between the falling edge of
CKB (CKA) and the rising edge of CKA (CKB) is less than tSKEW1,
then it is not guaranteed that FF will change state until the next
following CKA (CKB) edge.
543611-46
Figure 23. Full Flag Timing, When Synchronous
35
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKA (CKB )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WA (R/WB )
ENA (ENB )
REQA (REQB)
t AF
t AF
AF1 (AF2)
CKB (CKA )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WB (R/WA )
ENB (ENA )
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Almost-Full Flags is controlled by rising clock
edges; whereas, deassertion of the Almost-Full Flags is controlled
by falling clock edges.
Figure 24. Almost-Full Flag Timing, When Asynchronous
36
543611-29
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CKA (CKB)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WA (R/WB)
ENA (ENB)
REQA (REQB)
tAF
tSKEW1 (4)
tAF
AF1 (AF2)
CKB (CKA)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WB (R/WA)
ENB (ENA)
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Almost-Full Flags is controlled by rising clock
edges; whereas, internal deassertion of the Almost-Full Flags
is controlled by falling clock edges, and their external deassertion
is controlled by rising clock edges.
4. tSKEW1 is the minimum time between a falling CKB (CKA) edge
and a rising CKA (CKB) edge for AF to change predictably during
the current clock cycle. If the time between the falling edge of
CKB (CKA) and the rising edge of CKA (CKB) is less than tSKEW1,
then it is not guaranteed that AF will change state until the next
following CKA (CKB) edge.
543611-47
Figure 25. Almost-Full Flag Timing, When Synchronous
37
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKA (CKB )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WA (R/WB )
ENA (ENB )
REQA (REQB)
t HF
t HF
HF1 (HF2)
CKB (CKA )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WB (R/WA )
ENB (ENA )
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Both assertion and deassertion of the Half-Full Flags are controlled
entirely by rising clock edges, rather than by falling clock edges.
Figure 26. Half-Full Flag Timing, When Asynchronous
38
543611-30
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CKA (CKB)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WA (R/WB)
ENA (ENB)
REQA (REQB)
tSKEW2 (4)
tHF
tHF
HF2 (HF1)
CKB (CKA)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WB (R/WA)
ENB (ENA)
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Both assertion and deassertion of the Half-Full Flags are controlled
entirely by rising clock edges, rather than by falling clock edges.
4. tSKEW2 is the minimum time between a falling CKB (CKA) edge
and a rising CKA (CKB) edge for HF to change predictably during
the current clock cycle. If the time between the falling edge of
CKB (CKA) and the rising edge of CKA (CKB) is less than tSKEW2,
then it is not guaranteed that HF will change state until the next
following CKA (CKB) edge.
543611-48
Figure 27. Half-Full Flag Timing, When Synchronized
to a Port Clock Doing Reading
39
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKA (CKB)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WA (R/WB)
ENA (ENB)
REQA (REQB)
tSKEW1 (4)
tHF
tHF
HF1 (HF2)
CKB (CKA)
tRWS
tRWH
tES
tEH
tRQS
tRQH
R/WB (R/WA)
ENB (ENA)
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Both assertion and deassertion of the Half-Full Flags are
controlled entirely by rising clock edges, rather than by falling clock edges.
4. tSKEW1 is the minimum time between a falling CKB (CKA) edge
and a rising CKA (CKB) edge for HF to change predictably during
the current clock cycle. If the time between the falling edge of
CKB (CKA) and the rising edge of CKA (CKB) is less than tSKEW1,
then it is not guaranteed that HF will change state until the next
following CKA (CKB) edge.
Figure 28. Half-Full Flag Timing, When Synchronized
to a Port Clock Doing Writing
40
543611-49
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CK A
tRWS
R/WA
t ES
t EH
t EH
t ES
tRQS tRQH
tRQS
t ES
EN A
tRQS tRQH
REQA
t RSS
t RSH
t RS
RT2
t RSS
t RSH
CK B
tRWS
R/WB
t ES
t EH
t ES
t EH
t ES
EN B
tRQS tRQH
tRQS tRQH
tRQS
REQB
NOTES:
1. tRSS and tRSH need not be met unless a rising edge of CKA or CKB occurs while that clock is enabled.
2. tRSS is the time needed to deassert RT2 before returning to a normal FIFO cycle.
3. tRSH is the time needed before asserting RT2 after a normal FIFO cycle.
4. Read and write operations to FIFO #2 should be disabled while RT2 is being asserted.
543611-31
Figure 29. FIFO #2 Retransmit
41
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKB
tRWS
R/WB
t ES
t EH
t ES
t EH
t ES
EN B
tRQS tRQH
tRQS tRQH
tRQS
REQB
t RSH
tRSS
t RS
RT1
t RSH
t RSS
CKA
tRWS
R/WA
t ES
t EH
t EH
t ES
tRQS tRQH
tRQS
t ES
EN A
tRQS tRQH
REQA
NOTES:
1. tRSS and tRSH need not be met unless a rising edge of CKA or CKB occurs while that clock is enabled.
2. tRSS is the time needed to deassert RT1 before returning to a normal FIFO cycle.
3. tRSH is the time needed before asserting RT1 after a normal FIFO cycle.
4. Read and write operations to FIFO #1 should be disabled while RT1 is being asserted.
Figure 30. FIFO #1 Retransmit
42
543611-32
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CK A
t RWH
t RWH
tRWS
tRWS
R/WA
t EH
t EH
t ES
t ES
EN A
tRQH
tRQH
tRQS
tRQS
REQA
t DH
D0A - D35A
t DS
t DS
N1
N2
t DH
t EF
EF1
t EF
t FRL
CK B
t RWH
t RWH
tRWS
tRWS
R/W B
t EH
t EH
t ES
t ES
EN B
tRQH
tRQH
tRQS
tRQS
REQB
tA
tA
t OH
D0B - D35B
PREVIOUS DATA
t OH
N1
N2
NOTES:
1. A2A, A1A, A0A, and A0B are all held HIGH for FIFO access.
2. OEA is held HIGH.
3. OEB is held LOW.
4. tFRL (First Read Latency) - The first read following an empty condition
may begin no earlier than tFRL after the first write to an empty FIFO,
to ensure that valid read data is retrieved.
543611-33
Figure 31. FIFO #1 Write and Read Operation in
Near-Empty Region
43
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CK B
t RWH
t RWH
tRWS
tRWS
R/WB
t EH
t EH
t ES
t ES
EN B
tRQH
tRQH
tRQS
tRQS
REQB
t DH
t DH
t DS
D0B - D35B
t DS
N1
N2
t EF
EF2
t FRL
t EF
CK A
t RWH
t RWH
tRWS
t RWS
R/W A
t EH
t EH
t ES
t ES
EN A
tRQH
tRQH
tRQS
tRQS
REQA
D0A - D35A
PREVIOUS DATA
tA
tA
tOH
tOH
N1
N2
NOTES:
1. A2A, A1A, A0A, and A0B are all held HIGH for FIFO access.
2. OEB is held HIGH.
3. OEA is held LOW.
4. tFRL (First Read Latency) - The first read following an empty condition
may begin no earlier than tFRL after the first write to an empty FIFO,
to ensure that valid read data is retrieved.
543611-34
Figure 32. FIFO #2 Write and Read Operation in
Near-Empty Region
44
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CK A
t RWH
t RWH
tRWS
tRWS
R/WA
t EH
t EH
t ES
t ES
EN A
tRQH
tRQH
tRQS
tRQS
REQA
t DH
t DH
t DS
tDS
D0A - D35A
t FF
t FWL
FF1
t FF
CK B
t RWH
tRWS
t RWH tRWS
R/W B
t EH
tEH
t ES
t ES
EN B
tRQH
tRQH
tRQS
tRQS
REQB
tA
t OH
D0B - D35B
tA
t OH
PREVIOUS DATA
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. OEA is held HIGH.
3. OEB is held LOW.
4. tFWL (First Write Latency) - The first write following a full condition
may begin no earlier than tFWL after the first read from a full FIFO,
to ensure that valid write data is written.
543611-35
Figure 33. FIFO #1 Read and Write Operation in
Near-Full Region
45
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CK B
t RWH
t RWH
tRWS
tRWS
R/WB
t EH
t EH
t ES
t ES
EN B
tRQH
tRQH
tRQS
tRQS
REQB
t DH
t DH
t DS
tDS
D0B - D35B
t FF
t FWL
FF2
t FF
CK A
t RWH
tRWS
t RWH tRWS
R/W A
t EH
tEH
t ES
t ES
EN A
tRQH
tRQH
tRQS
tRQS
REQA
tA
t OH
D0A - D35A
tA
t OH
PREVIOUS DATA
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. OEB is held HIGH.
3. OEA is held LOW.
4. tFWL (First Write Latency) - The first write following a full condition
may begin no earlier than tFWL after the first read from a full FIFO,
to ensure that valid write data is written.
Figure 34. FIFO #2 Read and Write Operation in
Near-Full Region
46
543611-36
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CK B
tRWS
R/WB
t ES
EN B
t RQS
REQ B
tA
D0B - D17B
BITS
0-17
BITS
18-35
WORD # n+1
WORD # n
D18B - D35B
BITS
18-35
BITS
0-17
BITS
0-17
WORD # n
BITS
18-35
WORD # n+1
BITS
18-35
BITS
0-17
WORD # n+2
BITS
0-17
BITS
18-35
WORD # n+2
NOTES:
1. A0B is held HIGH for FIFO access.
2. OEB is held LOW.
3. WS0 is held HIGH and WS1 is held LOW for double-byte access.
4. Data-access time tA, after the rising edge of CKB, shown for the
first read cycle, applies similarly for all subsequent read cycles.
543611-37
Figure 35. Port B Double-Byte FIFO #1 Read Access for
36-to-18 Funneling
47
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CK B
tRWS
R/WB
t ES
EN B
t RQS
REQ B
t DS
D0B - D17B
t DH
BITS
0-17
WORD # n
BITS
18-35
BITS
0-17
WORD # n+1
BITS
18-35
BITS
0-17
WORD # n+2
NOTES:
1. A0B is held HIGH for FIFO access.
2. OEB is held HIGH.
3. WS0 is held HIGH and WS1 is held LOW for double-byte access.
4. Data-setup time tDS and data-hold time tDH, before and after
the rising edge of CKB, shown for the first write cycle, apply
similarly for all subsequent write cycles.
Figure 36. Port B Double-Byte FIFO #2 Write Access for
18-to-36 Defunneling
48
BITS
18-35
543611-38
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CK B
tRWS
R/WB
t ES
EN B
t RQS
REQ B
tA
D0B - D8B
BITS
0-8
BITS
9-17
BITS
18-26
WORD # n
D9B - D17B
BITS
9-17
BITS
18-26
BITS
18-26
BITS
27-35
BITS
27-35
BITS
0-8
BITS
9-17
WORD # n+1
BITS
27-35
BITS
0-8
WORD # n
D27B - D35B
BITS
0-8
WORD # n+1
WORD # n
D18B - D26B
BITS
27-35
BITS
9-17
BITS
18-26
WORD # n+1
BITS
0-8
WORD # n
BITS
9-17
BITS
18-26
BITS
27-35
WORD # n+1
NOTES:
1. A0B is held HIGH for FIFO access.
2. OEB is held LOW.
3. WS0 and WS1 both are held LOW for single-byte access.
4. Data-access time tA, after the rising edge of CKB, shown for the
first read cycle, applies similarly for all subsequent read cycles.
543611-39
Figure 37. Port B Single-Byte FIFO #1 Read Access for
36-to-9 Funneling
49
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CK B
tRWS
R/WB
t ES
EN B
t RQS
REQ B
t DS
D0B - D8B
t DH
BITS
0-8
BITS
9-17
WORD # n
BITS
18-26
BITS
27-35
BITS
0-8
WORD # n+1
NOTES:
1. A0B is held HIGH for FIFO access.
2. OEB is held HIGH.
3. WS0 and WS1 both are held LOW for single-byte access.
4. Data-setup time tDS and data-hold time tDH, before and after
the rising edge of CKB, shown for the first write cycle, apply
similarly for all subsequent write cycles.
Figure 38. Port B Single-Byte FIFO #2 Write Access for
50
BITS
9-17
543611-40
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
Outside the 'almost-full' region,
acknowledge is continuous
for a continuous request.
*
*
*
Starting at the third cycle after entering the
'almost-full' region, acknowledge
occurs on every third cycle to prevent overrun
of the full condition.
*
*
CKA (CKB )
tRWS
R/WA (R/WB )
t RQS
REQ A (REQB )
t ACK
ACK A (ACKB )
t ACK
t ACK
t ACK
1
t AF
2
AF1 (AF2)
NOTES:
1. For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
2. ACK can be tied directly to EN to directly gate FIFO accesses.
Indicates where a write would take place, if ACK were tied to EN.
3. REQ must be maintained HIGH with R/W stable throughout entire clock cycle for ACK to be generated.
4. When the REQ/ACK handshake is not used, ACK can be ignored,
and REQ may be tied HIGH or used as a second enable.
5. Parameters without parentheses apply to Port A. Parameters with parentheses apply to Port B.
*
543611-41
Figure 39. Write Request/Acknowledge Handshake
51
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
Outside the 'almost-empty' region,
acknowledge is continuous
for a continuous request.
*
*
*
Starting at the third cycle after entering the
'almost-empty' region, acknowledge
occurs on every third cycle to prevent underrun
of the empty condition.
*
*
CKA (CKB )
tRWS
R/WA (R/WB )
t RQS
REQ A (REQB )
t ACK
ACK A (ACKB )
t ACK
t ACK
t ACK
1
t AE
2
AE2 (AE1)
NOTES:
1. For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
2. ACK can be tied directly to EN to directly gate FIFO accesses.
Indicates where a read would take place, if ACK were tied to EN.
3. REQ must be maintained HIGH with R/W stable throughout entire clock cycle for ACK to be generated.
4. When the REQ/ACK handshake is not used, ACK can be ignored,
and REQ may be tied HIGH or used as a second enable.
5. Parameters without parentheses apply to Port A. Parameters with parentheses apply to Port B.
*
Figure 40. Read Request/Acknowledge Handshake
52
543611-42
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CKB
tRWS
R/WB
tES
ENB
tRQS
REQB
tWSS tWSH
tWSS tWSH
WS1
WS0
tPF
PFB
(SYNCHRONOUS
LATCHING)
tDS
tDH
D0B - D35B
(WHEN DATA
WORDS ARE
INCOMING)
tPF
PFB
(ASYNCHRONOUS,
WHEN DATA WORDS
ARE INCOMING)
tA
D0B - D35B
(WHEN DATA
WORDS ARE
OUTGOING)
tPF
PFB
(ASYNCHRONOUS,
WHEN DATA WORDS
ARE OUTGOING)
NOTE: During retransmit, WS1 and WS0 must be stable throughout entire clock cycle.
543611-50
Figure 41. Changing Port B
Word-Width Selection During Operation
53
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
CKB
tRWS
R/WB
tES
ENB
tRQS
REQB
tWSS tWSH
tWSS tWSH
WS1
WS0
tPF
PFB
(SYNCHRONOUS
LATCHING)
tDS
tDH
D0B - D35B
(WHEN DATA WORDS
ARE INCOMING)
tPF
PFB
(ASYNCHRONOUS,
WHEN DATA WORDS
ARE INCOMING)
tA
D0B - D35B
(WHEN DATA
WORDS ARE
OUTGOING)
tPF
PFB
(ASYNCHRONOUS,
WHEN DATA WORDS
ARE OUTGOING)
NOTE: During parity mode changes (odd or even), TPF may have additional delay from the rising edge of the clock.
Figure 42. Parity Generation
54
543611-51
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
PACKAGE DIAGRAMS
132PQFP (PQFP132-P-S950)
SECTION
0° - 8°
0.15 [0.006]
0.51 [0.020] MIN.
45°
CHAMFER
0.25 [0.010] TYP.
0.10 [0.004]
0.635
[0.025] TYP
NON-ACCUM
28.02 [1.103]
27.86 [1.097]
27.69 [1.090]
27.18 [1.070]
TOP VIEW
24.21 [0.953]
24.05 [0.947]
24.21 [0.953]
24.05 [0.947]
27.69 [1.090]
27.18 [1.070]
28.02 [1.103]
27.86 [1.097]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
0.51 [0.020]
MIN.
4.57 [0.180]
4.06 [0.160]
132PQFP
132-pin PQFP
55
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
144TQFP (TQFP-144-P-2020)
0.50 [0.020]
TYP.
0.20 [0.008]
0.09 [0.004]
0.27 [0.010]
0.17 [0.007]
20.0
[0.787]
BASIC
22.0
[0.866]
BASIC
20.0 [0.787]
BASIC
DETAIL
22.0 [0.866]
BASIC
1.60 [0.063]
REF. MAX
1.45 [0.057]
1.35 [0.053]
0.15 [0.006]
0.05 [0.002]
0.75 [0.030]
0.47 [0.019]
1.00
[0.039]
REF.
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
144TQFP
144-pin TQFP
56
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
ORDERING INFORMATION
LH543611/21
Device Type
X
Package
- ##
Speed
15
20
25 Cycle Times (ns)
30
35
M 144-pin, Thin Quad Flat Package (TQFP144-P-2020)
P 132-pin, Plastic Quad Flat Package (PQFP132-P-S950)
512 x 36 x 2/1K x 36 x 2 Bidirectional FIFO
Example: LH543611M-15 (512 x 36 x 2 Bidirectional FIFO, 15 ns, 144-pin, Thin Quad Flat Package)
543611-43
NOTE:
For PQFP-to-PGA conversion for through-hole board designs, SHARP recommends QFP-to-PGA adaptors from ISI (Interconnect Systems Inc.)
ISI makes three models that can map the LH543611/21 132-pin PQFP to a 13x13 PGA (100 mil); mode #A 13225-1® map to a SHARP specific 120-pin PGA. For more information, contact SHARP or ISI directly at P.O. Box 1089, Simi Valley, CA 93062, Tel: (805) 581-5626.
57