SHARP LR38581

LR38581
DESCRIPTION
PIN CONNECTIONS
The LR38581 is a CMOS timing generator IC which
generates timing pulses for driving 270 k/320 kpixel color CCD area sensors with a dual-powersupply operation and processing pulses for color
video signals.
TOP VIEW
GND
FH2B
FH2
FH1
VDD5
GND
FH1B
FR
TVMD
PLCH
TST4
48-PIN QFP
TST3
LR38581
Timing Generator IC for 270 k/320 k-pixel
Color CCDs with Dual-power-supply Operation
48 47 46 45 44 43 42 41 40 39 38 37
36 SAD2
35 SAD1
34 HP
33 VD
32 ADCK
31 GND
30 VDD3
29 CDCK
28 SGCK
27 GND
26 CKO
25 CKI
OBCP 1
CLP 2
PBLK 3
FS 4
FCDS 5
RS 6
GND 7
VDD3 8
ED0 9
ED1 10
ED2 11
MIR 12
FEATURES
• Designed for 270 k/320 k-pixel color CCD area
sensors with a dual-power-supply-operation
• Switchable between NTSC and PAL modes
• Switchable between normal and mirror images
• Level shifter for readout and shutter pulses included
• +3.3 V, +5 V and +12.5 V power supplies
• Package :
48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch
TST1
TST2
VDD5
V1
V2
V3
V4
NC
GND
VTG
VDD12
OFD
13 14 15 16 17 18 19 20 21 22 23 24
(QFP048-P-0707)
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
LR38581
SAD2
SAD1
HP
VD
ADCK
GND
VDD3
CDCK
SGCK
GND
CKO
CKI
BLOCK DIAGRAM
36
35
34
33
32
31
30
29
28
27
26
25
TST3 37
24 OFD
OSC
TST4 38
23 VDD12
PLCH 39
22 VTG
RESET
TVMD 40
1/4
PRESET
FR 41
FH1B 42
DECODER
& LATCH
V COUNTER
21 GND
20 NC
LEVEL
SHIFTER
(12.5 V)
H COUNTER
GND 43
1/2
19 V4
LEVEL
SHIFTER
18 V3
VDD5 44
17 V2
SHUTTER CONTROL
FH1 45
16 V1
FH2 46
15 VDD5
LEVEL
SHIFTER
MIX
1/3
2
FCDS
RS
7
8
9
10
11
12
MIR
6
ED2
5
ED1
4
ED0
3
VDD3
2
GND
1
FS
13 TST1
PBLK
GND 48
CLP
14 TST2
OBCP
FH2B 47
LR38581
PIN DESCRIPTION
PIN NO. SYMBOL
I/O
POLARITY
PIN NAME
DESCRIPTION
A pulse to clamp the optical black signal. This pulse stays
1
OBCP
O4MA3
Optical black clamp
pulse output
2
CLP
O4MA3
AD input signal
clamp pulse output
A pulse to clamp the AD input signal. The polarity can
be changed by PLCH (pin 39).
3
PBLK
O4MA3
Pre-blanking pulse
output
A pulse that corresponds to the cease period of the
horizontal transfer pulse.
4
FS
O4MA32
CDS pulse output 1
5
FCDS
O4MA32
CDS pulse output 2
low during the absence of effective pixels within the vertical
blanking. The polarity can be changed by PLCH (pin 39).
A pulse to sample-hold the signal from CCD.
The polarity can be changed by PLCH (pin 39).
The output phase of FS is selected by serial data.
A pulse to clamp the feed-through level from CCD.
The polarity can be changed by PLCH (pin 39).
The output phase of FCDS is selected by serial data.
S/H pulse output
A pulse to sample-hold the signal from CDS circuit.
The polarity can be changed by PLCH (pin 39).
–
Ground
The output phase of RS is selected by serial data.
A grounding pin.
–
–
Power supply
Supply of +3.3 V power.
ICSU3
–
Shift register clock
An input pin for the clock of the shift register, to control
the functions of LR38581. For details, see "Serial Data
6
RS
7
GND
–
8
VDD3
9
ED0
10
11
ED1
ED2
O4MA32
ICSU3
ICSU3
–
–
input
Shift register data
input
Strobe pulse input
Control."
An input pin for the data of the shift register, to control
the functions of LR38581. For details, see "Serial Data
Control."
An input pin for the strobe pulse, to control the functions
of LR38581. For details, see "Serial Data Control."
An input pin to select mirror or normal image mode
12
MIR
ICU3
–
L level
H level or open
Mirror mode
MIR
selection
FH1B
FH2B
: Normal image mode
: Mirror image mode
L (Normal mode) H or open (Mirror mode)
∏ FH1
∏ FH2
∏ FH2
∏ FH1
13
14
TST1
TST2
ICD5
ICD5
–
–
Test pin 1
Test pin 2
A test pin. Set open or to L level in the normal mode.
A test pin. Set open or to L level in the normal mode.
15
VDD5
–
–
16
V1
Power supply
Vertical transfer
Supply of +5 V power.
A pulse to drive vertical CCD shift register.
O4MA52
pulse output 1
Connect to ØV1 pin of CCD.
A pulse to drive vertical CCD shift register.
Connect to ØV2 pin of CCD.
A pulse to drive vertical CCD shift register.
Connect to ØV3 pin of CCD.
17
V2
O4MA52
Vertical transfer
pulse output 2
18
V3
O4MA52
Vertical transfer
pulse output 3
3
LR38581
PIN NO. SYMBOL
I/O
19
V4
O4MA52
20
21
NC
GND
–
–
22
VTG
O12MHV
23
VDD12
–
24
OFD
O12MHV
POLARITY
–
–
PIN NAME
Vertical transfer
DESCRIPTION
A pulse to drive vertical CCD shift register.
pulse output 4
Connect to ØV4 pin of CCD.
No connection
Ground
No connection
A grounding pin.
Readout pulse
output
–
Power supply
A pulse that transfers the charge of the photo-diode to
the vertical shift register.
Connect to VTG pin of CCD.
Supply of +12.5 V power.
A pulse that sweeps the charge of the photo-diode
OFD pulse output
for electronic shutter. Connect to OFD pin of CCD.
Held at L level at normal mode.
An input pin for reference clock oscillation.
Connect to CKO (pin 26) with R.
The frequencies are as follows :
25
CKI
OSCI3
–
Clock input
TVMD
L
Frequency
28.63636 MHz (1820 fH)
H
28.37500 MHz (1816 fH)
fH = Horizontal frequency
26
CKO
OSCO3
–
Clock output
27
GND
–
–
Ground
An output pin for reference clock oscillation.
The output is the inverse of CKI (pin 25).
A grounding pin.
An output pin to generate HP and VD pulses.
The frequencies are as follows :
28
SGCK
O4MA32
SSG clock output
TVMD
Frequency
L
H
14.31818 MHz (910 fH)
14.18750 MHz (908 fH)
An output pin for DSP IC.
The frequencies are as follows :
29
CDCK
O4MA32
DSP clock output
TVMD
L
Frequency
9.5035 MHz (1820/3 fH)
H
9.4375 MHz (1816/3 fH)
30
VDD3
–
–
Power supply
Supply of +3.3 V power.
31
GND
–
–
Ground
A grounding pin.
An output pin for AD converter.
The frequencies are as follows :
32
ADCK
O4MA32
AD clock output
Frequency
TVMD
L
9.5035 MHz (1820/3 fH)
H
9.4375 MHz (1816/3 fH)
The output phase of ADCK is selected by SAD1 (pin 35)
and SAD2 (pin 36).
4
LR38581
PIN NO. SYMBOL
33
VD
I/O
POLARITY
IC3
DESCRIPTION
An input pin for reference of vertical pulse.
pulse input
Connect to VD pin of DSP IC.
Horizontal reference An input pin for reference of horizontal pulse.
pulse input
Connect to HD pin of DSP IC.
34
HP
IC3
35
SAD1
ICU3
–
36
SAD2
ICU3
–
37
38
TST3
TST4
ICD5
ICD5
–
–
39
PLCH
ICU5
–
ICU5
PIN NAME
Vertical reference
–
ADCK phase control An input pin to select the phase of ADCK.
L
H or open
L
H or open
SAD1
input 1
SAD2
Phase
ADCK phase control
input 2
L
0˚
L
H or open H or open
60˚ delay 180˚ delay 240˚ delay
Test pin 3
Test pin 4
A test pin. Set open or to L level in the normal mode.
A test pin. Set open or to L level in the normal mode.
Polarity selection
An input pin to select the polarity of OBCP (pin 1),
input
TV mode selection
CLP (pin 2), FS (pin 4), FCDS (pin 5) and RS (pin 6).
An input pin to select TV standards.
40
TVMD
L level
H level or open
41
FR
O4MA53
Reset pulse output
Connect to ØR pin of CCD through the DC offset circuit.
The output phase of FR is selected by serial data.
42
FH1B
O4MA52
Horizontal transfer
pulse output 1B
A pulse to drive horizontal CCD shift register.
Connect to ØH1B pin of CCD.
43
GND
–
–
Ground
A grounding pin.
44
VDD5
–
–
45
FH1
O4MA53
Power supply
Horizontal transfer
Supply of +5 V power.
A pulse to drive horizontal CCD shift register.
46
FH2
O4MA53
pulse output 1
Horizontal transfer
Connect to ØH1 pin of CCD.
A pulse to drive horizontal CCD shift register.
Connect to ØH2 pin of CCD.
47
FH2B
O4MA52
pulse output 2
Horizontal transfer
A pulse to drive horizontal CCD shift register.
pulse output 2B
Connect to ØH2B pin of CCD.
48
GND
–
Ground
A grounding pin.
input
: NTSC mode
: PAL mode
A pulse to reset the charge of output circuit.
IC3
ICU3
ICSU3
ICU5
ICD5
O4MA3
–
O4MA32
O4MA52
O4MA53
O12MHV
OSCI3
OSCO3
: Input pin (CMOS level)
: Input pin (CMOS level with pull-up resistor)
: Input pin (CMOS schmitt-trigger level with pull-up
resistor)
: Input pin (CMOS level with pull-up resistor)
: Input pin (CMOS level with pull-up resistor)
: Output pin (VDD = 3.3 V)
5
:
:
:
:
:
:
Output pin (VDD = 3.3 V)
Output pin (VDD = 5 V)
Output pin (VDD = 5 V)
Output pin (VDD = 12.5 V)
Input pin for oscillation
Output pin for oscillation
LR38581
Serial Data Control
SERIAL DATA INPUT TIMING
ED0
ED1
D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18
ED2
The serial data ED1 is shifted by ED0 and is
latched at the rising edge of ED2.
The shutter mode data SMD1 and SMD2 of serial
data are latched at the rising edge of the horizontal
line in which VTG is active, the shutter speed data
SD0 to SD8 are latched at the rising edge of the
next horizontal line in which VTG is active.
SERIAL DATA INPUTS
DATA
D00
D01
NAME
SD0
SD1
FUNCTIONS
D02
SD2
D11
MR1
D03
D04
SD3
SD4
D12
D13
MR2
MC1
D05
D06
SD5
SD6
D14
D15
MC2
MS1
D07
SD7
D16
MS2
D08
SD8
D17
D18
MF1
MF2
Electronic shutter speed control
DATA
D09
D10
NAME
SMD1
SMD2
Supply voltage
Input voltage
SYMBOL
VDD3, VDD5
VDD12
RATING
–0.3 to +6.0
–0.3 to +15.0
VI3
VI5
–0.3 to VDD3 + 0.3
V
–0.3 to VDD5 + 0.3
V
UNIT
V
V
VO3
–0.3 to VDD3 + 0.3
V
Output voltage
VO5
VO12
–0.3 to VDD5 + 0.3
–0.3 to VDD12 + 0.3
V
V
Operating temperature
Storage temperature
TOPR
TSTG
–20 to +70
–55 to +150
˚C
˚C
6
Electronic shutter mode control
Phase control
ABSOLUTE MAXIMUM RATINGS
PARAMETER
FUNCTIONS
LR38581
ELECTRICAL CHARACTERISTICS
DC Characteristics
PARAMETER
Input "Low" voltage
Input "High" voltage
(VDD3 = 3.3±0.33 V, VDD5 = 5.0±0.5 V, VDD12 = 12.5±0.5 V, TOPR = –20 to +70 ˚C)
SYMBOL
VIL3
CONDITIONS
TYP.
MIN.
VIH3
MAX. UNIT
0.3VDD3
V
0.7VDD3
1.5
V
V
0.75VDD3
V
V
NOTE
1, 2
Input "Low" voltage
VIL5
Input "High" voltage
Input "Low" voltage
VIH5
VT+
3.5
Input "High" voltage
VT–
0.02VDD3
V
Hysteresis voltage
Input "Low" current
VT+ – VT–
|IIL3-1|
0.045VDD3
VI = 0 V
1.0
V
µA
Input "High" current
Input "Low" current
|IIH3-1|
|IIL3-2|
VI = VDD3
VI = 0 V
1.0
30
µA
µA
Input "High" current
|IIH3-2|
VI = VDD3
2.0
µA
Input "Low" current
Input "High" current
|IIL5-1|
|IIH5-1|
VI = 0 V
VI = VDD5
60
2.0
µA
µA
4
Input "Low" current
Input "High" current
|IIL5-2|
|IIH5-2|
VI = 0 V
VI = VDD5
2.0
60
µA
µA
5
0.4
V
0.4
V
V
0.4
V
V
3.0
8.0
8.0
Output "Low" voltage
VOL3-1
IOL = 1.5 mA
Output "High" voltage
Output "Low" voltage
VOH3-1
VOL3-2
IOH = –1.5 mA
IOL = 2 mA
VDD3 – 0.5
Output "High" voltage
Output "Low" voltage
VOH3-2
VOL3-3
IOH = –1.5 mA
IOL = 4 mA
VDD3 – 0.5
Output "High" voltage
VOH3-3
IOH = –3 mA
VDD3 – 0.5
Output "Low" voltage
Output "High" voltage
VOL5-1
VOH5-1
IOL = 9 mA
IOH = –6 mA
VDD5 – 0.5
Output "Low" voltage
Output "High" voltage
VOL5-2
VOH5-2
IOL = 12 mA
IOH = –9 mA
VDD5 – 0.5
Output "Low" voltage
Output "High" voltage
VOL12
VOH12
IOL = 12 mA
IOH = –12 mA
VDD12 – 0.5
NOTES :
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Applied to inputs (IC3, OSCI3).
Applied to input (ICU3).
Applied to input (ICSU3).
Applied to input (ICU5).
Applied to input (ICD5).
Applied to output (OSCO3). (Output (OSCO3) measures
on condition that input (OSCI3) level is 0 V or VDD3.)
7
Applied
Applied
Applied
Applied
Applied
to
to
to
to
to
output
output
output
output
output
(O4MA3).
(O4MA32).
(O4MA52).
(O4MA53).
(O12MHV).
V
4, 5
3
1
2, 3
6
7
8
0.4
V
V
9
0.4
V
V
10
0.4
V
V
11
PACKAGES FOR CCD AND CMOS DEVICES
PACKAGE
(Unit : mm)
48 QFP (QFP048-P-0707)
0.15±0.05
0.2±0.08
M
(1.0)
25
36
37
48
13
7.0±0.2
12
(1.0)
0.1±0.1
8
0.1
8.0±0.2
0.65±0.2
1.45±0.2
9.0±0.3
Package
base plane
1
(1.0)
(1.0)
7.0±0.2
0.08
24
9.0±0.3
0.5TYP.