LR38574 Timing Generator IC for 1 090 k/1 310 k-pixel CCDs LR38574 DESCRIPTION PIN CONNECTIONS The LR38574 is a CMOS timing generator IC which generates timing pulses for driving 1 090 k/ 1 310 k-pixel CCD area sensors and processing pulses. TOP VIEW SHTR DRMD FR TST3 VDD4 FH2 GND FH1 VDD4 CCD TST2 TST1 48-PIN QFP 48 47 46 45 44 43 42 41 40 39 38 37 FEATURES OFDC 1 V1x 2 VH1Ax 3 VH1Bx 4 V2x 5 VDD3 6 GND 7 V3x 8 VH3Ax 9 VH3Bx 10 V4x 11 OFDX 12 • Designed for 1/3-type 1 090 k/1 310 k-pixel CCD area sensors • Frequency of driving horizontal CCD : 12.27 MHz • Both double speed drive monitoring mode and still mode are possible • Two still mode types : 3 fields period and 4 fields period • External shutter control function with serial data input is possible • +3 V and +4.5 V power supplies • Package : 48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch 36 ID 35 ED2 34 ED1 33 ED0 32 HD 31 GND 30 VDD3 29 VD 28 DCLK 27 CLK 26 CKO 25 CKI PBLK BCPX CLPX ADCK GND FCDS FS VDD3 ACLX RS GND VCON 13 14 15 16 17 18 19 20 21 22 23 24 (QFP048-P-0707) In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LR38574 ID ED2 ED1 ED0 HD GND VDD3 VD DCLK CLK CKO CKI BLOCK DIAGRAM 36 35 34 33 32 31 30 29 28 27 26 25 OSC TST1 37 GATE TST2 38 DATA LATCH & SHUTTER CONTROL 24 VCON 23 GND CCD 39 22 RS VDD4 40 21 ACLX 1/2 1/8 RESET FH1 41 20 VDD3 GND 42 1/2 H COUNTER FH2 43 19 FS 18 FCDS GATE RESET VDD4 44 17 GND RESET TST3 45 DECODER 16 ADCK V COUNTER FR 46 15 CLPX DRMD 47 14 BCPX LEVEL SHIFTER 2 V1X VH1AX VH1BX V2X VDD3 7 8 9 10 11 12 OFDX 6 V4X 5 VH3BX 4 VH3AX 3 V3X 2 13 PBLK GND 1 OFDC SHTR 48 LR38574 PIN DESCRIPTION PIN NO. SYMBOL I/O POLARITY PIN NAME Control pulse output DESCRIPTION 1 OFDC O3 2 V1X O3 3 VH1AX O3 4 VH1BX O3 Readout pulse output 1B 5 V2X O3 Vertical transfer pulse output 2 A vertical transfer pulse for CCD. Connect to V2X pin of vertical driver IC. 6 VDD3 – – Power supply Supply of +3.3 V power. 7 GND – – 8 V3X O3 Ground Vertical transfer A grounding pin. A vertical transfer pulse for CCD. pulse output 3 Connect to V3X pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to 9 VH3AX O3 10 VH3BX O3 11 V4X O3 12 OFDX O3 13 PBLK for OFD voltage 14 BCPX O3 15 CLPX O3 16 ADCK O6MA3 17 GND – Vertical transfer A vertical transfer pulse for CCD. pulse output 1 Connect to V1X pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to Readout pulse output 1A Readout pulse output 3A Readout pulse A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH1BX pin of vertical driver IC. the vertical shift register. Connect to VH3AX pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH3BX pin of vertical driver IC. Vertical transfer A vertical transfer pulse for CCD. pulse output 4 Connect to V4X pin of vertical driver IC. A pulse that sweeps the charge of the photo-diode for the electronic shutter. Connect to OFD pin of CCD through the vertical driver IC and DC offset circuit. Pre-blanking pulse Held at H level at normal mode. A pulse that corresponds to the cease period of the output horizontal transfer pulse. Optical black clamp A pulse to clamp the optical black signal. This pulse stays high during the absence of effective pulse output Clamp pulse output AD clock output – the vertical shift register. Connect to VH1AX pin of vertical driver IC. output 3B OFD pulse output O3 A pulse to control OFD voltage. Ground pixels within the vertical blanking or the period of sweep-out signal. A pulse to clamp the dummy outputs of CCD signal. This pulse stays high during the sweep-out period. An output pin for AD converter. The output phase of ADCK is selected by serial data step by 90˚. A grounding pin. 3 LR38574 PIN NO. SYMBOL 18 FCDS I/O POLARITY O6MA3 PIN NAME CDS pulse output 1 O6MA3 CDS pulse output 2 DESCRIPTION A pulse to clamp the feed-through level from CCD. The output phase of FCDS is selected by serial data. A pulse to sample-hold the signal from CCD. The output phase of FS is selected by serial data. 19 FS 20 VDD3 – – Power supply Supply of +3.3 V power. An input pin for resetting all internal circuits at power on. 21 ACLX ICU3 – All clear input Connect to VDD through the diode and GND through the capacitor. 22 RS 23 GND O6MA3 – S/H pulse output – Ground A pulse to sample-hold the signal. The output phase of RS is selected by serial data. A grounding pin. An input pin to control internal vertical clock for long shutter speed. 24 VCON ICU3 – VD control input H level or open : VD L level : VD is masked by the pulse which is latched at the rising edge of VD. It's necessary to be set SMD = high and number of the fields data n ≥ 2 in serial data control at VCON operation. An input pin for reference clock oscillation. 25 CKI OSCI3 – Clock input 26 CKO OSCO3 – Clock output 27 CLK O6MA3 Clock output 28 DCLK O6MA3 Clock output An output pin for DSP IC. The frequency is 12.72727 MHz. The output phase of DCLK is selected by serial data Vertical reference step by 90˚. An input pin for reference of vertical pulse. Connect to VD pin of DSP IC. Supply of +3.3 V power. IC3 The frequency is 24.54545 MHz. An output pin for reference clock oscillation. The output is the inverse of CKI (pin 25). An output pin to generate HD and VD pulses. The frequency is 12.72737 MHz. 29 VD 30 VDD3 – – pulse input Power supply 31 GND – – Ground A grounding pin. Horizontal drive pulse input An input pin for reference of horizontal pulse. Connect to HD pin of DSP IC. An input pin for the strobe pulse, to control the functions of LR38574. For details, see "Serial Data Control". 32 HD IC3 33 ED0 ICSU3 – Strobe pulse input 34 ED1 ICSU3 – Shift register clock input An input pin for the clock of the shift register, to control the functions of LR38574. For details, see "Serial Data Control". 4 LR38574 PIN NO. SYMBOL 35 ED2 I/O POLARITY ICSU3 – 36 ID 37 TST1 ICD4 38 TST2 ICD4 PIN NAME Shift register data input DESCRIPTION An input pin for the data of the shift register, to control the functions of LR38574. For details, see "Serial Data Line index pulse Control". The pulse is used in color separator. – output Test pin 1 The signal switches between high and low at every line. A test pin. Set open or to L level in the normal mode. – Test pin 2 A test pin. Set open or to L level in the normal mode. An input pin to select CCD. It should be used with O3 MODE input which is in the serial data. 39 40 CCD ICU4 VDD4 – 41 FH1 O6MA43 42 GND – 43 FH2 O6MA43 44 45 VDD4 TST3 – ICD4 46 FR – – – – – O6MA43 47 DRMD ICU3 48 SHTR O3 IC3 ICU3 ICSU3 ICU4 ICD4 : : : : : Input Input Input Input Input pin pin pin pin pin (CMOS (CMOS (CMOS (CMOS (CMOS – CCD selection input MODE L CCD LZ23H3V1 L H H L – LZ23J3V H H – – Power supply Supply of +4.5 V power. Horizontal transfer pulse output 1 A horizontal transfer pulse for CCD. Connect to ØH1 pin of CCD. Ground Horizontal transfer A grounding pin. A horizontal transfer pulse for CCD. pulse output 2 Connect to ØH2 pin of CCD. Power supply Test pin 3 Supply of +4.5 V power. A test pin. Set open or to L level in the normal mode. Reset pulse output A pulse to reset the charge of output circuit. The output phase of FR is selected by serial data. Drive mode selection input Trigger output level) level with level with level with level with CCD L An input pin to select the period of still mode. L level : 3 fields period H level or open : 4 fields period A trigger pulse for effective signal period. O3 O6MA3 O6MA43 OSCI3 OSCO3 pull-up resistor) schmitt-trigger) pull-up resistor) pull-down resistor) 5 : : : : : Output pin (output high level is VDD3.) Output pin (output high level is VDD3.) Output pin (output high level is VDD4.) Input pin for oscillation Output pin for oscillation LR38574 Serial Data Control SERIAL DATA INPUT TIMING ED0 ED1 ED2 D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 ... D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 The data is shifted at the rising edge of ED1, and is latched at the rising edge of ED0. PWSA is effective at the rising edge of ED0, but others are effective at the horizontal line in which VH1AX to VH3BX are active. ED0 should be low level during data inputs of ED1 and ED2. As all internal data are set to low level by ACLX or PWSA, ED0 to ED1 should be input for desirable operations. As all internal data except PWSA are set to low level by PWSA, ED0 to ED1 should be input for desirable operations. 6 LR38574 SERIAL DATA INPUTS DATA D00-D06 NAME SD0-SD6 FUNCTION Step of high speed shutter D07 D08 SD7 SD8 Number of exposed fields DATA = L – D09 SD9 SMD INMD Electronic shutter mode control Integration mode control D12 PWSA D13 PLCH Power save control Polarity control of FCDS, FS and D14 MODE – RS pulses with CCD (pin 39) D15 BCPCNT BCP control D16 D17 ML1 ML2 D18 MR1 D19 D20 MR2 MR3 D21 MC1 D22 MC2 D23 MC3 D24 D25 MS1 MS2 D26 D27 MS3 MF1 D28 MF2 D29 D30 MF3 MA1 D31 MA2 All L – D10 D11 Monitoring mode selection DATA = H AT ACLX = L All L Monitoring Still L L Normal Power save – Negative Positive L 2 lines/4 lines 2 lines/8 lines CCD = L CCD = H CCD = L CCD = H L LZ23H3V1 LZ23J3V – – Uncontinuously Continuously L L – L L – L L L L – L Phase control L L – L L L – L L – L ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage SYMBOL VDD3, VDD4 RATING –0.3 to +6.0 UNIT V Input voltage VI3 VI4 –0.3 to VDD3 + 0.3 V V Output voltage VO3 VO4 –0.3 to VDD3 + 0.3 Operating temperature Storage temperature –0.3 to VDD4 + 0.3 –0.3 to VDD4 + 0.3 V V TOPR –20 to +70 ˚C TSTG –55 to +150 ˚C 7 LR38574 ELECTRICAL CHARACTERISTICS DC Characteristics PARAMETER Input "Low" voltage Input "High" voltage (VDD3 = 3.0 V to VDD4, VDD4 = 4.2 to 5.5 V, TOPR = –20 to +70 ˚C) SYMBOL VIL3-1 CONDITIONS VIH3-1 Input "Low" voltage VIL3-2 Input "High" voltage Hysteresis voltage VIH3-2 VT+ – VT– MIN. TYP. MAX. UNIT 0.2VDD3 V 0.8VDD3 V V 0.2VDD3 Schmitt-buffer 0.75VDD3 V V 0.2VDD4 V 0.08VDD3 NOTE 1, 2 3 Input "Low" voltage VIL4 Input "High" voltage Input "Low" current VIH4 |IIL3-1| VI = 0 V 1.0 V µA Input "High" current Input "Low" current |IIH3-1| |IIL3-2| VI = VDD3 VI = 0 V 2.0 1.0 60 µA µA Input "High" current Input "Low" current |IIH3-2| |IIL4-1| VI = VDD3 VI = 0 V 4.0 2.0 60 µA µA Input "High" current |IIH4-1| VI = VDD4 2.0 µA Input "Low" current Input "High" current |IIL4-2| |IIH4-2| VI = 0 V VI = VDD4 4.0 2.0 60 µA µA 5 VOL3-1 VOH3-1 IOL = 2 mA IOH = –1 mA 0.4 VDD3 – 0.5 V V 6 0.4 V 0.4 V V 0.4 V V Output "Low" voltage Output "High" voltage 0.8VDD4 Output "Low" voltage VOL3-2 IOL = 3 mA Output "High" voltage Output "Low" voltage VOH3-2 VOL3-3 IOH = –3 mA IOL = 3 mA VDD3 – 0.5 Output "High" voltage VOH3-3 VDD3 – 0.5 VDD4 – 0.5 Output "Low" voltage VOL4 IOH = –3 mA IOL = 10 mA Output "High" voltage VOH4 IOH = –10 mA V 4, 5 1 2, 3 4 7 8 9 NOTES : 1. 2. 3. 4. 5. Applied Applied Applied Applied Applied to to to to to 6. Applied to output (O3). 7. Applied to output (OSCO3). (Output (OSCO3) measures on condition that input (OSCI3) level is 0 V or VDD3.) 8. Applied to output (O6MA3). 9. Applied to output (O6MA43). inputs (IC3, OSCI3). input (ICU3). input (ICSU3). input (ICU4). input (ICD4). 8 PACKAGES FOR CCD AND CMOS DEVICES PACKAGE (Unit : mm) 48 QFP (QFP048-P-0707) 0.15±0.05 0.2±0.08 M (1.0) 25 36 37 48 13 7.0±0.2 12 (1.0) 0.1±0.1 9 0.1 8.0±0.2 0.65±0.2 1.45±0.2 9.0±0.3 Package base plane 1 (1.0) (1.0) 7.0±0.2 0.08 24 9.0±0.3 0.5TYP.