SIPEX SP6120BEY

SP6120B
®
Low Voltage, AnyFETTM, Synchronous ,Buck Controller
Ideal for 2A to 10A, High Performance, DC-DC Power Converters
■ Optimized for Single Supply, 3V - 5.5V Applications
N/C 1
16 BST
■ High Efficiency: Greater Than 95% Possible
15 GH
ENABLE 2
TM"
■ "AnyFET Technology: Capable Of Switching Either
14 SWN
ISP 3
SP6120B
PFET Or NFET High Side Switch
13 GND
ISN 4
■ Selectable Discontinuous or Continuous Conduction
16 Pin TSSOP
12 PGND
VFB 5
Mode
11 GL
COMP 6
■ Fast Transient Response from Window Comparator
10 VCC
SS 7
■ 16-Pin TSSOP, Small Size
9 PROG
ROSC 8
■ Accurate 1% Reference Over Line, Load and Temperature
■ Accurate 10% Frequency
Now Available in Lead Free Packaging
■ Accurate, Rail to Rail, 43mV, Over-Current Sensing
APPLICATIONS
■ Resistor Programmable Frequency
■ DSP
■ Resistor Programmable Output Voltage
■ Microprocessor Core
■ Low Quiescent Current: 950µA, 10µA in Shutdown
■ I/O & Logic
■ Hiccup Over-Current Protection
■ Industrial Control
■ Capacitor Programmable Soft Start
■ Distributed Power
■ Guaranteed Boost Voltage to Enhance High Side NFET ■ Low Voltage Power
DESCRIPTION
The SP6120B is a fixed frequency, voltage mode, synchronous PWM controller designed to
work from a single 5V or 3.3V input supply. Sipex's unique "AnyFETTM" Technology allows
the SP6120B to be used for resolving a multitude of price/performance trade-offs. It is
separated from the PWM controller market by being the first controller to offer precision,
speed, flexibility, protection and efficiency over a wide range of operating conditions.
NMOS High Side Drive
PROG = GND
NC
ENABLE
ENABLE
ISP
RZ
15k
CZ
4.7nF
VIN
QT
CIN
330µF x 2
NC
CS
RS
22.1k
39nF
L1
GND
ROSC
18.7k
PMOS High Side Drive
PROG = VCC
3.3V
CB
1µF
SWN
PGND
ROSC
MBR0530
CBST
1µF
GH
SP6120B
VFB
SS
CSS
0.33µF
BST
ISN
COMP
CP
100pF
®
2.5µH
QB
GL
VCC
DS
VIN
ENABLE
ISP
RI
10k
CP
100pF
QT, QB = FAIRCHILD FDS6690A
QT1 = FAIRCHILD FDS6375 (PMOS only)
L1 = PANASONIC ETQP6F2R5SFA
CSS
0.33µF
VFB
PGND
ROSC
ROSC
18.7k
QT1
GH
39nF
QB
VIN
DS
1.9V
1A to 8A
VOUT
2.5µH
GL
VCC
CS
RS
22.1k
L1
SWN
GND
SS
RZ
15k
CVCC
2.2µF
SP6120B
VIN
BST
ISN
COMP
PROG
CZ
4.7nF
Date: 5/25/04
ENABLE
1.9V
1A to 8A
VOUT
COUT
470µF x 3
RF
5.23k
®
3.3V
CIN
330µF x 2
COUT
470µF x 3
RF
5.23k
PROG
CVCC
2.2µF
RI
10k
DS = STMICROELECTRONICS STPS2L25U
CIN = SANYO 6TPB330M
COUT = SANYO 4TPB470M
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
1
© Copyright 2004 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability.
Peak Output Current < 10µs
GH, GL ........................................................................ 2A
Operating Temperature Range
SP6120C ................................................ 0°C to +70°C
SP6120E .............................................. -40°C to +85°C
Junction Temperature, TJ ...................................... +125°C
Storage Temperature Range .................. -65˚C to +150˚C
Power Dissipation
Lead Temperature (soldering 10 sec) ................... +300˚C
ESD Rating ........................................................ 2kV HBM
VCC ............................................................................... 7V
BST ........................................................................ 13.2V
BST-SWN .................................................................... 7V
SWN .................................................................. -1V to 7V
GH ..................................................... -0.3V to BST +0.3V
GH-SWN ..................................................................... 7V
All Other Pins ....................................... -0.3V to VCC +0.3V
SPECIFICATIONS
Unless otherwise specified: 3.0V < VCC <5.5V, 3.0V < BST < 13.2V, ROSC = 18.7kΩ, CCOMP = 0.1µF, CSS = 0.1µF, ENABLE =
3V, CGH = CGL = 3.3nF, VFB = 1.25V, ISP = ISN = 1.25V, SWN = GND = PGND = 0V, -40°C < TAMB <85°C (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC Supply Current
No Switching
-
0.95
1.8
mA
VCC Supply Current (Disabled)
ENABLE = 0V
-
5
20
µA
BST Supply Current
No Switching, VBST = VCC
No Switching, VCC = 5V, VBST = 10V
-
1
100
20
150
µA
µA
µA
QUIESCENT CURRENT
ERROR AMPLIFIER
Error Amplifier Transconductance
600
µs
COMP Sink Current
VFB = 1.35V, COMP = 0.5V, No Faults
15
35
65
COMP Source Current
VFB = 1.15V, COMP = 1.6V
15
35
65
COMP Output Impedence
3
VFB Input Bias Current
µA
MΩ
-
60
100
nA
1.238
1.250
1.262
V
REFERENCE
Error Amplifier Reference
Trimmed with Error Amp in Unity Gain
VFB 3% Low Comparator
3
%VREF
VFB 3% High Comparator
3
%VREF
OSCILLATOR & DELAY PATH
Oscillator Frequency
Oscillator Frequency #2
ROSC = 10.2kΩ
Duty Ratio
Loop In Control -100% DC possible
ROSC Voltage
Minimum GH Pulse Width
Date: 5/25/04
270
300
330
kHz
450
500
550
kHz
95
%
Information Only - Moves
with Oscillator Trim
0.65
V
VCC > 4.5V, Ramp up COMP
Voltage > 0.6V until GH starts
Switching
120
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
2
250
ns
© Copyright 2004 Sipex Corporation
SPECIFICATIONS: continued
Unless otherwise specified: 3.0V < VCC <5.5V, 3.0V < BST < 13.2V, ROSC = 18.7kΩ, CCOMP = 0.1µF, CSS = 0.1µF, ENABLE =
3V, CGH = CGL = 3.3nF, VFB = 1.25V, ISP = ISN = 1.25V, SWN = GND = PGND = 0V, -40°C < TAMB <85°C (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
25
50
70
µA
2
5
7
µA
200
500
-
µA
SOFTSTART
SS Charge Current
VSS = 1.5V
SS Discharge Current
VSS = 1.5V
COMP Discharge Current
VCOMP = 0.5V, Fault Initiated
COMP Clamp Voltage
VFB < 1.0V, VSS = 2.5V
2.0
2.4
2.8
V
1.7
2.0
2.2
V
SS Fault Reset
0.2
0.25
0.3
V
SS Clamp Voltage
2.0
2.4
2.8
V
32
43
54
mV
-
60
250
SS Ok Threshold
OVER CURRENT & ZERO CURRENT COMPARATORS
Over Current Comparator
Threshold Voltage
Rail to Rail Common Mode Input
ISN, ISP Input Bias Current
Zero Current Comparator
Threshold
VISP - VISN
2
nA
mV
UVLO
VCC Start Threshold
2.75
2.85
2.95
V
VCC Stop Threshold
2.65
2.75
2.9
V
ENABLE
Enable Threshold
ON
OFF
1.45
0.65
Enable Pin Source Current
V
0.6
4
9
µA
VCC > 4.5V
-
40
110
ns
GH Fall Time
VCC > 4.5V
-
40
110
ns
GL Rise Time
VCC > 4.5V
-
40
110
ns
GL Fall Time
VCC > 4.5V
-
40
110
ns
GH to GL Non-Overlap Time
VCC > 4.5V
0
60
140
ns
GL to GH Non-Overlap Time
VCC > 4.5V
0
60
140
ns
VBST OK Threshold
VCC = 3.0V, FB=1.15V, Search GL High
VCC = 5.5V, FB=1.15V, Search GL High
4.0
7.3
4.8
7.8
5.0
8.3
V
V
Forced GL ON
VBST < VBST OK Threshold, FB =1.15V
200
350
650
ns
GATE DRIVER
GH Rise Time
Note 1: Specifications to -40°C are guaranteed by design, characterization and correlation with statistical process control.
Date: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
3
© Copyright 2004 Sipex Corporation
PIN DESCRIPTION
NAME
FUNCTION
PIN NUMBER
1
N/C
No Connection
2
ENABLE
3
ISP
Current Sense Positive Input: Rail to Rail Input for Over-Current Detection,
43mV threshold with 10µs (typ) response time.
4
ISN
Current Sense Negative Input: Rail to Rail input for Over-Current Detection.
5
VFB
Feedback Voltage Pin: Inverting input of the error amplifier and serves as the
output voltage feedback point for the buck converter. The output voltage is
sensed and can be adjusted through an external resistor divider.
6
COMP
7
SS
8
ROSC
9
PROG
10
VCC
I.C. Supply Pin: ESD structures also hooked to this pin. Properly bypass this
pin to PGND with a low ESL/ESR ceramic capacitor.
11
GL
Synchronous FET Driver: 1nF/20ns typical drive capability.
12
PGND
TTL compatible input with internal 4uA pullup. Floating or Venable> 1.5V will
enable the part, Venable < 0.65V disables part.
Error Amplifier Compensation Pin: A lead lag network is typically connected
to this pin to compensate the feedback loop. This pin is clamped by the SS
voltage and is limited to 2.8V maximum.
Soft Start Programming Pin: This pin sources 50µA on start-up. A 0.01µF to
1µF capacitor on this pin is typically enough capacitance to soft start a power
supply. In addition, hiccup mode timing is controlled by this pin through the
5µA discharge current. The SS voltage is clamped to 2.7V maximum.
Frequency Programming Pin: A resistor to ground is used to program
frequency. Typical values - 18,700Ω, 300kHz; 10,200Ω, 500kHz.
Programming Pin:
PROG = GND; MODE = NFET/CONTINOUS
PROG = 68kΩ to GND; MODE = NFET/DISCONTINOUS
PROG = VCC; MODE = PFET/CONTINOUS
PROG = 68kΩ to VCC; MODE = PFET/DISCONTINOUS
Power Ground Pin: Used for Power Stage. Connect Directly to GND at I.C.
pins for optimal performance.
13
GND
Ground Pin: Main ground pin for I.C.
14
SWN
Switch Node Reference: High side MOSFET driver reference. Can also be
tied to GND for low voltage applications.
15
GH
HIgh Side MOSFET Driver: Can be NFET or PFET depending on Program
Mode. 1nF/20ns typical drive capability. Maximum voltage rating is
referenced to SWN.
16
BST
High Side Driver Supply Pin. When VBST is less than VBST OK Threshold, GL
is forced to turn on for at least 300ns. This is intended for enough time to
charge the BST capacitor.
Date: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
4
© Copyright 2004 Sipex Corporation
BLOCK DIAGRAM
SS
+
2V
-
VFB 3% Low ENABLE
-
VFB
3%
+ -
Reference
ENABLE 2
1.25V
3%
- +
+
Window
Comparator
Logic
-
+
VFB 5
Program
Logic
RESET
Dominant
PWM Latch
-
-
9 PROG
OFF 100%
16 BST
GM
Error Amplifier
SS
NFET/PFET
+
VFB
GND 13
Continuous/
Discontinuous
ON 100%
+
Q
15 GH
Driver
Logic
R
Synchronous
Driver
QPWM
14 SWN
11 GL
S
12 PGND
COMP 6
VCC 10
2.85 VON
2.75 VOFF
ISP 3
Set Dominant
Fault Latch
Soft Start
& Hiccup Logic
TOFF
S
+
OVC
Q FAULT
+
-
10µs
430mV
8 ROSC
F (kHz) = 5.7E6/ROSC (Ω)
+
x 10
ISN 4
0.65V
ICHARGE
1V RAMP
UVLO
R
-
+
-
Zero crossing detect
7
SS
250mV
+
APPLICATION SCHEMATIC
NMOS High Side Drive
PROG = GND
NC
ENABLE
®
ENABLE
ISP
CP
100pF
VFB
PGND
CZ
4.7nF
ROSC
CIN
330µF x 2
QT
SWN
GND
SS
CSS
0.33µF
VIN
GH
SP6120B
3.3V
CB
1µF
CBST
1µF
BST
ISN
COMP
RZ
15k
MBR0530
RS
CS
22.1k
L1
39nF
2.5µH
QB
GL
DS
VIN
VCC
1.9V
1A to 8A
VOUT
COUT
470µF x 3
RF
5.23k
PROG
CVCC
2.2µF
ROSC
18.7k
RI
10k
Figure 1. Schematic 3.3V to 1.9V Power Supply
CIN = SANYO 6TPB330M
COUT = SANYO 4TPB470M
QT, QB = FAIRCHILD FDS6690A
L1 = PANASONIC ETQP6F2R5SFA
DS = STMICROELECTRONICS STPS2L25U
Date: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
5
© Copyright 2004 Sipex Corporation
Typical Performance Characteristics
Refer to circuit in Figure 1 with VIN = 3.3V; VOUT = 1.9V, ROSC = 18.7kΩ, and TAMB = +25°C unless otherwise noted.
100
1.925
1.920
90
1.915
VOUT (V)
Efficiency (%)
1.910
80
70
1.905
1.900
1.895
1.890
60
1.885
1.880
50
1.875
0
2
4
6
8
10
0
1
2
3
4
5
Load Current (A)
Output Current (A)
Figure 2. Efficiency vs. Output Current
Figure 3. Load Regulation
VOUT
VOUT
Gate High
Gate High
IOUT(1A/div)
IOUT(5A/div)
Figure 5. Load Step Response: 0.4A to 7A
Figure 4. Load Step Response: 0.4A to 2A
VOUT
VOUT
VIN
VIN
Soft Start
Soft Start
IIN (1A/div)
IOUT (5A/div)
Figure 6. Start-Up Response: 5A Load
Date: 5/25/04
Figure 7. Overcurrent: 9A Load
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
6
© Copyright 2004 Sipex Corporation
Typical Performance Characteristics
Unless otherwise specified: VCC = BST = ENABLE = 3.3V, ROSC = 18.7kΩ, CCOMP = 0.1µF, CSS = 0.1µF, CGH = CGL = 3.3nF, VFB = 1.25V,
ISP = ISN = 1.25V, SWN = GND = PGND = 0V, TAMB = 25°C.
0.30
48
46
0.10
44
0.00
42
Overcurrent (mV)
1.25VREF (%)
0.20
-0.10
-0.20
-40
-15
10
35
Temperature (°C)
60
85
Figure 8. Error Amplifier Reference vs. Temperature
40
38
-40
-15
10
35
Temperature (°C)
60
85
Figure 9. Overcurrent Comparator Threshold Voltage
vs. Temperature
-44
5.25
SS Discharge (µA)
5.20
SS Charge (µA)
-45
-46
5.10
5.05
-47
-40
-15
10
35
Temperature (°C)
60
5.00
-40
85
-2.2
3.4
-2.4
VFB Low (% VREF)
3.6
3.2
3.0
60
85
-2.6
-2.8
-15
10
35
60
-3.2
-40
85
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 12. VFB 3% High Comparator vs. Temperature
Date: 5/25/04
10
35
Temperature (°C)
-3.0
2.8
2.6
-40
-15
Figure 11. SS Discharge Current vs. Temperature with
VSS = 1.5V
Figure 10. SS Charge Current vs. Temperature with
VSS = 1.5V
VFB High (% VREF)
5.15
Figure 13. VFB 3% Low Comparator vs. Temperature
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
7
© Copyright 2004 Sipex Corporation
Typical Performance Characteristics
Unless otherwise specified: VCC = BST = ENABLE = 3.3V, ROSC = 18.7k, CCOMP = 0.1µF, CSS = 0.1µF, CGH = CGL = 3.3nF, VFB = 1.25V,
2.900
2.850
2.875
2.825
VCC Stop (V)
VCC Start (V)
ISP = ISN = 1.25V, SWN = GND = PGND = 0V, TAMB = 25°C.
2.850
2.800
2.775
2.825
2.750
2.800
-40
-15
10
35
Temperature (°C)
60
-40
85
Figure 14. VCC Start Threshold vs. Temperature
-15
10
35
Temperature (°C)
60
85
Figure 15. VCC Stop Threshold vs. Temperature
800
302
Frequency (kHz)
Frequency (kHz)
700
301
300
600
500
400
299
300
298
200
-40
-15
10
35
Temperature (°C)
60
85
5
10
15
20
ROSC (kΩ)
25
30
Figure 17. Oscillator Frequency vs. ROSC with VCC = 5V
and CGH = CGL = Open.
Figure 16. Oscillator Frequency vs. Temperature
THEORY OF OPERATION
General Overview
The SP6120B is a constant frequency, voltage
mode PWM controller for low voltage, DC/DC
step down converters. It has a main loop where
an external resistor (ROSC) sets the frequency and
the driver is controlled by the comparison of an
error amp output (COMP) and a 1V ramp signal.
The error amp has a transconductance of 600µS,
an output impedance of 3 MΩ, an internal pole at
2 MHz and a 1.25V reference input. Although
the main control loop is capable of 0% and 100%
duty cycle, its response time is limited by the
external component selection. Therefore, a secondary loop, including a window comparator
positioned 3% above and below the reference,
has been added to insure fast response to line and
load transients. A unique “Ripple & Frequency
Date: 5/25/04
Independent” algorithm, added to the secondary
loop, insures that the window comparator does
not interfere with the main loop during normal
operation. In addition to receiving driver commands from the main and secondary loops, the
Driver Logic is also controlled by the Programming Logic, Fault Logic and Zero Crossing
Comparator. The Programming Logic tells the
Driver Logic whether the controller is using a
PFET or NFET high side driver as well as whether
the controller is operating in continuous or discontinuous mode. The Fault Logic holds the high
and low side drivers off if VCC dips below 2.75V,
if an over current condition exists, or if the part
is disabled through the ENABLE pin. The Zero
Crossing Comparator turns the lower driver off
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
8
© Copyright 2004 Sipex Corporation
General Overview: continued
on, the BST pin may not be high enough to fully
enhance the switch. To prevent this operation,
SP6120B monitors the BST pin voltage in reference to the VCC voltage. When the BST pin
voltage is less than VBST OK threshold, the
controller forces the GL to turn on for MINIMUM GL ON at the end of the switching cycle.
This provides enough time to recharge the CBST
and ensures the proper operation of the bootstrap circuit.
if the conduction current reaches zero and the
Driver Logic has made an attempt to turn the
lower driver on and the Programming Logic is
set for discontinuous mode. Lastly, the 4Ω drivers have internal gate non-overlap circuitry and
are designed to drive MOSFETs associated with
converter designs in the 5A to 10A range. Typically the high side driver is referenced to the
SWN pin; further improving the efficiency and
performance of the converter.
UVLO
Assuming that the ENABLE pin is either pulled
high or floating, the voltage on the VCC pin then
determines operation of the SP6120B. As VCC
rises, the UVLO block monitors VCC and keeps
the high side and low side MOSFETs off and the
COMP and SS pins low until VCC reaches 2.85V.
If no faults are present, the SP6120B will initiate
a soft start when VCC exceeds 2.85V. Hysteresis
(about 100mV) in the UVLO comparator provides noise immunity at start-up.
ENABLE
Low quiescent mode or “Sleep Mode” is initiated by pulling the ENABLE pin below 650mV.
The ENABLE pin has an internal 4µA pull-up
current and does not require any external interface for normal operation. If the ENABLE pin is
driven from a voltage source, the voltage must
be above 1.45V in order to guarantee proper
“awake” operation. Assuming that VCC is above
2.85V, the SP6120B transitions from “Sleep
Mode” to “Awake Mode” in about 20µs to 30µs
and from “Awake Mode” to “Sleep Mode” in a
few microseconds. SP6120B quiescent current
in sleep mode is 20µA maximum. During Sleep
Mode, the high side and low side MOSFETs are
turned off and the COMP and SS pins are held
low.
Soft Start
(see figures on next page)
Soft start is required on step-down controllers to
prevent excess inrush current through the power
train during start-up. Typically this is managed
by sourcing a controlled current into a programming capacitor (on the SS pin) and then using the
voltage across this capacitor to slowly ramp up
either the error amp reference or the error amp
output (COMP). The control loop creates narrow width driver pulses while the output voltage
is low and allows these pulses to increase to their
steady-state duty cycle as the output voltage
increases to its regulated value. As a result of
controlling the inductor volt*second product
during start-up, inrush current is also controlled.
The presence of the output capacitor creates
extra current draw during start-up. Simply stated,
dVOUT/dt requires an average sustained current
in the output capacitor and this current must be
considered while calculating peak inrush current
and over current thresholds. Since the SP6120B
ramps up the error amp reference voltage, an
expression for the output capacitor current can
be written as:
Bootstrap Circuit
When SP6120B is programmed to drive a high
side N channel MOSFET, a bootstrap circuit is
required to generate a voltage higher than VIN to
fully enhance the top MOSFET. A typical bootstrap only requires a capacitor and diode shown
as CBST and DBST in the application circuit on the
front page. When the bottom MOSFET QB is
turned on, DBST is forward biased and charges
the CBST close to VIN. When the top MOSFET
turn on, the switch node swings to the VIN
voltage. Now the voltage at the BST pin is 2*VIN
and DBST is reverse biased. The BST pin voltage
powers the high side MOSFET driver, and thus
the GH output goes up to 2*VIN to provide a VDS
equal to VIN.
Under certain conditions, the bottom MOSFET
may not turn on long enough to replenish CBST
voltage. Therefore, when the top MOSFET turns
ICOUT = (COUT/CSS) * (VOUT/1.25) * 50µA
Date: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
9
© Copyright 2004 Sipex Corporation
As the figure shows, the SS voltage controls a
variety of signals. First, provided all the external
fault conditions are removed, the fault latch is reset
and the SS cap begins to charge. When the SS
voltage reaches around 0.3V, the error amp reference begins to track the SS voltage while maintaining the 0.3V differential. As the SS voltage reaches
0.7V, the driver begins to switch the high side and
low side MOSFETs with narrow pulses in an
effort to keep the converter output regulated. As
the error amp reference ramps upward, the driver
pulses widen until a steady state value is reached.
The “bump” in the inductor current transfer curve
is indicative of excess charge current incurred due
to the finite propagation delay of the controller.
When the SS voltage reaches 2.0V, the secondary loop including the 3% window comparator
is enabled. Lastly, the SS voltage is clamped at
2.4V, ending the soft start charge cycle.
Hiccup Mode
When the converter enters a fault mode, the
driver holds the high side and low side MOSFETs
off for a finite period of time. Provided the part
is enabled, this time is set by the discharge of the
SS capacitor. The discharge time is roughly 10
times the charge interval thereby giving the
power supply plenty of time to cool during an
over current fault. The driver off-time is predominantly determined by the discharge time.
Restart will occur just like a normal soft start
cycle.
However, if a fault occurs during the soft start
charge cycle, the FAULT latch is immediately
set, turning off the high side and low side
MOSFETs. The MOSFETs remain off during
the remainder of the charge cycle and subsequent discharge cycle of the SS capacitor. Again,
provided there are no external fault conditions,
the FAULT latch will be reset when the SS
voltage reaches 250 mV.
2.4V
2.0V
SS Voltage
Over Current Protection
0.7V
0.25V
The SP6120B over current protection scheme is
designed to take advantage of three popular
detection schemes: Sense Resistor, Trace Resistor or Inductor Sense. Because the detection
threshold is only 43mV, both trace resistor and
inductor sense become attractive protection
schemes. The inductor sense scheme adds no
additional dc loss to the converter and is an
excellent alternative to Rdson based schemes;
dVSS/dt = 50µA/CSS
0V
Error Amplifier
Reference
1.25V
Voltage
VOUT = V(Eamp REF)* (1+RF/RI)
0V
ILOAD
Inductor Current
0V
43mV
V(VCC)
V(ISP) - V(ISN)
FAULT
Reset Voltage
0V
0V
2.4V
2.0V
V(VCC)
SS Voltage
SWN
Voltage
250mV
0V
V(VCC)
0V
V(VCC)
FAULT Voltage
3% Low
Enable Voltage
0V
0V
TIME
Date: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
10
© Copyright 2004 Sipex Corporation
Over Current Protection: continued
providing continuous current sensing and flexible MOSFET selection. An internal, 10µs filter
conditions the over current signal from transients generated during load steps. In addition,
because the over current inputs, ISP and ISN, are
capable of rail to rail operation, the SP6120B
provides excellent over current protection during conditions where VIN approaches VOUT.
Continuous
Load
Current
0A
GH, GL
Voltage
Zero Crossing Detection
In some applications, it may be undesirable to
have negative conduction current in the inductor. This situation happens when the ripple current in the inductor is higher than the load current. Therefore, the SP6120B provides an option
for “discontinuous” operation. If the Program
Logic (see next section) is set for discontinuous
mode, then the Driver Logic looks at the Zero
Crossing Comparator and the state of the lower
gate driver. If the low side MOSFET was “on”
and V(ISP)-V(ISN) < 0 then the low side
MOSFET is immediately turned off and held off
until the high side MOSFET is turned “on”.
When the high side MOSFET turns “on” , the
Driver Logic is reset. The following figures
show continuous and discontinuous operation
for a converter with an NFET high side MOSFET.
0V
0V
Discontinuous
Load
Current
0A
GH, GL
Voltage
0V
0V
Discontinuous vs. Continuous Mode
TIME
The discontinuous mode is used when better
light load efficiency is desired, for example in
portable applications. Additionally, for power
supply sequencing in some applications the DCDC converter output is pre-charged to a voltage
through a switch at start-up, and discontinuous
operation would be required to prevent reverse
inductor current from discharging the pre-charge
voltage. The continuous mode is preferable for
lower noise and EMI applications since the
discontinuous mode can cause ringing of the
switch node voltage when it turns both switches
off. Another example where continuous mode
could be required is one where the inductor has
an extra winding used for an over-winding regulator and thus continuous conduction is necessary to produce this second output voltage.
Date: 5/25/04
Program Logic
The Program pin (PROG) of the SP6120B adds
a new level of flexibility to the design of DC/DC
converters. A 10µA current flows either into or
out of the Program pin depending on the initial
potential presented to the pin. If no resistor is
present, the Program Logic simply looks at the
potential on the pin, sets the mode to “continuous” and programs NFET or PFET high side
drive accordingly. If the 68kΩ resistor is present,
the voltage drop across the resistor signals the
SP6120B to put the Driver Logic in “discontinuous” mode. With one pin and a 68kΩ resistor, the
SP6120B can be configured for a variety of
operating modes:
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
11
© Copyright 2004 Sipex Corporation
Program Logic: continued
tor detects whether the output voltage is above
or below the regulated value by 3%. Then, a
proprietary “Ripple & Frequency Independent”
algorithm synchronizes the output of the window comparator with the peak and valley of the
inductor current waveform. 3% low detection is
synchronized with inductor current peak; 3%
high detection is synchronized with the inductor
current valley. However, in order to eliminate
any additional loops, the current peak and valley
are determined by the edges associated with the
on-time in the main loop. The set pulse corresponding to the start of an on-time indicates a
PROGRAM LOGIC TRUTH TABLE
NFET
Continuous
68 kΩ to GND
NFET
Discontinuous
Short to VCC
PFET
Continuous
68 kΩ to VCC
PFET
Discontinous
The NFET/PFET programmability is for the
high side MOSFET. When designing DC/DC
converters, it is not always obvious when to use
an NFET with a charge pump or a simple PFET
for the high side MOSFET. Often, the controller
has to be changed, making performance evaluations difficult. This difficulty is worsened by the
limited availability of true low voltage controllers. In addition, by also programming the mode,
continuous or discontinuous, switch mode power
designs that are successful in bus applications
can now find homes in portable applications.
MAX
DC Load
Current
MIN
0A
Output
Voltage
Secondary Loop (3% Window Comparator)
VOUT
Date: 5/25/04
3% High Sync.
DSP, microcontroller and microprocessor applications have very strict supply voltage requirements. In addition, the current requirements to
these devices can change drastically. Linear
regulators, typically the workhorse for DC/DC
step-down, do a great job managing accuracy
and transient response at the expense of efficiency. On the other hand, PWM switching
regulators typically do a great job managing
efficiency at the expense of output ripple and
line/load step response. The trick in PWM
controller design is to emulate the transient response of the linear regulator.
Of course improving transient response should
be transparent to the power supply designer.
Very often this is not the case. Usually the very
circuitry that improves the controllers transient
response adversely interferes with the main PWM
loop or complicates the board level design of the
power converter.
The SP6120B handles line/load transient response in a new way. First, a window compara-
.
1.25V Cross.
Short to GND
3% Low
MODE
3% Low Sync.
NFET OR PFET
3% High
PROGRAM PIN
Reset
Main Loop
Set
V(VCC)
3% High
Latch On
0V
V(VCC)
3% Low
Latch On
0V
TIME
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
12
© Copyright 2004 Sipex Corporation
Output Drivers
Secondary Loop (3% Window Comparator):
continued
The driver stage consists of one high side, 4Ω
driver, GH and one low side, 4Ω, NFET driver,
GL. As previously stated, the high side driver can
be configured to drive a PFET or an NFET high
side switch. The high side driver can also be
configured as a switch node referenced driver.
Due to voltage constraints, this mode is mandatory
for 5V, single supply, high side NFET applications. The following figure shows typical driver
waveforms for the 5V, high side NFET design.
As with all synchronous designs, care must be
taken to ensure that the MOSFETs are properly
chosen for non-overlap time, peak current capability and efficiency.
current valley and the reset pulse corresponding
to the end of an on-time indicates a current peak.
In effect, the main loop determines the status of
the secondary loop.
Notice that the output voltage appears to coast
toward the regulated value during periods where
the main loop would be telling the drivers to
switch. It is during this interval that the 3%
window comparator has taken control away from
the main loop. The main loop regains control
only if the output voltage crosses through its
regulated value. Also notice where the 3% comparator takes over. The output voltage is considered “high” only if the trough of the ripple is
above 3%. The output voltage is considered
“low” only if the peak of the ripple is below 3%.
By managing the secondary loop in this fashion,
the SP6120B can improve the transient response
of high performance power converters without
causing strange disturbances in low to moderate
performance systems.
GATE DRIVER TEST CONDITONS
5V
90%
GH (GL)
FALL TIME
2V
10%
5V
90%
RISE TIME
2V
GH (GL)
10%
Driver Logic
Signals from the PWM latch (QPWM), Fault
latch (FAULT), Program Logic, Zero Crossing
Comparator, and 3% Window Comparators all
flow into the Driver Logic. The following is a
truth table for determining the state of the GH and
GL voltages for given inputs:
NON-OVERLAP
V(BST)
GH
Voltage
0V
DRIVER LOGIC TRUTH TABLE
V(VCC)
FAULT
1
1
0
0
0
0
0
0
0
0
QPWM or
3% COMP
X
X
1
1
0
0
0
0
0
0
NFET/PFET
N
P
N
P
N
P
N
P
N
P
CONT/DISC
X
X
X
X
C
C
D
D
D
D
ZERO CROSS
X
X
X
X
X
X
0
0
1
1
GH
0
1
1
0
0
1
0
1
0
1
GL
0
0
0
0
1
1
1
1
0
0
GL
Voltage
0V
V(VCC = VIN)
SWN
Voltage
~0V
The QPWM and 3% Comparators are grouped
together because 3% Low is the same as QPWM
= 1 and 3% High is the same as QPWM = 0.
~V(Diode) V
~2V(VIN)
BST
Voltage
~V(VIN)
TIME
Date: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
13
© Copyright 2004 Sipex Corporation
APPLICATIONS INFORMATION
duce considerable ac core loss, especially when
the inductor value is relatively low and the
ripple current is high. Ferrite materials, on the
other hand, are more expensive and have an
abrupt saturation characteristic with the inductance dropping sharply when the peak design
current is exceeded. Nevertheless, they are preferred at high switching frequencies because
they present very low core loss and the design
only needs to prevent saturation. In general,
ferrite or molypermalloy materials are better
choice for all but the most cost sensitive applications.
Inductor Selection
There are many factors to consider in selecting
the inductor including cost, efficiency, size and
EMI. In a typical SP6120B circuit, the inductor
is chosen primarily for value, saturation current
and DC resistance. Increasing the inductor value
will decrease output voltage ripple, but degrade
transient response. Low inductor values provide the smallest size, but cause large ripple
currents, poor efficiency and more output capacitance to smooth out the larger ripple current. The inductor must also be able to handle
the peak current at the switching frequency
without saturating, and the copper resistance in
the winding should be kept as low as possible to
minimize resistive power loss. A good compromise between size, loss and cost is to set the
inductor ripple current to be within 20% to 40%
of the maximum output current.
The switching frequency and the inductor operating point determine the inductor value as
follows:
L=
The power dissipated in the inductor is equal to
the sum of the core and copper losses. To minimize copper losses, the winding resistance needs
to be minimized, but this usually comes at the
expense of a larger inductor. Core losses have a
more significant contribution at low output current where the copper losses are at a minimum,
and can typically be neglected at higher output
currents where the copper losses dominate. Core
loss information is usually available from the
magnetic vendor.
VOUT (V IN (max) − VOUT )
VIN (max) FS Kr I OUT ( max)
The copper loss in the inductor can be calculated
using the following equation:
where:
FS = switching frequency
Kr = ratio of the ac inductor ripple current to
the maximum output current
PL( Cu) = I L2 ( RMS ) RWINDING
where IL(RMS) is the RMS inductor current that
can be calculated as follows:
The peak to peak inductor ripple current is:
I PP =
IL(RMS) = IOUT(max) 1 + 1
3
VOUT (VIN (max) − VOUT )
VI N (max) FS L
)
The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the
type and quantity of the output capacitors. The
ESR must be small enough that both the resistive voltage deviation due to a step change in the
load current and the output ripple voltage do not
exceed the tolerance limits expected on the
output voltage. During an output load transient,
the output capacitor must supply all the additional current demanded by the load until the
SP6120B adjusts the inductor current to the new
value. Therefore the capacitance must be large
I PP
2
and provide low core loss at the high switching
frequency. Low cost powdered iron cores have
a gradual saturation characteristic but can intro-
Date: 5/25/04
IOUT(max)
2
Output Capacitor Selection
Once the required inductor value is selected, the
proper selection of core material is based on
peak inductor current and efficiency requirements.
The core material must be large enough not to
saturate at the peak inductor current
I PEAK = I OUT (max) +
(
IPP
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
14
© Copyright 2004 Sipex Corporation
enough so that the output voltage is held up
while the inductor current ramps up or down to
the value corresponding to the new load current.
Additionally, the ESR in the output capacitor
causes a step in the output voltage equal to the
ESR value multiplied by the change in load
current. Because of the fast transient response
and inherent 100% and 0% duty cycle capability provided by the SP6120B when exposed to
output load transient, the output capacitor is
typically chosen for ESR, not for capacitance
value.
a solid electrolytic chip capacitor that has low
ESR and high capacitance. For the same ESR
value, POSCAP has lower profile compared
with tantalum capacitor.
Input Capacitor Selection
The input capacitor should be selected for ripple
current rating, capacitance and voltage rating.
The input capacitor must meet the ripple current
requirement imposed by the switching current.
In continuous conduction mode, the source current of the high-side MOSFET is approximately
a square wave of duty cycle VOUT/VIN. Most of
this current is supplied by the input bypass
capacitors. The RMS value of input capacitor
current is determined at the maximum output
current and under the assumption that the peak
to peak inductor ripple current is low, it is given
by:
ICIN(rms) = IOUT(max) √D(1 - D)
The output capacitor’s ESR, combined with the
inductor ripple current, is typically the main
contributor to output voltage ripple. The maximum allowable ESR required to maintain a
specified output voltage ripple can be calculated
by:
RESR ≤
∆VOUT
I PP
The worse case occurs when the duty cycle D is
50% and gives an RMS current value equal to
IOUT /2. Select input capacitors with adequate
ripple current rating to ensure reliable operation.
where:
∆VOUT = peak to peak output voltage ripple
IPP = peak to peak inductor ripple current
The power dissipated in the input capacitor is:
The total output ripple is a combination of the
ESR and the output capacitance value and can
be calculated as follows:
(
∆VOUT = IPP (1 – D)
COUTFS
)
2
PCIN = ICIN
( rms ) R ESR ( CIN )
This can become a significant part of power
losses in a converter and hurt the overall energy
transfer efficiency.
2
+ (IPPRESR)2
where:
The input voltage ripple primarily depends on
the input capacitor ESR and capacitance. Ignoring the inductor ripple current, the input voltage
ripple can be determined by:
FS = switching frequency
D = duty cycle
COUT = output capacitance value
∆ VIN = I out (max) RE SR (CIN ) +
Recommended capacitors that can be used effectively in SP6120B applications are: lowESR aluminum electrolytic capacitors, OS-CON
capacitors that provide a very high performance/
size ratio for electrolytic capacitors and lowESR tantalum capacitors. AVX TPS series and
Kemet T510 surface mount capacitors are popular tantalum capacitors that work well in
SP6120B applications. POSCAP from Sanyo is
Date: 5/25/04
I OUT ( MAX )VOUT (VI N − VOUT )
FS C INV IN
2
The capacitor type suitable for the output capacitors can also be used for the input capacitors. However, exercise extra caution when tantalum capacitors are considered. Tantalum capacitors are known for catastrophic failure when
exposed to surge current, and input capacitors
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
15
© Copyright 2004 Sipex Corporation
are prone to such surge current when power
supplies are connected ‘live’ to low impedance
power sources. Certain tantalum capacitors, such
as AVX TPS series, are surge tested. For generic tantalum capacitors, use 2:1 voltage derating to protect the input capacitors from surge
fall-out.
synchronous buck converters of efficiency over
90%, allow no more than 4% power losses for
high or low side MOSFETs. For input voltages
of 3.3V and 5V, conduction losses often dominate switching losses. Therefore, lowering the
RDS(ON) of the MOSFETs always improves
efficiency even though it gives rise to higher
switching losses due to increased Crss.
MOSFET Selection
Top and bottom MOSFETs experience unequal
conduction losses if their on time is unequal. For
applications running at large or small duty cycle,
it makes sense to use different top and bottom
MOSFETs. Alternatively, parallel multiple
MOSFETs to conduct large duty factor.
The losses associated with MOSFETs can be
divided into conduction and switching losses.
Conduction losses are related to the on resistance of MOSFETs, and increase with the load
current. Switching losses occur on each on/off
transition when the MOSFETs experience both
high current and voltage. Since the bottom
MOSFET switches current from/to a paralleled
diode (either its own body diode or a Schottky
diode), the voltage across the MOSFET is no
more than 1V during switching transition. As a
result, its switching losses are negligible. The
switching losses are difficult to quantify due to
all the variables affecting turn on/off time. However, the following equation provides an approximation on the switching losses associated
with the top MOSFET driven by SP6120B.
RDS(ON) varies greatly with the gate driver voltage. The MOSFET vendors often specify RDS(ON)
on multiple gate to source voltages (VGS), as
well as provide typical curve of RDS(ON) versus
VGS. For 5V input, use the RDS(ON) specified at
4.5V VGS. At the time of this publication, vendors, such as Fairchild, Siliconix and International Rectifier, have started to specify RDS(ON)
at VGS less than 3V. This has provided necessary
data for designs in which these MOSFETs are
driven with 3.3V and made it possible to use
SP6120B in 3.3V only applications.
PSH (max) = 12C rssV IN (max) I OUT (max) FS
where
Crss = reverse transfer capacitance of the top
MOSFET
Thermal calculation must be conducted to ensure the MOSFET can handle the maximum
load current. The junction temperature of the
MOSFET, determined as follows, must stay
below the maximum rating.
Switching losses need to be taken into account
for high switching frequency, since they are
directly proportional to switching frequency.
The conduction losses associated with top and
bottom MOSFETs are determined by:
TJ ( max) = T A (max) +
2
PCH (max) = RDS (ON ) I OUT (max) D
Rθ JA
where
2
PCL(max) = R DS (ON ) I OUT (max) (1 − D)
TA(max) = maximum ambient temperature
PMOSFET(max) = maximum power dissipation of the MOSFET
RΘJA = junction to ambient thermal resistance.
where
PCH(max) = conduction losses of the high side
MOSFET
RΘJA of the device depends greatly on the board
layout, as well as device package. Significant
thermal improvement can be achieved in the
maximum power dissipation through the proper
design of copper mounting pads on the circuit
board. For example, in a SO-8 package, placing
PCL(max) = conduction losses of the low side
MOSFET
RDS(ON) = drain to source on resistance.
The total power losses of the top MOSFET are
the sum of switching and conduction losses. For
Date: 5/25/04
PMOSFET (max)
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
16
© Copyright 2004 Sipex Corporation
two 0.04 square inches copper pad directly
under the package, without occupying additional board space, can increase the maximum
power from approximately 1 to 1.2W. For DPAK
package, enlarging the tap mounting pad to 1 square
inches reduces the RΘJA from 96°C/W to 40°C/W.
Loop Compensation Design
The goal of loop compensation is to manipulate
loop frequency response such that its gain crosses
over 0db at a slope of –20db/dec. The SP6120B
has a transconductance error amplifier and requires the compensation network to be connected between the COMP pin and ground, as
shown in Figure 18.
Schottky Diode Selection
When paralleled with the bottom MOSFET, an
optional Schottky diode can improve efficiency
and reduce noises. Without this Schottky diode,
the body diode of the bottom MOSFET conducts the current during the non-overlap time
when both MOSFETs are turned off. Unfortunately, the body diode has high forward voltage
and reverse recovery problem. The reverse recovery of the body diode causes additional
switching noises when the diode turns off. The
Schottky diode alleviates these noises and additionally improves efficiency thanks to its low
forward voltage. The reverse voltage across the
diode is equal to input voltage, and the diode
must be able to handle the peak current equal to
the maximum load current.
The first step of compensation design is to pick
the loop crossover frequency. High crossover
frequency is desirable for fast transient response,
but often jeopardize the system stability. Since
the SP6120B is equipped with 3% window
comparator that takes over the control loop on
transient, the crossover frequency can be selected primarily to the satisfaction of system
stability. Crossover frequency should be higher
than the ESR zero but less than 1/5 of the
switching frequency. The ESR zero is contributed by the ESR associated with the output
capacitors and can be determined by:
1
fZ(ESR) =
2πCOUTRESR
The power dissipation of the Schottky diode is
determined by
Crossover frequency of 20kHz is a sound first
try if low ESR tantalum capacitors or poscaps
are used at the output. The next step is to calculate the complex conjugate poles contributed by
the LC output filter,
1
fP(LC) =
2π√ LCOUT
PDIODE = 2VFIOUTTNOLFS
where
TNOL = non-overlap time between GH and GL.
VF = forward voltage of the Schottky diode.
COMP
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter, and feedback
resistor divider. In order to crossover at the
selected frequency fco, the gain of the error
amplifier has to compensate for the attenuation
caused by the rest of the loop at this frequency.
In the RC network shown in Figure 18, the
product of R1 and the error amplifier
transconductance determines this gain. Therefore, R1 can be determined from the following
equation that takes into account the typical error
amplifier transconductance, reference voltage
and PWM ramp built into the SP6120B.
®
R1
C2
SP6120B
C1
Figure 18. The RC network connected to the COMP pin
provides a pole and a zero to control loop.
R1 =
Date: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
17
1300VOUT fCO fZ(ESR)
VIN fP(LC)2
© Copyright 2004 Sipex Corporation
In Figure 18, R1 and C1 provides a zero fZ1
which needs to be placed at or below fP(LC). If fZ1
is made equal to fP(LC) for convenience, the
value of C1 can be calculated as
C1 =
Current Sense
The SP6120B allows sensing current using the
inductor, PCB trace or current-sense resistor.
Inductor-sense utilizes the voltage drop across
the ESR of the inductor, while PCB trace and
current-sense resistor introduce additional resistance in series with the inductor. The resistance of the sense element determines the
overcurrent protection threshold as follows,
ILIM = 43mV
RSEN
RSEN = current-sense resistance which can be
implemented as ESR of the inductor, trace or
discrete resistor.
1
2πfP(LC)R1
The optional C2 generates a pole fP1 with R1 to
cut down high frequency noise for reliable operation. This pole should be placed one decade
higher than the crossover frequency to avoid
erosion of phase margin. Therefore, the value of
the C2 can be derived from
C2 =
1
20πfCOR1
Figure 19 illustrates the overall loop frequency
response and frequency of each pole and zero.
To fine-tune the compensation, it is necessary to
physically measure the frequency response using a network analyzer.
The maximum power dissipation on the currentsense element is:
2
PSEN = I OUT ( max) R SEN
For the inductor-sense scheme shown in the
application circuit, RS and CS are used to replicate the signal across the ESR of the inductor. RS
and CS can be looked at as a low pass filter
whose output represents the DC differential
voltage between the switch node and the output.
At steady state, this voltage happens to be the
output current times the ESR of the inductor. In
addition, if the following relationship is satisfied,
L =RC
S S
ESR
Gain
-20db/dec
-40db/dec
Loop
-20db/dec
f
the output of the RsCs filter represents the exact
voltage across the ESR, including the ripple.
Since the SP6120B’s hiccup overcurrent protection scheme is intended to safeguard sustained overload conditions, the DC portion of
the current signal is more of interest. Therefore,
designing the RSCS time constant higher than L/
ESR provides reliable current sense against any
premature triggering due to noise or any transient conditions. Pick Rs between 10k and 100k,
and Cs can be determined by:
1
CS = 2 L
ESR RS
-20db/dec
-20db/dec
Error Amplifier
f
fZ1 fP(LC)
fZ(ESR)
fCO
fP1
Figure 19. Frequency response of a stable system and its
error amplifier.
Here the time constant of RSCS is twice the value
of L/ESR.
In some applications, it may be desirable to
extend the current sense capability of a given
RSEN element (usually the inductor ESR) beDate: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
18
© Copyright 2004 Sipex Corporation
yond the limit set by the 43mV threshold.
Figure 20: Current Sensing
A straight forward way to do this would be to
add a resistor RS2 in parallel with CS, creating a
voltage divider with RS. This changes the relationship with RS and CS to be
1
CS = 2 L
ESR RS //RS2
Output Voltage Programming
As shown in Figure 21(A), the voltage divider
connecting to the VFB pin programs the output
voltage according to
VOUT = 1.25( 1 +
Using a voltage divider across the inductor, the
new relationship becomes:
43mV RS + RS2
ILIM =
ESR
RS2
where 1.25V is the internal reference voltage.
Select R2 in the range of 10k to 100k, and R1 can
be calculated using
To calculate RS2, the formula becomes
RS2 = RS
/(
ILIMESR
–1
43mV
R1 =
)
RS2
RS
CS
L
SWN
VOUT
ESR
R2(VOUT – 1.25)
1.25
For output voltage less than 1.25V, a simple
circuit shown in Figure 21(B) can be used in
which VREF is an external voltage reference
greater than 1.25V. For simplicity, use the same
resistor value for R1 and R2, then R3 is determined as follows,
ISN
ISP
R1
)
R2
R3 =
VOUT > 1.25V
(VREF – 1.25)R1
2.5 – VOUT
VREF
VOUT < 1.25V
R3
®
SP6120B
®
R1
VFB
R1
VFB
SP6120B
R2
R2
A
B
Figures 21(A), a voltage divider connected to the VFB pin programs the output voltageand 21(B), a simple circuit using
one external voltage reference programs the output voltages to less than 1.25V.
Date: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
19
© Copyright 2004 Sipex Corporation
Layout Guideline
5. Connect the PGND pin close to the source of
the bottom MOSFET, and the SWN pin to the
source of the top MOSFET. Minimize the
trace between GH/GL and the gates of the
MOSFETs. All of these requirements reduce
the impedance driving the MOSFETs. This is
especially important for the bottom MOSFET
that tends to turn on through its miller capacitor when the switch node swings high.
PCB layout plays a critical role in proper function of the converters and EMI control. In switch
mode power supplies, loops carrying high di/dt
give rise to EMI and ground bounces. The goal
of layout optimization is to identify these loops
and minimize them. It is also crucial on how to
connect the controller ground such that its operation is not affected by noise. The following
guideline should be followed to ensure proper
operation.
1. A ground plane is recommended for minimizing noises, copper losses and maximizing
heat dissipation.
6. Minimize the loop composed of input capacitors, top/bottom MOSFETs and Schottky diode, This loop carries high di/dt current. Also
increase the trace width to reduce copper
losses.
2. Connect the ground of feedback divider, compensation components, oscillator resistor and
soft-start capacitor to the GND pin of the IC.
Then connect this pin as close as possible to
the ground of the output capacitor.
7. Maximize the trace width of the loop connecting the inductor, output capacitors,
Schottky diode and bottom MOSFET.
3. The VCC bypass capacitor should be right
next to the Vcc and GND pin.
4. The traces connecting to feedback resistor
and current sense components should be short
and far away from the switch node, and switching components.
Date: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
20
© Copyright 2004 Sipex Corporation
PACKAGE:
PLASTIC THIN SMALL
OUTLINE
(TSSOP)
E2
E1
D
A
Ø
e
B
A1
L
DIMENSIONS
in inches (mm)
Minimum/Maximum
Date: 5/25/04
16–PIN
A
- /0.043
(- /1.10)
A1
0.002/0.006
(0.05/0.15)
B
0.007/0.012
(0.19/0.30)
D
0.193/0.201
(4.90/5.10)
E1
0.169/0.177
(4.30/4.50)
e
0.026 BSC
(0.65 BSC)
E2
0.126 BSC
(3.20 BSC)
L
0.020/0.030
(0.50/0.75)
Ø
0°/8°
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
21
© Copyright 2004 Sipex Corporation
ORDERING INFORMATION
Model
Operating Temperature Range
Package Type
SP6120BCY ............................................. 0˚C to +70˚C ........................................ 16-Pin TSSOP
SP6120BCY/TR ....................................... 0˚C to +70˚C ....................................... 16-Pin TSSOP
SP6120BEY ............................................ -40˚C to +85˚C ...................................... 16-Pin TSSOP
SP6120BEY/TR ...................................... -40˚C to +85˚C ..................................... 16-Pin TSSOP
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6120BEY/TR = standard; SP6120BEY-L/TR = lead free
/TR = Tape and Reel
Pack quantity is 1500 for TSSOP.
Corporation
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: [email protected]
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 5/25/04
SP6120B Low Voltage, AnyFETTM, Synchronous, Buck Controller
22
© Copyright 2004 Sipex Corporation