APW7088 Two-Phase Buck PWM Controller with Integrated MOSFET Drivers Features General Description • Voltage-Mode Operation with Current Sharing The APW7088, two-phase PWM control IC, provides a - Adjustable Feedback Compensation - Fast Load Transient Response precision voltage regulation system for advanced graphic microprocessors in graphics card applications. The inte- • Operate with 8V~13.2VCC Supply Voltage • Programmable 3-Bit DAC Reference gration of power MOSFET drivers into the controller IC reduces the number of external parts for a cost and space saving power management solution. -±1.5% System Accuracy Over Temperature The APW7088 uses a voltage-mode PWM architecture, operating with fixed-frequency, to provides excellent load • Support Single- and Two-Phase Operations • 5V Linear Regulator Output on 5VCC • 8~12V Gate Drivers with Internal Bootstrap Diode • Lossless Inductor DCR Current Sensing • Fixed 300kHz Operating Frequency Per Phase • Power-OK Indicator Output - Regulated 1.5V on POK • Adjustable Over-Current Protection (OCP) • Accurate Load Line (DROOP) Programming • Adjustable Soft-Start • Over-Voltage Protection (OVP) • 5VCC pin to reset the IC. Such feature of the MODE pin makes the APW7088 ideally suitable for dual power input Under-Voltage Protection (UVP) applications, such as PCIE interfaced graphic cards. • Over-Temperature Protection (OTP) This control IC‘s protection features include a set of so- • QFN4x4 24-Lead Package (QFN4x4-24) • Lead Free and Green Devices Available phisticated over temperature, over-voltage, under-voltage, and over-current protections. Over-voltage results in the transient response. The device uses the voltage across the DCRs of the inductors for current sensing. Load line voltage positioning (DROOP), channel-current balance and over-current protection are accomplished through continuous inductor DCR current sensing. The MODE pin programs single- or two- phase operation. When IC operates in two-phase mode normally, it can transfer two-phase mode to single phase mode at liberty. Nevertheless, once operates in single-phase mode, the operation mode is latched. It is required to toggle SS or converter turning the lower MOSFETs on to clamp the rising output voltage and protects the microprocessor. (RoHS Compliant) Simplified Application Circuit The over-current protection level is set through external resistors. The device also provides a power-on-reset function and a programmable soft-start to prevent wrong operation and limit the input surge current during power-on VIN1 VID0 VID1 VID2 or start-up. APW7088 VOUT The APW7088 is available in a QFN4x4-24 package. POK Applications VIN2 COMP FB • Graphics Card GPU Core Power Supply • Motherboard Chipset or DDR SDRAM Core Power Supply • On-Board High Power PWM Converter with Output Current up to 60A ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 1 www.anpec.com.tw APW7088 Ordering and Marking Information Package Code QA : QFN4x4-24 Operating Ambient Temperature Range E : -20 to 70 °C Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7088 Assembly Material Handling Code Temperature Range Package Code APW7088 QA : XXXXX - Date Code APW7088 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). LGATE2 PHASE2 VID2 VCC PHASE1 LGATE1 Pin Configuration 24 23 22 21 20 19 18 UGATE2 UGATE1 1 BOOT1 2 17 BOOT2 5VCC 3 16 POK 25 PGND AGND 4 15 VID1 13 FB 10 11 12 COMP 9 VID0 CSN1 8 CSN2 7 CSP2 14 SS CSP1 6 DROOP MODE 5 4x4 QFN-24L Top View Absolute Maximum Ratings Symbol VCC VBOOT1/2 (Note 1) Rating Unit VCC Supply Voltage (VCC to AGND) Parameter -0.3 ~ 15 V BOOT1/2 Voltage (BOOT1/2 to PHASE1/2) -0.3 ~ 15 V <200ns pulse width >200ns pulse width -5 ~ VBOOT1/2+5 -0.3 ~ VBOOT1/2+0.3 V <200ns pulse width >200ns pulse width -5 ~ VCC+5 -0.3 ~ VCC+0.3 V <200ns pulse width >200ns pulse width -10 ~ 30 -2 ~ 15 V <200ns pulse width >200ns pulse width -0.3 ~ 42 -0.3 ~ 30 V UGATE1/2 Voltage (UGATE1/2 to PHASE1/2) LGATE1/2 Voltage (LGATE1/2 to PGND) PHASE1/2 Voltage (PHASE1/2 to PGND) BOOT1/2 to AGND Voltage Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 2 www.anpec.com.tw APW7088 Absolute Maximum Ratings (Cont.) Symbol (Note 1) Parameter Rating Unit V5VCC 5VCC Supply Voltage (5VCC to AGND, V5VCC < VCC +0.3V) -0.3 ~ 7 V VMODE MODE to AGND Voltage Input Voltage (SS, FB, COMP, DROOP, CSP1/2, CSN1/2, VID0/1/2 to AGND) -0.3 ~ 7 V -0.3 ~ V5VCC +0.3 V PGND to AGND Voltage PDMAX Maximum Power Dissipation -0.3 ~ +0.3 V Limited Internally W Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Soldering Temperature, 10 Seconds 150 o -65 ~ 150 o 260 o C C C Note 1: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Thermal Characteristics Symbol Parameter Rating θJA Junction-to-Ambient Resistance (Note 2) 45 θJC Junction-to-Case Resistance (Note 3) 7 Unit °C/W Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of QFN4x4-24 is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the QFN4x4-24 package. Recommended Operating Conditions (Note 4) Symbol VCC Parameter VCC Supply Voltage Range Unit 8 ~ 13.2 V V5VCC 5VCC Supply Voltage (V5VCC < VCC +0.3V) 5 ± 5% V VOUT Converter Output Voltage 0.85 ~ 2.5 V VIN1 PWM 1 Converter Input Voltage 3.1 ~ 13.2 V VIN2 PWM 2 Converter Input Voltage 3.1 ~ 13.2 V IOUT Converter Output Current TA Ambient Temperature TJ ~ 60 A -20 ~ 70 o o C Junction Temperature -20 ~ 125 CVCC Linear Regulator Output Capacitor 0.8 ~ 15 µF C C5VCC 5VCC Linear Regulator Output Capacitor 0.8 ~ 15 µF Note 4 : Refer to the typical application circuits. Electrical Characteristics Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70°C, unless otherwise specified. Typical values are at TA=25°C. The V5VCC is supplied by the internal regulator. Symbol Parameter Test Conditions APW7088 Unit Min. Typ. Max. - 5 10 mA - 5 - mA SUPPLY CURRENT ICC VCC Nominal Supply Current ISD VCC Shutdown Supply Current Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 UGATEx and LGATEx Open, FB forced above regulation point SS=GND 3 www.anpec.com.tw APW7088 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70°C, unless otherwise specified. Typical values are at TA=25°C. The V5VCC is supplied by the internal regulator. Symbol Parameter Test Conditions APW7088 Unit Min. Typ. Max. 5VCC Rising Threshold Voltage 4.2 4.5 4.8 V 5VCC POR Hysteresis 0.4 0.58 0.76 V POWER-ON-RESET (POR) AND OPERATION PHASE SELECTION V5VCC_THR MODE Rising Threshold Voltage IMODE VMODE Rising MODE Pin Input Current 0.77 0.8 0.83 V -100 - +100 nA 5VCC LINEAR REGULATOR VREG_5VCC Output Voltage IO = 0A, VCC =8V 4.75 5 5.25 V Line Regulation IO = 0A, VCC = 8V ~ 13.2V -20 - 20 mV Load Regulation IO = 3mA, VCC > 8V -200 - 200 mV Current-Limit 5VCC = GND 20 30 - mA TA=25oC -1 - +1 -1.5 - +1.5 FB Pin Input Current -100 - +100 nA REFERENCE VOLTAGE Accuracy IFB VPOK Over temperature % VID0/1/2 Logic High Threshold 1.2 - - V VID0/1/2 Logic Low Threshold - - 0.5 V VID0/1/2 Pull-high Current - 1 - µA POK Output Voltage - 1.5 - V o IO = 0~3mA, TA=25 C -2 - +2 IO = 0~3mA, Over temperature -3 - +3 POK Current-Limit POK = GND 4 8 15 mA POK Pull-Low Resistance IPOK = 5mA - 70 100 Ω POK Accuracy % ERROR AMPLIFIER DC Gain RL = 10kΩ to the ground - 85 - dB Gain-Bandwidth Product CL = 100pF, RL = 10kΩ to the ground - 20 - MHz Slew Rate CL = 100pF, IO = ±400µA - 8 - V/µs Upper Clamp Voltage IO = 1mA 2.7 3.0 - V Lower Clamp Voltage IO = -1mA - - 0.1 V COMP Pull-Low Resistance In fault or shutdown condition - 2 - kΩ 255 300 345 kHz - 1.5 - V 85 88 - % OSCILLATOR FOSC ∆VOSC1/2 Oscillator Frequency Oscillator Sawtooth Amplitude Maximum Duty Cycle Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 4 www.anpec.com.tw APW7088 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70°C, unless otherwise specified. Typical values are at TA=25°C. The V5VCC is supplied by the internal regulator. Symbol Parameter Test Conditions APW7088 Min. Typ. Max. Unit MOSFET GATE DRIVERS TD UGATE1/2 Source Current VBOOT = 12V, VUGATE-VPHASE = 2V - 2.6 - A UGATE1/2 Sink Current VBOOT = 12V, VUGATE-VPHASE = 2V - 1 - A LGATE1/2 Source Current VCC = 12V, VLGATE = 2V - 2.6 - A LGATE1/2 Sink Current VCC =12V, VLGATE = 2V - 1.4 - A UGATE1/2 Source Resistance VBOOT = 12V, 100mA Source Current - 2.5 3.75 Ω UGATE1/2 Sink Resistance VBOOT = 12V, 100mA Sink Current - 2 3 Ω LGATE1/2 Source Resistance VCC = 12V, 100mA Source Current - 2 3 Ω LGATE1/2 Sink Resistance VCC = 12V, 100mA Sink Current - 1.4 2.1 Ω - 30 - ns -100 - +100 nA Dead-Time CURRENT SENSE AND DROOP FUNCTION ICSP CSP1/2 Pin Input Current ICSN CSN1/2 Maximum Output Current R CSN1/2 = 2kΩ, Sourcing current 80 - - Sinking current 15 - - - 3 - Current Sense Amplifier Bandwidth µA MHz DROOP Output Current Accuracy RDROOP = 2kΩ, VDROOP =0.005V - 50 - µA DROOP Accuracy ∆VFB = VDROOP/20, VDROOP=1V -5 - +5 mV -10 - +10 % Current Difference Between Channel1/2 and Average Current SOFT-START AND ENABLE ISS 8 10 12 µA Soft-Start Complete Threshold - 3.2 - V SS Pull-low Resistance - 10 18 kΩ Soft-Start Current Source Flowing out of SS pin POWER OK AND PROTECTIONS VUV Over-Current Trip Level ICS1 + ICS2 110 120 140 µA FB Under-Voltage Threshold ~ 2µs noise filter, VFB falling, Percentage of VR at Error Amplifier 40 50 60 % - 87.5 - % 115 125 135 % - 60 80 mV - 150 - o - o VPOK_L POK Lower Threshold VOV, VPOK_H FB Over-Voltage Threshold and POK Upper Threshold ~ 2µs noise filter, VFB rising Percentage of VR at Error Amplifier FB Over-Voltage Hysteresis TOTR Over-Temperature Trip Level TJ rising Over-Temperature Hysteresis Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 - 5 50 C C www.anpec.com.tw APW7088 Typical Operating Characteristics 5VCC Line Regulation 5VCC Load Regulation 6 VCC=12V, VIN=12V 5VCC Voltage,V5VCC (V) 5VCC Voltage,V5VCC (V) 6 5 4 3 2 5 4 3 2 1 1 0 0 0 2 4 6 8 10 12 0 14 5 10 Output Voltage Load Regulation 25 30 35 40 Output Voltage Line Regulation VID0, VID1 and VID2 are high VCC=12V, VIN=12V VID0, VID1 and VID2 are high 0.855 0.855 Feedback Voltage,VFB (V) Feedback Voltage,VFB (V) 20 0.857 0.857 0.853 0.851 0.849 0.847 0.845 0.853 0.851 0.849 0.847 0.845 0.843 0.843 0.841 0.841 0 10 20 30 40 5 50 6 7 8 9 10 11 12 13 VIN Voltage,VIN (V) Output Current,IOUT (A) Reference Voltage Accuracy Over Switching Frequency Over Temperature Temperature 330 0.863 VID0, VID1 and VID2 are high 0.860 Switching Frequency, FSW (kHz) Reference Voltage,VDAC (V) 15 5VCC Load Current ,I5VCC (mA) VCC Voltage,VCC (V) 0.857 0.854 0.851 0.849 0.846 0.843 0.840 -20 0 20 40 60 80 100 120 o 300 290 280 -20 0 20 40 60 80 100 120 o Junction Temperature, TJ ( C) Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 310 270 -40 0.837 -40 320 Junction Temperature, TJ ( C) 6 www.anpec.com.tw APW7088 Operating Waveforms Power On Power Off IOUT=10A IOUT=10A V5VCC V5VCC 1 1 VCOMP VCOMP 2 2 VSS VSS 3 3 VOUT 4 VOUT 4 CH1: V5VCC (5V/div) CH2: VCOMP (1V/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div CH1: V5VCC (5V/div) CH2: VCOMP (1V/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div Enable by SS Pin Shutdown by SS Pin IOUT=10A IOUT=10A VSS VSS 1 1 VCOMP VCOMP 2 2 VOUT 3 VOUT 3 CH1: VSS (2V/div) CH2: VCOMP (1V/div) CH3: VOUT (1V/div) Time: 10ms/div Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 CH1: VSS (2V/div) CH2: VCOMP (1V/div) CH3: VOUT (1V/div) Time: 10ms/div 7 www.anpec.com.tw APW7088 Operating Waveforms (Cont.) Power On Without VIN2 Voltage Under-Voltage Protection (UVP) VOUT VFB 1 1 VPHASE1 VPHASE1 2 2 VPHASE2 VPHASE2 3 3 4 Vss Vss 4 CH1: VOUT (1V/div) CH2: VPHASE1 (10V/div) CH3: VPHASE2 (2V/div) CH4: VSS (2V/div) Time: 5ms/div CH1: VFB (500mV/div) CH2: VPHASE1 (10V/div) CH3: VPHASE2 (10V/div) CH4: VSS (2V/div) Time: 500µs/div Load Transient , 40A==>0A Load Transient , 0A==>40A 1 2 VPHASE1 VPHASE1 1 IPHASE2 IPHASE2 2 VOUT VOUT 3 3 IOUT IOUT 4 RSEN=3kΩ L=0.56µH DCR=4mΩ RSEN=3kΩ L=0.56µH DCR=4mΩ 4 CH1: VPHASE1 (20V/div) CH2: IPHASE2 (20A/div) CH3: VOUT (AC, 200mV/div) CH4: IOUT (10A/div) Time: 20µs/div Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 CH1: VPHASE1 (20V/div) CH2: IPHASE2(20A/div) CH3: VOUT (AC, 200mV/div) CH4: IOUT (10A/div) Time: 20µs/div 8 www.anpec.com.tw APW7088 Operating Waveforms (Cont.) Short-Circuit Test After Power On OCP at Slow Slew IOUT RSEN=1.5kΩ L=0.56µH DCR=4mΩ RSEN=1.5kΩ L=0.56µH DCR=4mΩ IL1 1 IL1 1 IL2 IL2 2 2 VSS 3 VOUT 4 VSS 3 VOUT 4 CH1: IL1 (10A/div) CH2: IL2 (10A/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div CH1: IL1 (10A/div) CH2: IL2 (10A/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div OVP After Power On Short-Circuit Test Before Power On RSEN=1.5kΩ L=0.56µH DCR=4mΩ Pull-Up VFB > V OV VSS 1 IL1 VFB 1 VLG1 2 IL2 3 VLG2 2 VSS 3 4 VOUT 4 CH1: VFB (500mV/div) CH2: VSS (2V/div) CH3: VLG1 (10V/div) CH4: VLG2 (10V/div) Time: 100µs/div CH1: IL1 (10A/div) CH2: IL2 (10A/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 9 www.anpec.com.tw APW7088 Pin Description PIN NAME 1 UGATE1 2 BOOT1 3 5VCC 4 AGND 5 MODE 6 CSP1 7 CSN1 8 CSN2 9 CSP2 10 DROOP 11 VID0 12 COMP 13 FB 14 SS 15 VID1 16 POK 17 BOOT2 18 UGATE2 19 PHASE2 20 LGATE2 FUNCTION High-side Gate Driver Output for channel 1. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. Bootstrap Supply for the floating high-side gate driver of channel 1. Connect the Bootstrap capacitor between the BOOT1 pin and the PHASE1 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT ranged from 0.1µF to 1µF. Ensure that CBOOT is placed near the IC. Internal Regulator Output. This is the output pin of the linear regulator, which is converting power from VCC and provides output current up to 20 mA minimums for internal bias and external usage. Signal Ground for the IC. All voltage levels are measured with respect to this pin. Tie this pin to ground island/plane through the lowest impedance connection available. Operation Phase Selection Input. Pulling this pin lower than 0.64V sets two-phase operation with both channels enabled. Pulling this pin higher than 0.8V sets single-phase operation with the channel 2 disabled. Once operating in single-phase mode, the operation mode is latched. It is required to toggle SS or 5VCC pin to reset the IC. Positive Input of current sensing Amplifier for channel 1. This pin combined with CSN1 senses the inductor current through an RC network. Negative Input of current sensing amplifier for channel 1. This pin combined with CSP1 senses the inductor current through an RC network. Negative Input of current sensing amplifier for channel 2. This pin combined with CSP2 senses the inductor current through an RC network. Positive Input of current sensing Amplifier for Channel 2. This pin combined with CSN2 senses the inductor current through an RC network. Load Line (droop) Setting. Connect a resistor between this pin and AGND to set the droop. A sourcing current, proportional to output current is present on the DROOP pin. The droop scale factor is set by the resistors (connected with CSP1, CSP2, and DROOP), resistance of the output inductors and the internal voltage divider with the ratio of 5%. This is one of the inputs for the internal DAC that provides the reference voltage for output regulation. This pin responds to logic threshold. The APW7088 decodes the VID inputs to establish the output voltage; see VID Tables for correspondence between DAC codes and output voltage settings. This pin is internally pulled high at floating status. Error Amplifier Output. Connect the compensation network between COMP, FB, and VOUT for Type 2 or Type 3 feedback compensation. Feedback Voltage. This pin is the inverting input to the error comparator. A resistor divider from the output to AGND is used to set the regulation voltage. Soft-start Current Output. Connect a capacitor from this pin to AGND to set the soft-start interval. Pulling the voltage on this pin below 0.5V causes COMP to pull low and then shuts off the output. One of DAC Inputs, same as VID0 and VID2. Power OK and 1.5V Reference Output. This pin is a reference output used to indicate the status of the voltages on SS pin and FB pin. POK provides 1.5V reference if VFB> 87.5% of reference (VR). Bootstrap Supply for the floating high-side gate driver of channel 2. Connect the Bootstrap capacitor between the BOOT2 pin and the PHASE2 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT range from 0.1µF to 1µF. Ensure that CBOOT is placed near the IC. High-side Gate Driver Output for Channel 2. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. Switch Node for Channel 2. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATE2 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. An Schottky diode between this pin and ground is recommended to reduce negative transient voltage that is common in a power supply system. Low-side Gate Driver Output for Channel 2. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off. Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 10 www.anpec.com.tw APW7088 Pin Description (Cont.) PIN 21 NAME VID2 22 VCC 23 LGATE1 24 PHASE1 25 PGND FUNCTION One of DAC Inputs, same as VID0 and VID1. Supply Voltage Input. This pin provides bias supply for the low-side gate drivers and the bootstrap circuit for high-side drivers. This pin can receive a well-decoupled 8V~13.2V supply voltage. Ensure that this pin is bypassed by a ceramic capacitor next to the pin. Low-side Gate Driver Output for Channel 1. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off. Switch Node for Channel 1. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATT1 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. An Schottky diode between this pin and ground is recommended to reduce negative transient voltage which is common in a power supply system. Power Ground for the low-side gate drivers. Connect this pin to the source of low-side MOSFETs. This pin is used as sink for LGATE1 and LGATE2 drivers. Block Diagram POK VCC 1.5V Reference VCC 5VCC Linear Regulator 5VCC 87.5% 125% Power-onReset OV UV V5VCC 50% Over-Temperature Protection FB PGND VDROOP VID0 VID1 VID2 3-Bit DAC VDAC + SSEND Droop Control DROOP Control Logic Operation Phase Selection - 3.6V VR ISS 10µA Error Amplifier SS Soft-Start 300kHz Oscillator and Sawtooth COMP VOSC1 AGND VOSC2 VCC VCC BOOT2 BOOT1 UGATE2 PHASE2 MODE UGATE1 PWM Signal Controller VCC VCC LGATE2 PHASE1 LGATE1 120µA CSN2 CSP2 Current Sense ICS2 Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 Current Balance OC ICS1+ICS2 ICS1 ICS1+ICS2 11 Current Sense CSN1 CSP1 www.anpec.com.tw APW7088 Typical Application Circuit VIN +12V 5 BOOT1 PHASE1 Q1 1 24 L1 0.56µH C5 0.1µF VCC VOUT 1.2V DCR=4mΩ C13 1µF 3 C4 10µF MODE UGATE1 22 2 LGATE1 5VCC C14 1µF PGND C6 1200µFx3 Q2 23 25 C7 47µFx2 IOCP=45A Q1 : APM4350KPx1 Q2 : APM4354KPx2 14 C15 0.1µF 11 15 21 10 R11 2kΩ 16 SS APW7088 BOOT2 17 VID0 VID1 UGATE2 VID2 DROOP PHASE2 C8 10µF C9 330µFx3 Q3 18 19 L2 0.56µH C10 0.1µF DCR=4mΩ POK LGATE2 Q4 20 C3 2.2nF R4 2kΩ CSP1 C2 22nF 12 CSN1 COMP CSP2 13 R2 3.6kΩ R1 1.5kΩ R3 51Ω FB CSN2 R5 1.5kΩ 6 PHASE1 7 9 PHASE2 8 R7 1.5kΩ AGND 4 C1 10nF Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 R8 1.5kΩ 12 C12 0.1µF R6 1.5kΩ C11 0.1µF www.anpec.com.tw APW7088 Function Description 5VCC Linear Regulator When soft-start is initiated, the internal 10µA current 5VCC is the output terminal of the internal 5V linear regulator which regulates a 5V voltage on 5VCC by source starts to charge the capacitor. When the soft-start voltage across the soft-start capacitor reaches the en- controlling an internal bypass transistor between VCC and 5VCC. The linear regulator powers the internal abled threshold about 0.8V (VSS_VT), the internal reference starts to rise and follows the soft-start voltage with con- control circuitry and is stable with a low-ESR ceramic output capacitor. Bypass 5VCC to GND with a ceramic verter operating at fixed 300kHz PWM switchin g frequency. When output voltage rises up to 87.5% of capacitor of at least 1µF. Place the capacitor physically close to the IC to provide good noise decoupling. The the regulation voltage, the power-ok is enabled. The softstart time (from the moment of enabling the IC to the linear regulator can also provide output current, up to 20mA, for external loads. The linear regulator with current- moment when V POK goes high) can be expressed as below : limit protection can protect itself during over-load or shortcircuit conditions on 5VCC pin. The 5VCC linear regulator stop regulating in Over-Tem- TSS = CSS × ( VSS _ VT + VDAC × 0.875) ISS where CSS= external soft-start capacitor perature Protection. When the junction temperature is cooled by 50oC, the 5VCC linear regulator starts to regulate the output voltage again. VSS_VT= internal soft start threshold voltage, is about 0.8V 5VCC Power-On-Reset (POR) VDAC= Internal digital VID programmable reference voltage Figure 1 shows the power sequence. The APW7088 ISS= soft-start current=10µA keeps monitoring the voltage on 5VCC pin to prevent During soft-start stage, the under-voltage protection is wrong logic operations which may occur when 5VCC voltage is not high enough for the internal control cir- inhibited. However, the over-voltage and over-current protection functions are enabled. If the output capacitor has cuitry to operate. The 5VCC POR has a rising threshold of 4.6V (typical) with 0.58V of hysteresis. After the residue voltage before startup, both lower and upper MOSFETs are in off-state until the internal soft-start volt- 5VCC voltage exceeds its rising Power-On-Reset (POR) voltage threshold, the IC starts a start-up pro- age equals the FB pin voltage. This will ensure the output voltage starts from its existing voltage level. cess and then ramps up the output voltage to the setting of output voltage. The 5VCC POR signal resets the Operation Phase Selection fault latch, set by the undervoltage or over-current event, when the signal is at low level. Voltage(V) The MODE pin programs single- or two- phase operation. It has a typical value for rising threshold of 0.8V, VMODE_THR, with 0.16V of hysteresis (0.64V), VMODE_THF. When the MODE pin voltage is higher than the VMODE_THR, the device operates in single-phase; when the MODE pin voltage is lower VCC than VMODE_THF and VIN2 supply voltage is above approximate 4V, the device operates in two-phase operation. VSS 5VCC POR This function makes the APW7088 ideally suitable for dual power input applications like PCIE interfaced graphic V5VCC VPOK VFB cards. The figure 2 shows the power sources of the two 1.5V channels. The input power of PWM1 converter is supplied by PCIE bus power and the input power of PWM2 VSS_VT converter is supplied by an external power. If the input power connector of PWM2 converter is not plugged into Time Figure 1. Power Sequence Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 13 www.anpec.com.tw APW7088 Function Description (Cont.) Operation Phase Selection (Cont.) rent protection responds, the output voltage will fall out of the required regulation range. The under-voltage the socket before start-up, the internal VIN2 sensing circuit can sense the absence of VIN2 and set the IC to operate in continually monitors the VFB voltage after soft-start is completed. If a load step is strong enough to pull the single-phase mode with PWM2 disabled. When the IC operates in two-phase mode, it can switch the operating output voltage lower than the under-voltage threshold, the IC shuts down converter’s output. Cycling the 5VCC mode from two-phase to single-phase operation. Once operating in single-phase mode, the operation mode is POR resets the fault latch and starts a start-up process. The under-voltage threshold is 50% of the nominal out- latched. It is required to toggle SS or 5VCC pin to reset the IC. PCIE +12V put voltage. The under-voltage comparator has a built-in 2µs noise filter to prevent the chips from wrong UVP VCC shutdown being caused by noise. Over-Current Protection (OCP) PWM 1 converter External Power MODE VIN2 PWM 2 converter Figure 3 shows the circuit of sensing inductor current. Connecting a series resistor (R S) and a capacitor (C S) Operation Phase Selection network in parallel with the inductor and measuring the voltage (VC) across the capacitor can sense the in- PHASE2 ductor current. 4V VIN2 sensing circuit VL L DCR PHASE Figure 2. VIN2 Sensing Circuit IL Over-Voltage Protection (OVP) Rs The over-voltage protection function monitors the output voltage through FB pin. When the FB voltage increases Cs VC CSP CSN over 125% of the reference voltage (VR) due to the highside MOSFET failure or other reasons, the over-voltage R2 protection comparator designed with a 2µs noise filter will force the low-side MOSFET gate drivers high. This Figure 3. Illustration of Inductor Current Sensing Circuit action actively pulls down the output voltage and eventually attempts to trigger the over-current shutdown of an The equations of the sensing network are, VL (s)=IL (s) × (SL+DCR) ATX power supply. As soon as the output voltage is within regulation, the OVP comparator is disengaged. The chip VC(S) = VL(S) × will restore its normal operation. When the OVP occurs, the POK will drop to low as well. Take This OVP scheme only clamps the voltage overshoot L DCR for example, if the above is true, the voltage across the RSCS = and does not invert the output voltage when otherwise activated with a continuously high output from low-side capacitor CS is equal to voltage drop across the inductor MOSFETs driver, which is a common problem for OVP schemes with a latch. DCR, and the voltage VC is proportional to the current IL. The sensing current through the resistor R2 can be ex- Under-Voltage Protection (UVP) pressed as below : In the operational process, when a short-circuit occurs, ICS = the output voltage will drop quickly. Before the over-curCopyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 1 IL(S) × (SL + DCR) = 1 + SRSCS 1 + SRSCS 14 IL × DCR R2 www.anpec.com.tw APW7088 Function Description (Cont.) Over-Current Protection (OCP) (Cont.) Droop Control where ICS is the sensed current VDROOP IL is the inductor current DCR is the inductor resistance RDROOP VR R2 is the sense resistor VREFIN/EN or 0.6V The APW7088 is a two-phase PWM controller; therefore, the IC has two sensed current parts, ICS1 and ICS2. When ICS1 plus ICS2 is greater than 120µA, the over current occurs. Figure 4. Illustration of Droop Setting Function In over-current protection, the IC shuts off the converter and then initials a new soft-start process. After 3 over- Over-Temperature Protection (OTP) When the junction temperature increases above the ris- current events are counted, the device turns off both highside and low-side MOSFETs and the converter’s output ing threshold temperature TOTR, the IC will enter the overtemperature protection state that suspends the PWM, is latched to be floating. which forces the LGATE and UGATE gate drivers to output low voltages and turns off the 5VCC linear regulator Current Sharing output. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again The APW7088 uses inductor’s DCRs and external networks to sense the both currents flowing through the inductors of the PWM1 and PWM2 channels. The current after the junction temperature cools by 50oC. The OTP is designed with a 50oC hysteresis to lower the average TJ sharing circuit, with closed-loop control, uses the sensed currents to adjust the two-phase inductor currents. For during continuous thermal overload conditions, which increases lifetime of the APW7088. example, if the sensed current of PWM1 is bigger than PWM2, the duty of PWM1 will decrease and the duty of Table 1. DAC Output Voltage vs. VID Inputs PWM2 will increase. Then, the device will reduce IL1 current and increase IL2 current for current sharing. VID2 VID1 VID0 0 0 0 DAC Output Voltage, VDAC (V) 1.20 DROOP 0 0 1 1.15 In some high current applications, a requirement on 0 1 0 1.10 precisely controlled output impedance is imposed. This dependence of output voltage on load current is often 0 1 1 1.05 1 0 0 1.00 termed droop regulation. As shown in figure 4, the droop control block gener- 1 0 1 0.95 1 1 0 0.90 ates a voltage through external resistor R DROOP , then set the droop voltage. The droop voltage, VDROOP , is 1 1 1 0.85 proportional to the total current in two channels. As the following equation shows, VDROOP = 0.05 × [(ICS1 + ICS 2 ) × RDROOP ] The VDROOP voltage is used the regulator to adjust the output voltage so that it’s equal to the reference voltage minus the droop voltage. Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 15 www.anpec.com.tw APW7088 Application Information Output Voltage Setting The output voltage is adjustable from 0.85V to 2.5V with a resistor-divider connected with FB, AGND, and converter’s FLC output. Using 1% or better resistors for the resistor-divider is recommended. The output voltage is determined -40dB/dec GAIN (dB) by : RTOP VOUT = VDAC × 1 + RGND FESR Where VDAC is the internal digital VID programmable reference voltage, the RTOP is the resistor connected from converter’s output to FB and RGND is the resistor con- -20dB/dec nected from FB to AGND. Suggested RGND is in the range from 1K to 20KΩ. To prevent stray pickup, locate resistors RTOP and RGND close to the APW7088. Frequency(Hz) Figure 6. Frequency Resopnse of the LC filters PWM Compensation The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain The PWM modulator is shown in figure 7. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given slope and 180 degrees phase shift in the control loop. A compensation network among COMP, FB, and V OUT by : GAINPWM = should be added. The compensation network is shown in Figure 8. The output LC filters consists of the VIN ∆VOSC output inductors and output capacitors. For two-phase convertor, when assuming VIN1=VIN2=VIN, L1=L2=L, the Driver OSC transfer function of the LC filter is given by : 1 + s × ESR × COUT 1 s × L × COUT + s × ESR × COUT + 1 2 The poles and zero of this transfer functions are : 1 FLC = 1 2× π× L × COUT 2 GAINLC = FESR = PHASE Output of Error Amplifier Driver Figure 7. The PWM Modulator The compensation network is shown in figure 8. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The FLC is the double-pole frequency of the two-phase LC filters, and FESR is the frequency of the zero introduced by The transfer function of error amplifier is given by: the ESR of the output capacitors. L1=L GAINAMP VOUT L2=L COUT VPHASE2 1 1 // R2 + VCOMP sC1 sC2 = = 1 VOUT R1// R3 + sC3 1 1 s + ×s + R1 + R3) × C3 R2 × C2 ( R1 + R3 = × C1 + C2 1 R1× R3 × C1 s s + × s + R2 × C1 × C2 R3 × C3 ESR Figure 5. The Output LC Filter Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 PWM Comparator ∆VOSC 2 1 2 × π × ESR × COUT VPHASE1 VIN 16 www.anpec.com.tw APW7088 Application Information (Cont.) PWM Compensation (Cont.) 4. Set the pole at the ESR zero frequency FESR: The pole and zero frequencies of the transfer function are: 1 FZ1 = 2 × π × R2 × C2 FP1 = FESR Calculate the C1 by the following equation: C1 = 1 FZ2 = 2 × π × (R1 + R3 ) × C3 1 FP1 = C1× C2 2 × π × R2 × C1 + C2 1 FP2 = 2 × π × R3 × C3 5. Set the second pole FP2 at the half of the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the C1 R3 C3 C2 2 × π × R2 × C2 × FESR − 1 R2 error amplifier. FP2 = 0.5 X FSW C2 FZ2 = FLC VOUT FB R1 Combine the two equations will get the following VCOMP component calculations: R1 FSW −1 2 × FLC 1 C3 = π × R3 × FSW VDAC R3 = Figure 8. Compensation Network The closed loop gain of the converter can be written as: GAINLC X GAINPWM X GAINAMP Figure 9. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to FZ1 FZ2 FP1 FP2 design the compensation network. Using the below guidelines should give a compensation similar to the GAIN (dB) curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. 1. Choose a value for R1, usually between 1K and 5K. Compensation Gain 20log (R2/R1) 20log (VIN/ΔVOSC) 2. Select the desired zero crossover frequency FO= (1/5 ~ 1/10) X FSW Use the following equation to calculate R2: FLC FESR ∆VOSC FO R2 = × × R1 VIN FLC PWM & Filter Gain Frequency(Hz) 3. Place the first zero FZ1 before the output LC filter double pole frequency FLC. FZ1 = 0.75 X FLC Figure 9. Converter Gain and Frequency Output Inductor Selection Calculate the C2 by the following equation: The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output volt- 1 C2 = 2 × π × R2 × FLC × 0.75 Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 Converter Gain age is fixed, it can be written as: 17 www.anpec.com.tw APW7088 Application Information (Cont.) Output Inductor Selection (Cont.) D= of the inductor’s current. The ripple voltage of output capacitors can be represented by: VOUT VIN For two-phase converter, the inductor value (L) determines ∆VESR the sum of the two inductor ripple currents, ∆IP-P, and af- These two components constitute a large portion of the total output voltage ripple. In some applications, multiple fects the load transient reponse. Higher inductor value reduces the output capacitors’ripple current and induces capacitors have to be parallelled to achieve the desired ESR value. If the output of the converter has to support lower output ripple voltage. The ripple current can be approxminated by : another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR VIN - 2VOUT VOUT ∆IP - P = × FSW × L VIN Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (FSW ) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage. Output Capacitor Selection and suppress the voltage ripple to a tolerable level. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors must also be considered. To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing the voltage excursion during load step change. For getting same load transient response, the output capacitance of two-phase converter only needs around half of output capacitance of single-phase converter. Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current specified on the capacitors in order to prevent the capacitor from over-heating. Input Capacitor Selection Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed each time high-side MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of high-side MOSFET and the source of low-side MOSFET. Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and cur- selecting output capacitors. Higher capacitor value and lower ESR reduce the output ripple and the load tran- rent ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor volt- sient drop. Therefore, selecting high performance low ESR capacitors is recommended for switching regulator age rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times applications. In addition to high frequency noise related to MOSFET turn-on and turn-off, the output voltage ripple is a conservative guideline. For two-phase converter, the RMS current of the bulk input capacitor is roughly calcu- includes the capacitance voltage drop ∆VCOUT and ESR voltage drop ∆VESR caused by the AC peak-to-peak sum Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 ∆ IP − P 8 × COUT × FSW = ∆IP − P × RESR ∆VCOUT = lated as the following equation: 18 www.anpec.com.tw APW7088 Application Information (Cont.) Input Capacitor Selection (Cont.) IRMS = where I IOUT × 2D ⋅ (1 - 2D) 2 is the load current OUT TC is the temperature dependency of RDS(ON) FSW is the switching frequency For a through hole design, several electrolytic capacitors tSW is the switching interval D is the duty cycle may be needed. For surface mount design, solid tantalum capacitors can be used, but caution must be exer- Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transi- cised with regard to the capacitor surge current rating. MOSFET Selection tion loss. The switching interval, t SW , is the function of the reverse transfer capacitance CRSS. The (1+TC) term is The APW7088 requires two N-Channel power MOSFETs on each phase. These should be selected based upon a factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs. Temperature” curve RDS(ON), gate supply requirements, and thermal management requirements. of the power MOSFET. In high-current applications, the MOSFET power dissipation, package selection, and heatsink are the domi- Layout Consideration In any high switching frequency converter, a correct layout nant design factors. The power dissipation includes two loss components, conduction loss and switching loss. is important to ensure proper operation of the regulator. With power devices switching at higher frequency, the The conduction losses are the largest component of power dissipation for both the high-side and the low- resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit side MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equa- elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the tions below). Only the high-side MOSFET has switching losses since the low-side MOSFETs body diode or an MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous rec- by the low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike tifier turns on. These equations assume linear voltagecurrent transitions and do not adequately model power during the switching interval. In general, using short, wide printed circuit traces should minimize interconnecting im- loss due the reverse-recovery of the low-side MOSFET body diode. The gate-charge losses are dissipated by pedances and the magnitude of voltage spike. Besides, signal and power grounds are to be kept separating and the APW7088 and don’t heat the MOSFETs. However, large gate-charge increases the switching interval, tSW finally combined using ground plane construction or single point grounding. The best tie-point between the which increases the high-side MOSFET switching losses. Ensure that all MOSFETs are within their maxi- signal ground and the power ground is at the negative side of the output capacitor on each channel, where there mum junction temperature at high ambient temperature by calculating the temperature rise according to package is less noise. Noisy traces beneath the IC are not recommended. Figure 10. illustrates the layout, with bold thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, lines indicating high current paths; these traces must be short and wide. Components along the bold lines should package type, ambient temperature, and air flow. For the high-side and low-side MOSFETs, the losses are be placed lose together. Below is a checklist for your layout : approximately given by the following equations: 2 Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW 2 Plow-side = IOUT (1+ TC)(RDS(ON))(1-D) Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 19 www.anpec.com.tw APW7088 Application Information (Cont.) Layout Consideration (Cont.) • Keep the switching nodes (UGATEx, LGATEx, BOOTx, and PHASEx) away from sensitive small signal nodes APW7088 VIN1=VIN since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any layer. BOOT1 • The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and UGATE1 discharging current. The traces from the gate drivers to the MOSFETs (UGATEx, LGATEx) should be short PHASE1 and wide. LGATE1 L1 • Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane be- RS1 CS1 CSP1 VOUT CSN1 tween the two pads reduces the voltage bounce of the node. In addition, the large layout plane between CSN2 CSP2 the drain of the MOSFETs (VIN and PHASEx nodes) can get better heat sinking. • For experiment result of accurate current sensing, the LGATE2 current sensing components are suggested to place CS2 L O A D RS2 PHASE2 close to the inductor part. To avoid the noise interference, the current sensing trace should be away L2 UGATE2 from the noisy switching nodes. • Decoupling capacitors, the resistor-divider, and boot BOOT2 capacitor should be close to their pins. (For example, place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible). • The input bulk capacitors should be close to the drain VIN2=VIN of the high-side MOSFET, and the output bulk capacitors should be close to the loads. The input capaci- Figure 10. Layout Guidelines tor’s ground should be close to the grounds of the output capacitors and low-side MOSFET. • Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces can’t be close to the switching signal traces (UGATEx, LGATEx, BOOTx, and PHASEx). Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 20 www.anpec.com.tw APW7088 Package Information QFN4x4-24 D b E A Pin 1 D2 A1 A3 L K E2 Pin 1 Corner e QFN4x4-24 S Y M B O L A MIN. MAX. MIN. MAX. 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 0.002 INCHES MILLIMETERS A3 0.20 REF 0.008 REF b 0.18 0.30 0.008 0.012 D 3.90 4.10 0.154 0.161 D2 2.50 2.80 0.098 0.110 E 3.90 4.10 0.154 0.161 E2 2.50 2.80 0.098 0.110 0.45 0.014 e 0.50 BSC L 0.35 K 0.20 0.020 BSC 0.018 0.008 Note : 1. Followed from JEDEC MO-220 WGGD-6. Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 21 www.anpec.com.tw APW7088 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application QFN4x4-24 A H T1 330.0±2.00 50 MIN. P0 P1 P2 4.0±0.10 8.0±0.10 2.0±0.05 C d D 1.5 MIN. 20.2 MIN. D0 D1 T A0 B0 K0 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.30± 0.20 12.4+2.00 13.0+0.50 -0.00 -0.20 W E1 12.0±0.30 1.75±0.10 F 5.5±0.05 (mm) Devices Per Unit Package Type QFN4x4-24 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 Quantity 3000 22 www.anpec.com.tw APW7088 Taping Direction Information QFN4x4-24 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 23 www.anpec.com.tw APW7088 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak (Tp)* package body Temperature Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 3 Package Thickness <2.5 mm ≥2.5 mm Volume mm ≥350 220 °C 220 °C Volume mm <350 235 °C 220 °C Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT ESD Latch-Up Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883E-3015.7 JESD 78 24 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV, VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7088 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 25 www.anpec.com.tw