SIPEX SP6828TR

®
SP6828/6829
+3V Low Power Voltage Inverters
■ 99.9% Voltage Conversion Efficiency
■ +1.15V to +4.2V Input Voltage Range
■ +1.15 VIN Guaranteed Start-up
■ Inverts Input Supply Voltage
■ 20µA Quiescent Current for the SP6828
■ 40µA Quiescent Current for the SP6829
■ 25mA Output Current
■ 12kHz Operating Frequency for the SP6828
■ 35kHz Operating Frequency for the SP6829
■ Ideal for +3.6V Lithium Ion Battery
Applications
■ Reverse +3.6V Lithium Ion Battery
Protection
■ 5-pin SOT23 Package
DESCRIPTION
The SP6828/6829 devices are CMOS Charge Pump Voltage Inverters that can be
implemented in designs requiring a negative voltage from a +3V battery source. The SP6828/
6829 devices are ideal for both battery-powered and board level voltage conversion
applications with a typical operating current of 20µA for the SP6828 and 40µA for the SP6829.
Both devices can output 25mA with a voltage drop of 500mV. These devices combine a low
quiescent current with high efficiency (>95% over most of its load-current range), which is ideal
for designs using +3.3V or +3.6V lithium ion batteries. Applications include cell phones, PDAs,
medical instruments and other portable equipment. The SP6828/6829 devices are available in
a space-saving 5-pin SOT23 Package.
5 C1+
VOUT 1
VIN 2
C1- 3
SP6828DS/11
SP6828
SP6829
4 GND
SP6828/6829 +3V Low Power Voltage Inverter
1
© Copyright 2000 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect reliability.
VIN...................................................................................................+4.5V
VOUT.................................................................................................-4.5V
V OUT Short Circuit to GND.................................................Indefinite
IOUT...................................................................................................50mA
Storage Temperature.....................................................-65˚C to +150˚C
Power Dissipation (TAMB=+70°C).................................................571mW
Lead Temperature (Soldering)....................................................300oC
ESD Rating...............................................2kV Human Body Model
SPECIFICATIONS FOR THE SP6828/6829
VIN = +3.3V, C1=C2=10µF for the SP6828, C1=C2=3.3µF for the SP6829, and TAMB= -40°C to +85°C unless otherwise noted. Typical values are taken
specifically at TAMB=+25°C. Test Circuit Figure 19 unless otherwise noted.
PARAMETER
MIN.
TYP.
1.15
1.4
0.86
Supply Voltage
Supply Current
Output Resistance
Oscillator Frequency
8.4
7
24.5
20
MAX.
4.2
20
40
60
40
80
120
29
50
65
12
15.6
18
45.5
53
35
UNITS
CONDITIONS
V
RL=10kΩ, TAMB=+25° C, Note 1
RL=10kΩ, TAMB=-40° C to +85° C
µA
SP6828, TAMB=+25° C, RL = ∞
SP6828, TAMB=-40° C to +85° C,
RL = ∞
SP6829, TAMB=+25° C, RL = ∞
SP6829, TAMB=-40° C to +85° C,
RL = ∞
Ω
IOUT=5mA, TAMB=+25° C
IOUT=5mA, TAMB=-40° C to +85° C
kHz
SP6828, TAMB=+25° C
SP6828, TAMB=-40° C to +85° C
SP6829, TAMB=+25° C
SP6829, TAMB=-40° C to +85° C
99.9
%
RL = ∞
Power Efficiency (Ideal)
97
%
RL=10kΩ, NOTE 2
Power Efficiency (Actual)
95
91
%
Voltage Conversion Efficiency
95
RL=10kΩ, NOTE 3
IOUT = 10mA, NOTE 3
NOTE 1: VOUT = -VIN +200mV
NOTE 2: Power Efficiency (Ideal) =
NOTE 3: Power Efficiency (Actual) =
SP6828DS/11
VOUT x IOUT
-VIN x (-VIN/RL)
VOUT x IOUT
VIN x IIN
SP6828/6829 +3V Low Power Voltage Inverter
2
© Copyright 2000 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect reliability.
VIN....................................................................................................+6.0V
VOUT.................................................................................................-6.0V
V OUT Short Circuit to GND.................................................Indefinite
IOUT...................................................................................................50mA
Storage Temperature.....................................................-65˚C to +150˚C
Power Dissipation (T AMB=+70°C).........................................571mW
Lead Temperature (Soldering)......................................................300 oC
ESD Rating..................................................2kV Human Body Model
SPECIFICATIONS FOR THE SP6828-5
VIN = +5.0V, C1=C2=10µF and TAMB= -40°C to +85°C unless otherwise noted.Typical values are taken specifically at TAMB=+25°C.
Test Circuit Figure 19 unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
1.25
1.5
0.86
5.5
Supply Current
50
Output Resistance
24
Supply Voltage
Oscillator Frequency
6
Voltage Conversion Efficiency
95
UNITS
CONDITIONS
V
RL=10kΩ, TAMB=+25° C, Note 1
RL=10kΩ, TAMB=-40° C to +85° C
115
µA
TAMB=-40° C to +85° C, RL = ∞
50
65
Ω
IOUT=5mA, TAMB=+25° C
IOUT=5mA, TAMB=-40° C to +85° C
20
kHz
TAMB=-40° C to +85° C
99.9
%
RL = ∞
Power Efficiency (Ideal)
98
%
RL=10kΩ, NOTE 2
Power Efficiency (Actual)
91
94
%
RL=10kΩ, NOTE 3
IOUT = 10mA, NOTE 3
NOTE 1: VOUT = -VIN +200mV
NOTE 2: Power Efficiency (Ideal) =
NOTE 3: Power Efficiency (Actual) =
SP6828DS/11
VOUT x IOUT
-VIN x (-VIN/RL)
VOUT x IOUT
VIN x IIN
SP6828/6829 +3V Low Power Voltage Inverter
3
© Copyright 2000 Sipex Corporation
PINOUT
PIN ASSIGNMENTS
Pin 1— VOUT — Inverting charge pump output.
VIN 2
C1- 3
Pin 2 — VIN — Input to the positive power
supply.
5 C1+
VOUT 1
SP6828
SP6829
Pin 3 — C1- — Negative terminal to the charge
pump capacitor.
4 GND
Pin 4 — GND — Ground reference.
Pin 5 — C1+ — Positive terminal to the charge
pump capacitor.
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = +3.3V, C1 = C2 = C3 = 10µF for SP6828, C1 = C2 = C3 = 3.3µF for SP6829, and TAMB = 25oC unless
otherwise noted. The SP6828/6829 devices use the circuit found in Figure 19 when obtaining the following typical
performance characteristics (unless otherwise noted).
60
70
65
40
30
20
50
45
40
30
VIN = 3.3V
25
2.5 3.0
VIN (V)
3.5
20
-60 -40 -20
4.0
Figure 1. Output Resistance vs. Supply Voltage
SP6828DS/11
55
35
10
0
1.5 2.0
VIN = 1.5V
60
ROUT (Ohm)
ROUT (Ohm)
50
VIN = 4.2V
0 20 40 60 80 100
Temperature (oC)
Figure 2. Output Resistance vs. Temperature
SP6828/6829 +3V Low Power Voltage Inverter
4
© Copyright 2000 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = +3.3V, C1 = C2 = C3 = 10µF for SP6828, C1 = C2 = C3 = 3.3µF for SP6829, and TAMB = 25oC unless
otherwise noted. The SP6828/6829 devices use the circuit found in Figure 19 when obtaining the following typical
performance characteristics (unless otherwise noted).
16
40
Pump Frequency (kHz)
15
fOUT (kHz)
14
13
12
11
10
9
0
Figure 3. Charge Pump Frequency vs. Supply Voltage
for the SP6828
41
VIN = 4.2V
VIN = 3.3V
12
11
VIN = 1.5V
10
9
8
-60 -40 -20
3
2
Supply Voltage (V)
4
VIN = 4.2V
39
Pump Frequency (kHz)
14
fPUMP (kHz)
1
Figure 4. Charge Pump Frequency vs. Supply Voltage
for the SP6829
15
37
35
VIN = 3.3V
33
31
VIN = 1.5V
29
27
25
-50
0 20 40 60 80 100
Temperature (oC)
50
0
Temperature ( C)
100
O
Figure 5. Charge Pump Frequency vs. Temperature
for the SP6828
SP6828DS/11
30
25
8
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VIN (V)
13
35
Figure 6. Charge Pump Frequency vs. Temperature
for the SP6829
SP6828/6829 +3V Low Power Voltage Inverter
5
© Copyright 2000 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = +3.3V, C1 = C2 = C3 = 10µF for SP6828, C1 = C2 = C3 = 3.3µF for SP6829, and TAMB = 25oC unless
otherwise noted. The SP6828/6829 devices use the circuit found in Figure 19 when obtaining the following typical
performance characteristics (unless otherwise noted).
40
40
35
VIN = 4.2V;
VOUT = -3.2V
25
Output Current (mA)
IOUT (mA)
30
VIN = 3.3V;
VOUT = -2.5V
20
15
10
VIN = 2V;
VOUT = -1.5V
5
30
VIN = 3.3V;
VOUT = -2.5V
25
20
15
VIN = 2V;
VOUT = -1.5V
10
5
0
0
0
30
20
10
Capacitance (µF)
40
0
Figure 7. Output Current vs. Capacitance for the SP6828
30
20
10
Capacitance (µF)
40
Figure 8. Output Current vs. Capacitance for the SP6829
600
Output Ripple (mVp-p)
300
500
Ripple (mV)
VIN = 4.2V;
VOUT = -3.2V
35
VIN = 4.2V;
VOUT = -3.2V
400
300
200
VIN = 3.3V;
VOUT = -2.5V
100
VIN = 2V;
VOUT = -1.5V
0
0
200
150
100
VIN = 3.3V;
VOUT = -2.5V
50
VIN = 2V;
VOUT = -1.5V
20
30
10
Capacitance (µF)
0
40
0
Figure 9. Output Voltage Ripple vs. Capacitance
for the SP6828
SP6828DS/11
VIN = 4.2V;
VOUT = -3.2V
250
20
30
10
Capacitance (µF)
40
Figure 10. Output Voltage Ripple vs. Capacitance
for the SP6829
SP6828/6829 +3V Low Power Voltage Inverter
6
© Copyright 2000 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = +3.3V, C1 = C2 = C3 = 10µF for SP6828, C1 = C2 = C3 = 3.3µF for SP6829, and TAMB = 25oC unless
otherwise noted. The SP6828/6829 devices use the circuit found in Figure 19 when obtaining the following typical
performance characteristics (unless otherwise noted).
0.0
40
-0.5
35
-1.0
VIN = 2V
-1.5
25
VOUT (V)
IIN (µA)
30
20
15
-2.0
VIN = 3.3V
-2.5
-3.0
VIN = 4.2V
10
-3.5
5
-4.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VIN (V)
-4.5
0
10
20
30 40
IOUT (mA)
50
60
Figure 12. Output Voltage vs. Output Current
Figure 11. SP6828 Supply Current vs. Supply Voltage
100
Voltage Efficiency (%)
Power Efficiency (%)
100
90
80
70
0
5
10
20
15
IOUT (mA)
25
80
70
30
Figure 13. Power Efficiency vs. Output Current
SP6828DS/11
90
0
5
10
20
15
IOUT (mA)
25
30
Figure 14. Voltage Efficiency vs. Output Current
SP6828/6829 +3V Low Power Voltage Inverter
7
© Copyright 2000 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = +3.3V, C1 = C2 = C3 = 10µF for SP6828, C1 = C2 = C3 = 3.3µF for SP6829, and TAMB = 25oC unless
otherwise noted. The SP6828/6829 devices use the circuit found in Figure 19 when obtaining the following typical
performance characteristics (unless otherwise noted).
102
120
100
100
96
80
VEFF (%)
98
VEFF (%)
94
92
60
90
40
88
20
86
0
84
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VIN (V)
Figure 15. Voltage Efficiency vs. Supply Voltage
with a 10kΩ load
0
1
2
3
VIN (V)
4
Figure 16. Voltage efficiency vs. Supply Voltage
without a Load
102
100
98
VIN = 3.3V
VOUT = -3.2V
IL = 5mA
VIN = 3.3V
VOUT = -3.2V
IL = 5mA
VEFF (%)
96
94
92
90
88
86
84
0.5 1.0 1.5 2.0 2.5 3.0 3.5
VIN (V)
Figure 17. Output Noise and Ripple for the SP6828
SP6828DS/11
Figure 18. Output Noise and Ripple for the SP6829
SP6828/6829 +3V Low Power Voltage Inverter
8
© Copyright 2000 Sipex Corporation
VOUT
1
VIN
C1-
C2
RL
+
5
2 SP6828
SP6829
3
4
C1+
GND
C3
C1
Figure 19. SP6828/6829 in its Typical Operating Circuit as a Negative Voltage Converter; this Circuit Was Used to
Obtain the Typical Performance Characteristics Found in Figures 1 Through 18 (unless otherwise noted)
VOUT
1
VIN
C2
C1-
RL
5
2 SP6828
SP6829
3
4
C1+
GND
C3
C1
Figure 20. SP6828/6829 Connected as a Voltage Inverter with the load from VOUT to VIN
SP6828DS/11
SP6828/6829 +3V Low Power Voltage Inverter
9
© Copyright 2000 Sipex Corporation
DESCRIPTION
The SP6828/6829 devices are CMOS Charge
Pump Voltage Converters that can be used to
invert a +1.15V to +4.2V input voltage. These
devices are ideal for designs involving batterypowered and/or board level voltage conversion
applications.
VOUT = -VIN
VIN
The typical operating frequency of the SP6828
is 12kHz. The typical operating frequency of the
SP6829 is 35kHz. The SP6828 has a typical
operating current of 20µA and the SP6829
operates at 40µA. Both devices can output 25mA
with a voltage drop of 500mV. The devices are
ideal for designs using +3.3V or +3.6V lithium
ion batteries such as cell phones, PDAs, medical
instruments, and other portable equipment. The
SP6828/6829 devices combine a high efficiency
with a low quiescent current.
C1
S3
S2
C2
S4
VOUT
Figure 21. Circuit for an Ideal Voltage Inverter
THEORY OF OPERATION
Charge-Pump Output
The output of the SP6828/6829 devices is not
regulated and therefore is dependent on the
output resistance and the amount of load current.
As the load current increases, losses may slightly
increase at the output and the voltage may become
slightly more positive. The loss at the negative
output, VLOSS, equals the current draw, IOUT, from
VOUT times the negative converter's source
resistance, RS:
The SP6828/6829 devices should theoretically
produce an inverted input voltage. In real world
applications, there are small voltage drops at the
output that reduce efficiency. The circuit of an
ideal voltage inverter can be found in Figure 21.
The voltage inverters require two external
capacitors to store the charge. A description of
the two phases follows:
Phase 1
In the first phase of the clock cycle, switches S2
and S4 are opened and S1 and S3 closed. This
connects the flying capacitor, C1, from VIN to
ground. C1 charges up to the input voltage applied
at VIN.
VLOSS = IOUT x RS.
The actual inverted output voltage at VOUT will
equal the inverted voltage difference of VIN and
VLOSS:
VOUT = -(VIN - VLOSS).
Phase 2
In the second phase of the clock cycle, switches
S2 and S4 are closed and S1 and S3 are opened.
This connects the flying capacitor, C1, in parallel
with the output capacitor, C2. The charge stored
in C1 is now transferred to C2. Simultaneously,
the negative side of C2 is connected to VOUT and
the positive side is connected to ground. With
the voltage across C2 smaller than the voltage
across C1, the charge flows from C1 to C2 until
the voltage at the VOUT equals -VIN.
SP6828DS/11
S1
Efficiency
Theoretically, the total power loss of a switched
capacitor voltage converter can be summed up as
follows:
∑PLOSS = PINT + PCAP + PCONV,
where PLOSS is the total power loss, PINT is the total
internal loss in the IC including any losses in the
MOSFET switches, PCAP is the resistive loss of
SP6828/6829 +3V Low Power Voltage Inverter
10
© Copyright 2000 Sipex Corporation
where
the charge pump capacitors, and PCONV is the total
conversion loss during charge transfer between
the flying and output capacitors. These are the
three theoretical factors that may effect the power
efficiency of the SP6828/6829 devices in designs.
POUT = VOUT x IOUT
Internal losses come from the power dissipated
in the IC's internal circuitry.
PIN = VIN x IIN
Losses in the charge pump capacitors will be
induced by the capacitors' ESR. The effects of
the ESR losses and the output resistance can be
found in the following equation:
where POUT is the power output, VOUT is the
output voltage, IOUT is the output current, PIN is
the power from the supply driving the SP6828/
6829 devices, VIN is the supply input voltage, and
IIN is the supply input current.
and
IOUT2 x ROUT = PCAP + PCONV
Ideal Efficiency
The ideal efficiency is not the true power
efficiency because it is not calculated relative to
the input power which includes the input current
losses in the charge pump. The ideal efficiency
can be determined with the following equation:
and
ROUT ≈ 4 x (2 x RSWITCHES + ESRC1) +
1
ESRC2 + fOSC x C1 ,
where IOUT is the output current, ROUT is the
circuit's output resistance, RSWITCHES is the internal
resistance of the MOSFET switches, ESRC1 and
ESRC2 are the ESR of their respective capacitors,
and fOSC is the oscillator frequency. This term
with fOSC is derived from an ideal switchedcapacitor circuit as seen in Figure 22.
Efficiency (IDEAL) =
POUT
x 100% ,
POUT (IDEAL)
where
POUT (IDEAL) = -VIN x
Conversion losses will happen during the charge
transfer between the flying capacitor, C1, and
the output capacitor, C2, when there is a voltage
difference between them. PCONV can be determined
by the following equation:
-VIN
RL ,
and POUT is the measured power output. Both
efficiencies are provided to designers for
comparison.
f
VOUT
V+
PCONV = fOSC x [ 1/2 x C1 x (VIN2 - VOUT2) +
C1
/2 x C2 x (VRIPPLE2 - 2 x VOUT x VRIPPLE) ].
1
C2
RL
Actual Efficiency
To determine the actual efficiency of the SP6828/
6829 device operation, a designer can use the
following equation:
Requivalent
VOUT
V+
P
Efficiency (ACTUAL) = OUT x 100% ,
PIN
Requivalent =
1
f x C1
C2
RL
Figure 22. Equivalent Circuit for an Ideal Switched
Capacitor
SP6828DS/11
SP6828/6829 +3V Low Power Voltage Inverter
11
© Copyright 2000 Sipex Corporation
Input Bypass Capacitor
The bypass capacitor at the input pin will reduce
AC impedance and the impact of any of the
SP6828/6829 devices' switching noise. It is
recommended that for heavy loads a bypass
capacitor approximately equal to the flying
capacitor, C1, be used. For light loads, the value
of the bypass capacitor can be reduced.
APPLICATION INFORMATION
For the following applications, C1 = C2 = 10µF
for the SP6828 and C1 = C2 = 3.3µF for the
SP6829.
Capacitor Selection
Low ESR capacitors are needed to obtain low
output resistance. Refer to Table 1 for some
suggested low ESR capacitors. The output
resistance of the SP6828/6829 devices is a
function of the ESR of C1 and C2. This output
resistance can be determined by the equation
previously provided in the Efficiency section:
When loading the SP6828/6829 devices from IN
to OUT, the input current remains constant
(disregarding any spikes due to internal
switching). Implementing a 0.1µF bypass
capacitor should be sufficient.
When loading the SP6828/6829 devices from
OUT to GND, the current from the supply will
flow into the input for half of the cycle and will
be zero for the other half of the cycle. Designers
should implement a large bypass capacitor
(C3 = C1) if the supply has a high AC impedance.
ROUT ≈ 4 x (2 x RSWITCHES + ESRC1) +
1
ESRC2 + fOSC x C1 ,
where ROUT is the circuit output resistance,
RSWITCHES is the internal resistance of the MOSFET
switches, ESRC1 and ESRC2 are the ESR of their
respective capacitors, and fOSC is the oscillator
frequency. This term with fOSC is derived from an
ideal switched-capacitor circuit as seen in
Figure 21.
Negative Voltage Converter
The typical operating circuit for the SP6828/
6829 devices is a negative voltage converter.
Refer to Figure 19. This circuit is used to obtain
the Typical Performance Characteristics found
in Figures 1 to 18 (unless otherwise noted).
Minimizing the ESR of C1 and C2 will minimize
the total output resistance and will improve the
efficiency.
Voltage Inverter with the Load from
VOUT to VIN
A designer can find the most common application
for the SP6828/6829 devices in Figure 20 as a
voltage inverter. The only external components
needed are 3 capacitors: the flying capacitor, C1,
the output capacitor, C2, and the bypass capacitor,
C3 (if necessary).
Flying Capacitor
Decreasing flying capacitor, C1, values will
increase the output resistance of the SP6828/
6829 devices while increasing C1 will reduce the
output resistance. There is a point where
increasing C1 will have a negligible effect on the
output resistance due to the the domination of the
output resistance by the internal MOSFET switch
resistance and the total capacitor ESR.
Driving Excessive Loads
The output should never be pulled above ground.
A designer should implement a Schottky diode
(1N5817) from OUT to GND when driving
heavy loads where a higher supply is sourcing
current into OUT. Refer to Figure 23 for this
circuit connection.
Output Capacitor
Increasing output capacitor, C2, values will
decrease the output ripple voltage. Reducing the
ESR of C2 will reduce both output ripple voltage
and output resistance. If higher output ripple can
be tolerated in designs, smaller capacitance values
for C2 should be used with light loads. The
following equation can be used to calculate the
peak-to-peak ripple voltage:
VRIPPLE = 2 x IOUT x ESRC2 +
SP6828DS/11
IOUT
fOSC x C2 .
SP6828/6829 +3V Low Power Voltage Inverter
12
© Copyright 2000 Sipex Corporation
GND
4
SP6828
SP6829
1
OUT
1N5817
Figure 23. Protection for Heavy Loads
C3
+VIN
D1 = D2 = 1N4148
D1
D2
IN
VOUT1
2
C1+
GND
C1
C1-
5
SP6828
SP6829
C4
4
1
3
OUT
VOUT2
C2
VOUT1 = (2 x VIN) - VFD1 - VFD2
VOUT2 = -VIN
where
VOUT1 = positive doubled output voltage,
VIN = input voltage,
VFD1 = forward bias voltage across D1,
VFD2 = forward bias voltage across D2, and
VOUT2 = inverted output voltage.
Figure 24. SP6828/6829 Device Connected in a Doubler/Inverter Combination Circuit
SP6828DS/11
SP6828/6829 +3V Low Power Voltage Inverter
13
© Copyright 2000 Sipex Corporation
+VIN
OFF
ON
IN
Shutdown
Logic
2
C1+
GND
C1
C1-
5
CIN
0.1µF
SP6828
SP6829
4
1
3
OUT
VOUT
C2
Figure 25. SP6828/6829 Device with Shutdown Control
Combining a Doubler and Inverter Circuit
A designer can connect a SP6828/6829 device in
a combination doubler/inverter circuit as seen in
Figure 24. The doubler uses capacitors C3 and
C4 while the inverter uses C1 and C2. Loading
either output decreases both output voltages to
GND because both the doubler and the inverter
circuits use the charge pump. Designers should
not allow the total current output from the doubler
and the inverter to exceed 40mA.
Connecting in Parallel
A designer can parallel a number of SP6828/
6829 devices to reduce the output resistance for
specific designs. All devices will need their own
flying capacitor, C1, but a single output capacitor
will serve all of the devices connected in parallel
by increasing the capacitance of C2 by a factor of
n where n equals the total number of devices
connected. This connection can be found in
Figure 26.
Implementing Shutdown
If shutdown control of the SP6828/6829 devices
is necessary, the circuit found in Figure 25 can
be implemented. The 0.1µF capacitor at IN
absorbs transient input currents. The output
resistance of the devices can be determined by
the following equation:
Cascading Devices
A designer can cascade SP6828/6829 devices to
produce a larger inverted voltage output. Refer
to Figure 27 for this circuit connection. With
two cascaded devices, the unloaded output
voltage is decreased by the output resistance of
the first device multiplied by the quiescent current
of the second device connected. The total output
resistance is greatly increased when more than
two devices are cascaded.
ROUT = 20 + 2 x RBUFFER ,
where ROUT is the output resistance and RBUFFER
is the output resistance of the buffer driving IN.
RBUFFER can be reduced by connecting multiple
buffers in parallel at IN. The polarity of the
SHUTDOWN signal can be changed by using a
noninverting buffer to drive IN.
SP6828DS/11
Layout and Grounding
Designers should make an effort to minimize
noise by paying special attention to the circuit
layout with the SP6828/6829 devices. External
components should be connected in close
proximity to the device and a ground plane
should be implemented. This will keep electrical
traces short minimizing parasitic inductance and
capacitance.
SP6828/6829 +3V Low Power Voltage Inverter
14
© Copyright 2000 Sipex Corporation
+VIN
IN
C1
GND
C1+
SP6828
SP6829
5
4
C1
GND
2
C1+
SP6828
SP6829
5
4
“1”
C1-
C1
“2”
OUT
1
3
IN
IN
2
2
C1+
C1-
RL
SP6828
SP6829
5
4
“n”
OUT
1
3
GND
C1-
OUT
1
3
VOUT
VOUT = -VIN
R
RTOT = OUT
n
where VOUT = output voltage,
VIN = input voltage,
RTOT = total resistance of the devices connected in parallel,
ROUT = the output resistance of a single device, and
n = the total number of devices connected in parallel.
C2 x n
Figure 26. SP6828/6829 Devices Connected in Parallel to Reduce Total Output Resistance
+VIN
IN
C1+
GND
C1
C1-
SP6828
SP6829
5
4
C1+
C1
“1”
5
3
IN
IN
2
2
OUT
GND
C1-
5
2
SP6828
SP6829
C1+
C1
4
“2”
1
3
OUT
GND
C1-
3
SP6828
SP6829
4
“n”
1
5
C2
C2
OUT
VOUT
C2
VOUT = -n x VIN
where VOUT = output voltage,
VIN = input voltage, and
n = the total number of devices connected.
Figure 27. SP6828/6829 Devices Cascaded to Increase Output Voltage
SIPEX PART
NUMBER
MANUFACTURER
PART NUMBER
CAPACITANCE /
VOLTAGE
MAX ESR
@ 100kHz
PACKAGE
SP6828
AVX
TPSC106*025
10µF / 25V
0.5Ω
SM Case C
SP6828
SPRAGUE
593D106X035
10µF / 35V
0.3Ω
SM Case D
SP6828
KEMET
T494C106*020
10µF / 20V
0.5Ω
SM Case C
SP6828
SANYO-OSCON
94SC106X0016C
10µF / 16V
0.15Ω
Radial Case C
SP6829
KEMET
T494B335*020
3.3µF / 20V
1.5Ω
SM Case B
SP6829
SPRAGUE
595D335X0035
3.3µF / 35V
2.0Ω
SM Case C
SP6829
SANYO-OSCON
94SC335X0016A
3.3µF / 16V
0.35Ω
Radial Case A
Table 1. Suggested Low ESR Tantalum Capacitors
SP6828DS/11
SP6828/6829 +3V Low Power Voltage Inverter
15
© Copyright 2000 Sipex Corporation
PACKAGE: SOT23-5
b
C
L
e
E
e1
D
C
L
a
C
L
0.20
DATUM 'A'
A A2
C
E1
A
L
2
A1
A
.10
MIN
MAX
A
0.90
1.45
A1
0.00
0.15
A2
0.90
1.30
b
0.25
0.50
C
0.09
0.20
D
2.80
3.10
E
2.60
3.00
E1
1.50
1.75
L
0.35
0.55
SYMBOL
e
0.95ref
e1
1.90ref
a
SP6828DS/11
0
O
10
SP6828/6829 +3V Low Power Voltage Inverter
16
O
© Copyright 2000 Sipex Corporation
ORDERING INFORMATION
Model
Temperature Range
Package Type
SP6828EK . ............................................ -40˚C to +85˚C ............................................... SOT23-5
SP6828-5EK ........................................... -40˚C to +85˚C ............................................... SOT23-5
SP6828EK/TR ......................................... -40˚C to +85˚C ............................................... SOT23-5
SP6828-5EK/TR ..................................... -40˚C to +85˚C ............................................... SOT23-5
SP6829EK . ............................................ -40˚C to +85˚C ............................................... SOT23-5
SP6829EK/TR ......................................... -40˚C to +85˚C ............................................... SOT23-5
Please consult the factory for pricing and availability on a Tape-On-Reel option.
Corporation
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: [email protected]
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
SP6828DS/11
SP6828/6829 +3V Low Power Voltage Inverter
17
© Copyright 2000 Sipex Corporation