SL4017B Counter/Divider High-Voltage Silicon-Gate CMOS The SL4017B is 5-stage Johnson counter having 10 decoded outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded outputs are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes one cycle every 10 clock input cycles in the SL4017B. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND SL S System Logic Semiconductor ORDERING INFORMATION SL4017BN Plastic SL4017BD SOIC T A = -55° to 125° C for all packages PIN ASSIGNMENT • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply SL4017B FUNCTION TABLE Clock Clock Enable L X X X Reset Output State * L no change H L no change X H reset counter Q0=H, Q1Q9=L, C0=H L L Advance to next state X L no change X L no change H L Advance to next state * Carry Out=H for Q0,Q1,Q2,Q3 or Q4=H Carry Out = L otherwise, X=don’t care SL S System Logic Semiconductor SL4017B MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT I IN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW -65 to +150 °C 260 °C Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C * RECOMMENDED OPERATING CONDITIONS Symbol VCC DC Supply Voltage (Referenced to GND) VIN, VOUT TA Parameter DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SL S System Logic Semiconductor SL4017B DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V ≥-55°C 25°C ≤125 °C Unit VIH Minimum HighLevel Input Voltage VOUT=0.5V or VCC - 0.5V VOUT=1.0V or VCC - 1.0V VOUT=1.5V or VCC - 1.5V 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V VIL Maximum Low Level Input Voltage VOUT=0.5V or VCC - 0.5V VOUT=1.0V or VCC - 1.0V VOUT=1.5V or VCC - 1.5V 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum HighLevel Output Voltage VIN=GND or VCC 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.9 5 V VOL Maximum LowLevel Output Voltage VIN=GND or VCC 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V I IN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA I CC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 µA I OL Minimum Output Low (Sink) Current VIN= GND or VCC UOL =0.4 V UOL =0.5 V UOL =1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Minimum Output High (Source) Current VIN= GND or VCC UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 10 15 -2.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 I OH mA mA SL S System Logic Semiconductor SL4017B AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200kΩ, Input tr =tf=20 ns) VCC Symbol V ≥-55°C 25°C Maximum Clock Frequency 5.0 10 15 2.5 5 5.5 tPLH, tPHL Maximum Propagation Delay, Clock to Decode Output (Figure 1) 5.0 10 15 tPLH, tPHL Maximum Propagation Delay, Clock to Carry Output (Figure 1) tTLH, tTHL tPLH, tPHL fmax CIN Parameter Guaranteed Limit ≤125° C Unit 2.5 5 5.5 1.25 2.5 2.75 MHz 650 270 170 650 270 170 1300 540 340 ns 5.0 10 15 600 250 160 600 250 160 1200 500 320 ns Maximum Output Transition Time, Carry Output or Decode Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns Maximum Propagation Delay, Reset to Carry Output or Decode Output (Figure 1) 5.0 10 15 530 230 170 530 230 170 1060 460 340 ns Maximum Input Capacitance - 5 pF TIMING REQUIREMENTS (VCC=5.0V±10%, C L=50pF, Input tr =tf=20 ns, RL=200kΩ ) VCC Guaranteed Limit Symbol Parameter V ≥-55°C 25°C ≤125° C tw Minimum Pulse Width, Clock (Figure 1) 5.0 10 15 200 90 60 200 90 60 400 180 120 tr, tf Maximum Input Rise and Fall Times, Clock (Figure 1) 5.0 10 15 tw Minimum Pulse Width, Reset (Figure 1) 5.0 10 15 260 110 60 260 110 60 520 220 120 ns Minimum Removal Time, Reset (Figure 1) 5.0 10 15 400 280 150 400 280 150 800 560 300 ns trem SL S System Logic Semiconductor Unit ns µs UNLIMITED SL4017B tSU Minimum Setup Time, Clock Inhibit to Clock (Figure 1) 5.0 10 15 230 100 70 230 100 70 SL S 460 200 140 ns System Logic Semiconductor SL4017B Figure 1. Switching Waveforms Timing diagram SL S System Logic Semiconductor SL4017B EXPANDED LOGIC DIAGRAM SL S System Logic Semiconductor