IW4017B Description The IW4017B is 5 –stageJohnson counter having 10 decode outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBITsignal is low. Counter advancement via the clock line isinhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits highspeed operation, 2- input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded Outputs are normally low and go high only at their C ARR YOUT respective decoded time slot. Each decoded output remains high for one full clock cycle. A Signal completes one cycle every 10 clock input cycles. Features Operating Voltage Range: 3.0 to 18 V at 18 V over full packageMaximum input current of 1 utemperature range ;100 nA at 18 V and 25 C A Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply Pin Assignment 16 DIP - 16 16 2.5 V min @ 15.0 V supply SOP - 16 Logic Diagram Package Function Table Clock L X X PIN16 = VCC PIN 8 = GND Clock Enable X H X Reset Output State L L H no change no change reset counter Q0=H, Q1-Q9=L, C0=H Advance to next state L L X L no change X L no change H L Advance to next state Carry Out=H for Q0 ,Q1,Q2,Q3 or Q4=H Carry Out = L otherwise, X = don ' t care BEIJING ESTEK ELECTRONICS CO.,LTD 1 IW4017B Absolute Maximum Ratings Symbol Parameter Value Unit -0.5 to 20 V VCC DC Supply Voltage (Referenced to GND) V IN DC Input Voltage (Referenced to GND) -0.5 to VCC 0.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC 0.5 V +- 10 750 500 mA mW 100 mW -65 to 150 °C 260 °C IIN DC Input Current, per Pin PD Power Dissipation in Still Air, Plastic PD SOIC Package Power Dissipation per Output Transistor Tstg DIP Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating - Plastic DIP: - 10 mW/ °C from 65°to 125 °C SOIC Package °C from 65°to 125 °C Recommended Operating Conditions Symbol VCC VIN , VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND (VIN or VOUT) VCC . Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC Unused outputs must be left open. BEIJING ESTEK ELECTRONICS CO.,LTD 2 IW4017B DC Electrical Characteristics (Voltages Referenced to GND) VCC Symbol 125 Parameter Test Conditions Guaranteed Limit V ³ -55°C 25°C £ Unit VIH Minimum High-Level VOUT=0.5 V or VCC - 0.5 V Input Voltage VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V 5.0 10 15 3.5 7 11 3.5 7 11 °C 3.5 7 11 VIL Maximum Low Level Input Voltage 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum High-Level VIN=GND or VCC Output Voltage 5.0 10 15 5.0 10 15 4.95 9.95 14.95 4.5 9.0 13.5 4.95 9.95 14.95 4.5 9.0 13.5 4.95 9.95 14.95 4.5 9.0 13.5 V 0.05 0.05 0.05 0.5 1.0 1.5 0.05 0.05 0.05 0.5 1.0 1.5 0.05 0.05 0.05 0.5 1.0 1.5 V VIL =1.5V, VIH=3.5V, IO=1µA VIL =3.0V, VIH=7.0V, IO=1µA VIL =4.0V, VIH=11V, IO=1µA 5.0 10 15 5.0 10 15 VIN= GND or VCC 18 +- 0.1 +- 0.1 +- 1.0 uA VIN= GND or VCC 5.0 10 15 20 1.0 2.0 4.0 20 1.0 2.0 4.0 20 30 60 120 600 uA VIN= GND or VCC VOL=0.4 V VOL=0.5 V VOL=1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 VIN= GND or VCC VOH=4.6 V VOH=2.5 V VOH=9.5 V VOH=13.5 V 5.0 5.0 10 15 -0.64 –2.0 –1.8 –4.2 -0.51 –1.6 –1.3 –3.4 -0.36 –1.15 –0.9 –2.4 VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V VIL =1.5V, VIH=3.5V, IO=-1µA VIL =3.0V, VIH=7.0V, IO=-1µA VIL =4.0V, VIH=11V, IO=-1µA VOL IIN Maximum Low-Level Output Voltage Maximum Input Leakage Current ICC Maximum Quiescent Supply Current (per Package) I Minimum Low (Sink)Output Current IOH Minimum Output High (Source) Current VIN=GND or VCC V mA mA BEIJING ESTEK ELECTRONICS CO.,LTD 3 IW4017B AC Electrical Characteristics (C L=50pF, RL=200 k , Input t r =t f =20 ns) VCC Guaranteed Limit V -55°C 25°C 125°C Unit 5.0 10 15 2.5 5 5.5 2.5 5 5.5 2.0 4.0 5.0 MHz tPLH, tPHL MaximumPropagation Delay, Clock to Decode Output (Figure 1) 5.0 10 15 650 270 170 650 270 170 800 350 250 ns tPLH, tPHL Maximum Propagation Delay, Clock to Carry Output (Figure 1) 5.0 10 15 600 250 160 600 250 160 750 300 200 ns tTLH, tTHL Maximum Output Transition Time, Carry Output or Decode Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 300 150 120 ns tPLH, tPHL Carry Maximum Propagation Delay, Reset to 5.0 10 15 530 230 170 530 230 170 700 300 250 ns Symbol fmax Parameter Maximum Clock Frequency Output or Decode Output (Figure 1) CIN Maximum Input Capacitance Timing Requirements - pF 5 (VCC=5.0V +- 10%, CL=50pF, RL=200 k , Input t r =t f =20 ns) Symbol Parameter V ﾳ -55°C 25°C 125°C Unit 200 90 60 200 90 60 300 150 100 ns tw Minimum Pulse Width, Clock (Figure 1) 5.0 10 15 tr, tf Maximum Input Rise and Fall Times, Clock (Figure 1) 5.0 10 15 tw Minimum Pulse Width, Reset (Figure 1) 5.0 10 15 260 110 60 260 110 60 400 180 100 ns trem Minimum Removal Time, Reset (Figure 1) 5.0 10 15 400 280 150 400 280 150 550 400 200 ns tSU Minimum Setup Time, Clock Inhibit to Clock (Figure 1) 5.0 10 15 230 100 70 230 100 70 300 150 100 ns ms UNLIMITED BEIJING ESTEK ELECTRONICS CO.,LTD 4 IW4017B 1/ ft s u CLOCK max ft CLOCK INHIBI T V % CC % 90 90 50% 50% 10 10 50% tw 50% 50 50% % %D % GN rt t rem V CC 50% GN D tw V CC 50% RESET 50% GN D t PH L H t PL Q1 DECODE Q9 OUTPU Q0 OR 90% CARRY OUTPU T 10% V CC 50% 50% GN D T DECODE t PH L t PLH 90% 10% 50% 50% t THL THL V CC GN D Figure 1. Switching Waveforms Timing diagram BEIJING ESTEK ELECTRONICS CO.,LTD 5 IW4017B Expanded Logic Diagram Address : 6A06--6A07 Rm 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing Postalcode:100039 Tel: 86-010-58895780 / 81 / 82 / 83 / 84 Fax : 010-58895793 Http://www.estek.com.cn Email:[email protected] REV No:01-060833 BEIJING ESTEK ELECTRONICS CO.,LTD 6