SL4541B Programmable Timer High-Performance Silicon-Gate CMOS The SL4541 programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitons and can also be reset via the MASTER RESET input. The output from this timer is the Q or not Q output from the 8th, 10th, 13th, or 16th counter stage. The desired stage is chosen using time-select inputs A and B. The output is available in either of two modes selectable via the MODE input, pin 10. When this MODE input is a logic “1”,the output will be a continuous square wave having a ORDERING INFORMATION frequency equal to the oscillator frequency divided by 2N. With the SL4541BN Plastic MODE input set to logic ”0” and after a MASTER RESET is initiated, SL4541BD SOIC the output (assuming Q output has been selected) changes from a low N-1 T = -55° to 125° C for all packages A to a high state after 2 counts and remains in that state until another MASTER RESET pulse is applied or the MODE input is set to a logic “1”. Timing is initialized by setting the AUTO RESET input (pin 5) to logic “0”and turning power on. If pin 5 is set to logic “1”, the AUTO RESET circuit is disabled and counting will not start untill after a positive MASTER RESET pulse is applied and returns to a low level. The AUTO RESET consumes an appreciable amount of power and should not be used if low-power operation is desired. For reliable automatic power-on reset, VCC should be greater than 5V. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply LOGIC DIAGRAM PIN ASSIGNMENT PIN 14 =VCC PIN 7 = GND PINS 4,11 = NO CONNECTION SLS System Logic Semiconductor NC = NO CONNECTION SL4541B MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW -65 to +150 °C 260 °C Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL4541B DC ELECTRICAL CHARACTERISTICS Digital Section VCC Symbol Parameter Guaranteed Limit Test Conditions V ≥ -55 °C ≤ 25 °C ≤ 125 °C Unit VIH Minimum High-Level Input Voltage VOUT=0.5V or VCC-0.5V VOUT=1.0V or VCC-1.0V VOUT=1.5V or VCC-1.5V 5 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V VIL Maximum Low -Level Input Voltage VOUT=0.5V or VCC-0.5V VOUT=1.0V or VCC-1.0V VOUT=1.5V or VCC-1.5V 5 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum High-Level Output Voltage VIN=GND or VCC 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN=GND or VCC 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage VIN= GND or VCC Current 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 µA IOL Minimum Output Low (Sink) Current VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V 5.0 10 15 1.9 5 12.6 1.55 4 10 1.08 2.8 7.2 Minimum Output High (Source) Current VIN= GND or VCC UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 10 15 -6.2 -1.9 -5 -12.6 -5 -1.55 -4 -10 -3 -1.08 -2.8 -7.2 IOH SLS System Logic Semiconductor mA mA SL4541B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ, Input t r=t f=20 ns) VCC Symbol fmax Parameter Maximum Clock Frequency (Figure 1) tPLH, t PHL Maximum Propagation Delay, Clock to Q (Figure 1) (28) (216) Guaranteed Limit V ≥-55°C 25°C ≤125°C Unit 5.0 10 15 1.5 4 6 1.5 4 6 0.75 2 3 MHz 5.0 10 15 10.5 3.8 2.9 10.5 3.8 2.9 21 7.6 5.8 ns 5.0 10 15 18 10 7.5 18 10 7.5 36 20 15 tTHL Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 tTLH Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 360 180 130 360 180 130 720 360 260 CIN Maximum Input Capacitance - 7.5 ns pF TIMING REQUIREMENTS (CL=50pF, RL=200kΩ, Input t r=t f=20 ns) VCC Symbol tw tr,t f Parameter Minimum Pulse Width, Master Reset or Clock (Figure 1) 5 10 15 Maximum Rise and Fall Time, Clock (Figure 1) 5 10 15 Guaranteed Limit +25° C -40° C to +85° C Unit 900 300 225 1800 600 450 ns µs Unlimited SLS System Logic Semiconductor SL4541B Figure 1. Switching Weveforms FREQUENCY SELECTION TABLE INPUTS A B L L L H H L H H No. of Stages N 13 10 8 16 Count 2N 8192 1024 256 65536 FUNCTION TABLE PIN 5 6 9 10 STATE 0 1 Auto Reset On Auto Reset Disable Master Reset Off Master Reset On Output Initially Output Initially High Low After Reset After Reset (not Q) (Q) Single Transition Recycle Mode Mode EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor