SL4503B Hex Buffer High-Voltage Silicon-Gate CMOS The SL4503B is a hex noninverting buffer with 3-state outputs having high sink- and source-current capability. Two output ENABLE controls are provided, one of which controls four buffers and the other controls the remaining two buffers. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Nois e margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION SL503BN Plastic SL4503BD SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs PIN 16=VCC PIN 8= GND Output Enable 1,Enable 2 A Y L L L L H H H X Z Z = high impedance X = don’t care SLS System Logic Semiconductor SL4503B MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW -65 to +150 °C 260 °C Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC DC Supply Voltage (Referenced to GND) VIN, VOUT TA Parameter DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL4503B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V ≥-55°C 25°C ≤125 °C Unit VIH Minimum High-Level Input Voltage VOUT= VCC - 0.5V VOUT= VCC - 1.0 V VOUT= VCC - 1.5V 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V VIL Maximum Low -Level Input Voltage VOUT=0.5 V VOUT=1 V VOUT=1.5 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum High-Level Output Voltage VIN= VCC 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN=GND 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 1 2 4 20 1 2 4 20 30 60 120 600 µA IOL Minimum Output Low (Sink) Current VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V 5.0 10 15 2.6 6.5 19.2 2.1 5.5 16.1 1.3 3.8 11.2 Minimum Output High VIN= GND or VCC (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 10 15 -1.2 -5.8 -3.1 -8.2 -1.02 -4.8 -2.6 -6.8 -0.7 -3 --1.8 -4.8 18 ±0.4 ±0.4 ±12 IOH IOZ Maximum Tree-State Leakage Current Output in High-Impedance State VIN= GND or VCC VOUT= GND or VCC mA mA SLS µA System Logic Semiconductor SL4503B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ unless otherwise specified, Input tr=t f=20 ns) VCC Guaranteed Limit Symbol Parameter V ≥-55°C 25°C ≤125°C Unit tPLH Maximum Propagation Delay, Input A to Output Y (Figure 1) 5.0 10 15 150 70 50 150 70 50 300 140 100 ns tPHL Maximum Propagation Delay, Input A to Output Y (Figure 1) 5.0 10 15 110 50 35 110 50 35 220 100 70 ns tPHZ, t PZH Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 kΩ 5.0 10 15 140 60 50 140 60 50 280 120 100 ns tPZL, t PLZ Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 kΩ 5.0 10 15 180 80 70 180 80 70 360 160 140 ns tTLH Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 90 45 35 90 45 35 180 90 70 ns tTHL Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 70 40 25 70 40 25 140 80 50 ns CIN Maximum Input Capacitance - 7.5 pF Maximum Tree-State Output Capacitance (Output in High-Impedance State) - 15 pF COUT Figure 1. Switching Waveforms SLS System Logic Semiconductor Figure 2. Switching Waveforms SL4503B EXPANDED LOGIC DIAGRAM (1/6 of the Device) SLS System Logic Semiconductor