SL74HC165 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS The SL74HC165 is identical in pinout to the LS/ALS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device is an 8-bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial Shift/ Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table). The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC165N Plastic SL74HC165D SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 16=VCC PIN 8 = GND FUNCTION TABLE Inputs Internal Stages Output Operation Serial Shift/ Parallel Load Clock Clock Inhibit SA A-H QA QB-QG QH L H X X a...h a b-g h Asynchronous Parallel Load H L L X L QAn-QFn QGn Serial Shift via Clock H L H X H QAn-QFn QGn H L L X L QAn-QFn QGn Serial Shift via Clock H L H X H QAn-QFn QGn Inhibit H X H X X H H X X X H L L X X no change Inhibited Clock no change No Clock X = Don’t Care QAn-QFn = Data shifted from the preceding stage SLS System Logic Semiconductor SL74HC165 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HC165 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit Test Conditions V 25 °C to -55°C ≤85 °C ≤125 °C Unit Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN= VIL or VIH IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Symbol Parameter VIH VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA VOL Maximum Low-Level Output Voltage VIN= VIL or VIH IOUT ≤ 20 µA V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 8.0 80 160 µA SLS System Logic Semiconductor SL74HC165 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 8) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 MHz tPLH, t PHL Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH (Figures 1 and 8) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tPLH, t PHL Maximum Propagation Delay , SerialShift./.Parallel Load to QH or QH (Figures 2 and 8) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tPLH, t PHL Maximum Propagation Delay, Input H to QH or QH (Figures 3 and 8) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tTLH, t THL Maximum Output Transition Time, Any Output (Figures 1 and 8) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns - 10 10 10 pF CIN CPD SLS Maximum Input Capacitance Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 85 System Logic Semiconductor pF SL74HC165 TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit tSU Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load (Figure 4) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tSU Minimum Setup Time, Input SA to Clock (or Clock Inhibit) (Figure 5) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tSU Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit) (Figure 6) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tSU Minimum Setup Time, Clock to Clock Inhibit (Figure 7) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns th Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs (Figure 4) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns th Minimum Hold Time, Clock (or Clock Inhibit) to Input SA (Figure 5) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns th Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load (Figure 6) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns trec Minimu m Recovery Time, Clock to Clock Inhibit (Figure 7) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tw Minimum Pulse Width, Clock (or Clock Inhibit) (Figure 1) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tw Minimum Pulse Width, Serial Shift/Parallel Load (Figure 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns SLS System Logic Semiconductor SL74HC165 SWITCHING WAVEFORMS SLS System Logic Semiconductor SL74HC165 TIMING DIAGRAM EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor