SL74HC374 Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS The SL74HC374 is identical in pinout to the LS/ALS374. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. Data meeting the setup and hold time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip-flops, but when Output Enable is high, the outputs are forced to the high-impedance state; thus, data may be stored even when the outputs are not enabled. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC374N Plastic SL74HC374D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 20=VCC PIN 10 = GND Inputs Output Enable D Q L H H L L L X no change X Z L H Clock Output L,H, X X = don’t care Z = high impedance SLS System Logic Semiconductor SL74HC374 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HC374 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit Test Conditions V 25 °C to -55°C ≤85 °C ≤125 °C Unit Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 VIN= VIL or VIH IOUT ≤ 20 µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN= VIL or VIH IOUT ≤ 6.0 mA IOUT ≤7.8 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Symbol Parameter VIH VOL Maximum Low-Level Output Voltage V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA IOZ Maximum Three State Leakage Current Output in High-Impedance State VIN =VIH or VIL VOUT= VCC or GND 6.0 ±0.5 ±5.0 ±10 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 4.0 40 160 µA SLS System Logic Semiconductor SL74HC374 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 4.5 6.0 6.0 30 35 5.0 24 28 4.0 20 24 MHz tPLH, t PHL Maximum Propagation Delay, Clock to Q (Figures 1 and 4) 2.0 4.5 6.0 125 25 21 155 31 26 190 38 32 ns tPLZ, t PHZ Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tPZH, t PZL Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tTLH, t THL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Maximum Input Capacitance - 10 10 10 pF Maximum Three-State Output Capacitance (Output in High-Impedance State) - 15 15 15 pF Symbol fmax CIN COUT Parameter Power Dissipation Capacitance (Per Enabled Output) CPD Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 34 pF TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit tSU Minimum Setup Time, Data to Clock (Figure 3) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns th Minimum Hold Time, Clock to Data (Figure 3) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns SLS System Logic Semiconductor SL74HC374 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit Figure 5. Test Circuit EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor