SLS SL74LV32

TECHNICAL DATA
SL74LV32
Quad 2-Input OR Gate
The SL74LV32 is low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT32A.
The SL74LV32 provides the 2-input AND function.
•
•
•
Optimized for Low Voltage applications: 1.2 to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Low Input Current
ORDERING INFORMATION
SL74LV32N
Plastic
SL74LV32D
SOIC
IZ74LV32
Chip
TA = -40° ÷ 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
A1
Y1
B1
A2
Y2
B2
A3
Y3
B3
FUNCTION TABLE
A4
Input
Y4
B4
PIN 14 =VCC
PIN 7 = GND
Output
A
B
Y = A*B
L
L
L
L
H
H
H
L
H
H
H
H
H - high level
L - low level
SLS
System Logic
Semiconductor
1
SL74LV32
MAXIMUM RATINGS *
Symbol
VCC
IIK *
DC supply voltage (Referenced to GND)
Value
Unit
-0.5 ÷ +5.0
V
1
DC input diode current
±20
mA
2
DC output diode current
±50
mA
DC output source or sink current
-bus driver outputs
±25
mA
DC VCC current for types with
- bus driver outputs
±50
mA
DC GND current for types with
- bus driver outputs
±50
mA
Power dissipation per package, plastic DIP+
SOIC package+
750
500
mW
-65 ÷ +150
°C
260
°C
IOK *
IO *
Parameter
3
ICC
IGND
PD
Tstg
TL
Storage temperature
Lead temperature, 1.5 mm from Case for 10 seconds
(Plastic DIP ), 0.3 mm (SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SOIC Package: : - 8 mW/°C from 70° to 125°C
* 1: VI < -0.5V or VI > VCC+0.5V
* 2: Vo < -0.5V or Vo > VCC+0.5V
* 3: -0.5V < Vo < VCC+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, t f
Input Rise and Fall Time
VCC =1.2 V
VCC =2.0 V
VCC =3.0 V
VCC =3.6 V
Min
Max
Unit
1.2
3.6
V
0
VCC
V
-40
+125
°C
0
0
0
0
1000
700
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
SLS
System Logic
Semiconductor
2
SL74LV32
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
Guaranteed Limit
VCC,
V
-40°C ÷ 85°C
25°C
Unit
-40°C ÷
125°C
min
max
min
max
min
max
VIH
High-Level Input
Voltage
1.2
2.0
3.0
3.6
0.9
1.4
2.1
2.5
-
0.9
1.4
2.1
2.5
-
0.9
1.4
2.1
2.5
-
V
VIL
Low -Level Input
Voltage
1.2
2.0
3.0
3.6
-
0.3
0.6
0.9
1.1
-
0.3
0.6
0.9
1.1
-
0.3
0.6
0.9
1.1
V
VOH
High-Level Output VI = VIL or VIH
Voltage
IO = -50 µÀ
1.2
2.0
3.0
3.6
1.1
1.92
2.92
3.52
-
1.0
1.9
2.9
3.5
-
1.0
1.9
2.9
3.5
-
V
VI = VIL or VIH
IO = -6.0 mÀ
3.0
2.48
-
2.34
-
2.20
-
V
Low-Level Output VI = VIL or VIH
Voltage
IO = 50 µÀ
1.2
2.0
3.0
3.6
-
0.09
0.09
0.09
0.09
-
0.1
0.1
0.1
0.1
-
0.1
0.1
0.1
0.1
V
VI = VIL or VIH
IO = 6.0 mÀ
3.0
-
0.33
-
0.4
-
0.5
V
VOL
IIL
Low-Level Input
Leakage Current
VI = 0 V
3.6
-
-0.1
-
-1.0
-
-1.0
µA
IIÍ
High-Level Input VI = VCC
Leakage Current
3.6
-
0.1
-
1.0
-
1.0
µA
IÑÑ
Quiescent Supply VI = 0 Â or VCC
Current
IO = 0 µÀ
(per Package)
3.6
-
2.0
-
20
-
40
µA
SLS
System Logic
Semiconductor
3
SL74LV32
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t LH = t HL = 6.0 ns, VIL = 0V, VIH=VCC, RL=1k )
Symbol
Parameter
Guaranteed Limit
VCC
V
25°C
Unit
-40°C ÷ 85°C
-40°C ÷ 125°C
min
max
min
max
min
max
tTHL, (t TLH)
Output Transition
Time, Any Output
(Figure 1)
1.2
2.0
*
-
60
16
10
-
75
20
13
-
90
24
15
tPHL, (t PLH)
Propagation Delay,
Input A to Output Y
(Figure 1)
1.2
2.0
*
-
125
20
12
-
360
25
15
-
360
30
18
Input Capacitance
3.0
-
7.0
-
-
-
-
CI
CPD
Power Dissipation Capacitance (Per Gate)
ns
pF
ÒÀ=25°Ñ, VI=0V÷VCC
pF
44
tL H
tHL
0.9
Input À, B
V
VC C
0.9
V
1
1
0.1
0.1
tP LH
0.9
V
Output Y
GND
tP H L
V OH
0.9
V
1
0.1
1
0.1
tT LH
V OL
TT HL
V 1 = 0.5 V CC
* - VCC= (3.3±0.3) V
PD = CPDVCC2fI+ (CLVCC2fo), fI-input frequency, fo- output frequency (MHz)
(CLVCC2fo) – sum of the outputs
Figure 1. Switching Waveforms
VC C
VI
VO
DEVICE
UNDER
PULSE
GENERATOR
RT
SLS
System Logic
Semiconductor
TEST
CL
RL
Termination resistance RT should be equal to ZOUT pulse
generators
4
SL74LV32
Figure 2. Test Circuit
SLS
System Logic
Semiconductor
5
SL74LV32
CHIP PAD DIAGRAM SL74LV32
12
11
10
08
13
1.20 ±0.0 3
09
Chip marking
25LV32
(x=1.009; y=0.727)
14
07
01
02
06
04
03
05
1.23 ±0.03
Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer)
Thickness of chip 0.46 ± 0,02 mm
PAD LOCATION
Pad No
Symbol
X
Y
01
02
03
04
05
06
07
08
09
10
11
12
13
14
A1
B1
Y1
A2
B2
Y2
GND
Y3
A3
B3
Y4
A4
B4
Vcc
0.111
0.111
0.504
0.672
1.009
1.009
1.009
1.009
1.009
0.672
0.504
0.336
0.111
0.111
0.287
0.119
0.111
0.111
0.111
0.277
0.447
0.806
0.974
0.974
0.974
0.974
0.772
0.618
SLS
System Logic
Semiconductor
6