TECHNICAL DATA IN74LV640 Octal 3-State Inverting Bus Transceiver The 74LV640 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT640. The 74LV640 provides six inverting buffers with Schmitt-trigger action. • • • • Wide Operating Voltage: 1.2 to 3.6 V Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low input current ORDERING INFORMATION IN74LV640N Plastic IN74LV640D SOIC IZ74LV640 Chip TA = -40° to 125° C for all packages PIN ASSIGNMENT DIR 01 LOGIC DIAGRAM DIR OE A3 04 17 B2 16 B3 640 B4 14 B5 18 A7 08 13 B6 17 A8 09 12 B7 GND 10 11 B8 A3 B3 05 B1 15 A2 B2 04 18 A6 07 A1 B1 03 A2 03 A5 06 19 VCC 19 OE A4 05 01 02 20 A1 02 16 A4 B4 06 A5 07 A6 08 A7 B5 B6 B7 A8 Inputs 14 13 Inputs/Outputs OE DIR À Â L L A=B input L H input B=A H X Z Z 12 09 B8 FUNCTION TABLE 15 11 PIN 20=VCC PIN 10 = GND 1 IN74LV640 MAXIMUM RATINGS * Symbol Parameter VCC DC supply voltage (Referenced to GND) IIK* 1 Value Unit -0.5 ÷ +5.0 V DC input diode current ±20 mA 2 DC output diode current ±50 mA 3 DC output source or sink current -bus driver outputs ±35 mA DC GND current for types with - bus driver outputs ±70 mA ICC DC VCC current for types with - bus driver outputs ±70 mA PD Power dissipation per paskade, plastic DIP+ SOIC package+ 750 500 mW -65 ÷ +150 °C 260 °C IOK* Io* IGND Tstg TL Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/°C from 65° to 125°C SOIC Package: : - 8 mW/°C from 65° to 125°C * 1: VI < -0.5V or VI > VCC+0.5V * 2: Vo < -0.5V or Vo > VCC+0.5V * 3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tLH, t HL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Min Max Unit 1.2 3.6 V 0 VCC V -40 +125 °C 0 1000 700 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74LV640 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter VIH High-Level Input Voltage VIL Low -Level Input Voltage VOH High-Level Output Voltage Guaranteed Limit Test Conditions VCC VO = VCC0.1 V 1.2 2.0 3.0 3.6 0.9 1.4 2.1 2.5 max - 1.2 2.0 3.0 3.6 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 V 1.2 2.0 3.0 3.6 1.1 1.92 2.92 3.52 - 1.0 1.9 2.9 3.5 - 1.0 1.9 2.9 3.5 - V 3.0 2.48 - 2.34 - 2.20 - 1.2 2.0 3.0 3.6 - 0.09 0.09 0.09 0.09 - 0.1 0.1 0.1 0.09 - 0.1 0.1 0.1 0.09 3.0 - 0.33 - 0.40 - 0.50 VI = VIH –or VIL IO = -50 µA VI = VIH –or VIL V 25°C min -40°C ÷ 85°C min max 0.9 1.4 2.1 2.5 Unit -40°C ÷ 125°C min max 0.9 1.4 2.1 2.5 V IO = -8.0 mA VOL Low-Level Output Voltage VI = VIH –or VIL IO = 50 µA VI = VIH –or VIL V IO = 8.0 mA IIL Low-Level Input Leakage Current VI=0 V * - -0.1 - -1.0 - -1.0 µA IIH High-Level Input Leakage Current VI= VÑÑ * - 0.1 - 1.0 - 1.0 µA IOZ Maximum ThreeState Leakage Current VI= VIL or VIH VO=VCC or GND 1.2 * - ±0.5 - ±5.0 - ±10 µA ICC Quiescent Supply Current (per Package) VI=0 V or VÑÑ * - 8.0 - 80.0 - 180.0 µA IO = 0 µA . 3 IN74LV640 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t LH =t HL = 6.0 ns, RL=1 k? ) Guaranteed Limit Test Conditions VCC 1.2 2.0 * min - max VIL=0 V VIH=VCC tLH = tHL =6.0 ns ÑL = 50 pF VIL=0 V VIH=VCC tLH = tHL =6.0 ns ÑL = 50 pF VIL=0 V VIH=VCC tLH = tHL =6.0 ns ÑL = 50 pF VIL=0 V VIH=VCC tLH = tHL =6.0 ns ÑL = 50 pF 1.2 2.0 * - 120 30 20 - 140 37 24 - 160 43 28 ns 1.2 2.0 * - 120 28 17 - 140 35 21 - 160 43 26 ns 1.2 2.0 * - 60 16 10 - 75 20 13 - 90 24 15 ns Input Capacitance (Pin 1 or Pin 19) 3.0 - 7.0 - - - - pF Input Capacitance (Pin 2-9 or Pin 11-18) 3.0 - 20.0 - - - - pF - 50 - - - - pF Symbol Parameter tPLH, t PHL Propagation Delay, A to B , B to A tPLZ, t PHZ Propagation Delay , Direction or Output Enable to A or B tPZL, t PZH Propagation Delay , Direction or Output Enable to A or B tTLH, t THL Output Transition Time, Any Output CI CI/O CPD V VI=0 V or VÑÑ 25°C 100 23 14 -40°C ÷ 85°C min max 125 28 18 Unit -40°C ÷ 125°C min max 140 34 21 ns * - VCC=3.3±0.3V t HL VC C t LH 0.9 VCC 0.9 V1 0.1 0.1 t PHL VO GND RT DEVICE UNDER TEST RL CL t PLH 0.9 0.9 V1 B (A) VI PULSE GENERATOR V1 0.1 t THL V1 0.1 t TLH Figure 1. Switching Waveforms V CC Termination resistance RT – should be equal to ZOUT of pulse generators Figure 2. Test Circuit 4 IN74LV640 CHIP PAD DIAGRAM IZ74LV640 Chip marking ÊÁLV640 (X=2.010;Y=1.810) 18 17 16 15 14 13 12 20 11 1.99 +0.03 19 10 01 09 02 03 04 05 06 07 08 2.30 ±0.03 Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 ± 0,02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 Symbol DIR A1 A2 A3 A4 A5 A6 A7 A8 GND B8 B7 B6 B5 B4 B3 B2 B1 20 VCC OE X 0.140 0.140 0.370 0.790 1.000 1.200 1.417 1.833 2.060 2.060 2.060 2.060 1.833 1.415 1.000 0.790 0.580 0.370 0.140 Y 0.573 0.315 0.140 0.140 0.140 0.140 0.140 0.140 0.354 0.760 1.340 1.520 1.750 1.750 1.750 1.750 1.750 1.750 1.544 0.140 1.375 5