TECHNICAL DATA SL74LVU04 Hex Inverter N SUFFIX PLASTIC The 74LVU04 is a low-voltage, Si-gate CMOS device and is pin compatible with the 74HCU04. The 74LVU04 is a general purpose hex inverter. Each of the six inverters is a single stage with unbuffered outputs. • • • • 14 1 D SUFFIX SOIC 14 1 Wide Operating Voltage: 1.0÷5.5 V Optimized for Low Voltage applications: 1.0÷3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low Input Current LOGIC DIAGRAM ORDERING INFORMATION SL74LVU04N Plastic SL74LVU04D SOIC SL74LVU04 Chip TA = -40° ÷ 125° C for all packages PIN ASSIGNMENT FUNCTION TABLE Input Output A Y L H H L PIN 14 =VCC PIN 7 = GND SLS System Logic Semiconductor 1 SL74LVU04 MAXIMUM RATINGS * Symbol VCC IIK * DC supply voltage (Referenced to GND) Value Unit -0.5 ÷ +7.0 V 1 DC input diode current ±20 mA 2 DC output diode current ±50 mA DC output source or sink current -bus driver outputs ±25 mA DC VCC current for types with - bus driver outputs ±50 mA DC GND current for types with - bus driver outputs ±50 mA Power dissipation per package, plastic DIP+ SOIC package+ 750 500 mW -65 ÷ +150 °C 260 °C IOK * IO * Parameter 3 ICC IGND PD Tstg Storage temperature TL Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SOIC Package: : - 8 mW/°C from 70° to 125°C * 1: VI < -0.5V or VI > VCC+0.5V * 2: Vo < -0.5V or Vo > VCC+0.5V * 3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time 1.0 V≤VCC <2.0 V 2.0 V≤VCC <2.7 V 2.7 V≤VCC <3.6 V 3.6 V≤VCC ≤5.5 V Min Max Unit 1.0 5.5 V 0 VCC V -40 +125 °C 0 0 0 0 500 200 100 50 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor 2 SL74LVU04 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions Guaranteed Limit VCC, V 25°C min max -40°C ÷ 85°C -40°C ÷ 125°C min min max max VIH High-Level Input Voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.0 1.6 2.4 2.4 2.4 3.6 4.4 VIL Low -Level Input Voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.2 0.4 0.5 0.5 0.5 0.9 1.1 - 0.2 0.4 0.5 0.5 0.5 0.9 1.1 - 0.2 0.4 0.5 0.5 0.5 0.9 1.1 V VOH High-Level Output Voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.05 1.85 2.55 2.85 3.45 4.35 5.35 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - V 2.48 - 2.40 - 2.20 - 4.5 3.70 - 3.60 - 3.50 - VI = VIH or VIL I0=100 ìA 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.15 0.15 0.15 0.15 0.15 0.15 0.15 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 VI = VIH or VIL I0=6.0 mA 3.0 - 0.33 - 0.40 - 0.50 VI = VIH or VIL I0=12 mA 4.5 - 0.40 - 0.55 - 0.65 VI=0 V 5.5 - -0.1 - -1.0 - -1.0 VI = VIH or VIL I0=-100 ìA VI = VIH or VIL I0=-6.0 mA VI = VIH or VIL I0=-12 mA VOL IIL Low-Level Output Voltage Low-Level Input Leakage Current 3.0 1.0 1.6 2.4 2.4 2.4 3.6 4.4 Unit 1.0 1.6 2.4 2.4 2.4 3.6 4.4 V V ìA DC ELECTRICAL CHARACTERISTICS (continuation) Symbol SLS Parameter System Logic Semiconductor Test Conditions Guaranteed Limit VCC, 25°C -40°C ÷ 85°C Unit -40°C ÷ 125°C 3 SL74LVU04 V min max min max min max IIH High-Level Input Leakage Current VI= VÑÑ 5.5 - 0.1 - 1.0 - 1.0 ICC Quiescent Supply Current (per Package) VI=0 Â or VÑÑ 5.5 - 4.0 - 20 - 40 ìA Additional Quiescent Supply Current on input VI = VÑÑ - 0.6V 2.7 3.6 - 0.2 0.2 - 0.5 0.5 - 0.85 0.85 mA ICC1 IO = 0 ìA - AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t LH =t HL = 2.5 ns, RL=1 kÙ) Symbol tPHL (t PLH) CI CPD Parameter Propagation Delay, Input A to Output Y (Figure 1 ) Input Capacitance Test Conditions VI=0 V or V1 tLH = tHL =2.5 ns Ñ L = 50 pF RL = 1 kÙ Guaranteed Limit VCC V -40°C ÷ 85°C 25°C -40°C ÷ 125°C Unit Min max min max min max 1.2 2.0 2.7 3.0 4.5 - 70 22 16 13 11 - 80 26 19 15 13 - 100 31 23 18 16 ns 5.5 - 7.0 - - - - pF Power Dissipation Capacitance (Per Inverter) Ò À=25°Ñ, VI=0V or VCC pF 36 Used to determine the no-load dynamic power consumption: PD = CPDVCC2fI+ (CLVCC2fo), fI - input frequency, fo - output frequency (MHz) (CLVCC2fo) – sum of the outputs SLS System Logic Semiconductor 4 SL74LVU04 tH L tL H Input À VX 0.1 V1 0.9 0.9 VX 0.1 tP HL GND tP LH VOH Output Y VY VY VOL VX=0.5 VCC Figure 1. Switching Waveforms VC C VI PULSE GENERATOR Termination resistance RT – should be equal to ZOUT of pulse generators VO RT DEVICE UNDER TEST CL RL Figure 2. Test circuit SLS System Logic Semiconductor 5 SL74LVU04 CHIP PAD DIAGRAM SL74LVU04 1.33 ±0.03 1.42 ± 0.03 13 12 11 10 09 08 14 07 01 02 03 04 05 06 Chip marking IN74LVU04 (x=0.130; y=0.130) Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 ± 0,02 mm PAD LOCATION Pad No Symbol X Y 01 02 03 04 05 06 07 08 09 10 11 12 13 14 A1 Y1 A2 Y2 A3 Y3 GND Y4 A4 Y5 A5 Y6 A6 VCC 0.130 0.130 0.381 0.616 0.881 1.116 1.115 1.115 1.115 0.804 0.569 0.378 0.143 0.130 0.463 0.230 0.126 0.126 0.126 0.126 0.631 0.846 1.181 1.194 1.194 1.194 1.194 0.813 SLS System Logic Semiconductor 6