CXA2161R I2C Bus Compatible Audio Video (AV) Switch & Electronic Volume Control Description The Sony CXA2161R is an Audio/Video switch designed primarily for application in Digital Set Top Boxes. It provides video and audio routing from the digital encoder source to the TV and VCR scart (peritelevision) connectors. In addition, the TV audio output has a programmable volume control. The chip is programmed by means of an I2C interface and can operate from a single or dual power supply. Target specifications: Canal+, BSkyB, TPS, NorDig, and ECCA Euro-Box Features Supply • Single: 0V, +5V, +12V • Dual: 0V, –5V, +5V and +12V (Low number of external parts required) Video • 2 scart switching (VCR, TV) • VCR input supports RGB mode • Integrated 75Ω drivers for direct video connection • Y/C mixer with trap for RF modulators • Switchable clamps on inputs • Adjustable gain on RGB outputs • Video output shutdown for low power modes • Fast blanking switch • Slow blanking switch for TV and VCR output • SVHS switch on VCR output • Y/C auxiliary input Audio • Four stereo audio inputs • Volume control (–56dB to +6dB in 2dB steps) • Additional switchable gain on audio DAC inputs • Audio overlay facility • Volume bypass for TV and Phono outputs • Mono switching on TV, VCR outputs • High drive capability (600Ω loads possible) • Switchable audio limiter function • Switchable Mono output for RF modulators • Audio output disable 56 pin LQFP (Plastic) I2C and Logic • Fast mode compatible I2C bus • Function monitor with loop through • Interrupt output for function monitor • Logic output pin • Sync detector for Y/CVBS inputs Applications • Digital Set Top Box • Integrated digital television Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C) unless stated • Supply voltage VCC 14 V • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1.1 W (when mounted on the board) Operating Conditions • Single supply • Dual supply • Operating temperature Topr 12 ± 0.6 5 ± 0.25 –5 ± 0.25 5 ± 0.25 12 ± 0.6 –20 to +75 V V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00202-PS CXA2161R Block Diagram (1) Video and Digital Section Typical Connection ↓ Typical Connection ↓ FBLK_SW +3.5V 0V DIG FBLK_IN1 10 VCR FBLK_IN2 12 9 TV_FBLK VIDEO SWITCH1 (TV) DIG BLUE VIN_1 50 DC Restore VCR BLUE VIN_2 7 DC Restore DIG GREEN/CVBS VIN_3 51 VCR GREEN VIN_4 DIG RED/CHROMA VIN_5 52 DC Restore/C bias DIG CHROMA VIN_6 53 C bias VCR RED/CHROMA VIN_7 5 VIN_13 1 6 ×2 Output disable 47 VOUT_1 TV BLUE ×2 Output disable 46 VOUT_2 TV GREEN DC Restore/Tip DC Restore TV AUX CHROMA Output disable 45 VOUT_3 TV RED/C Output disable 43 VOUT_4 TV CVBS/Y Output disable & Bi-drection Control 41 VOUT_5 VCR CHROMA ×2 DC Restore/C bias RGB Gain Control (+1, 2, 3dB) C bias Clamp Cntl DIG CVBS/LUMA VIN_8 54 Tip DIG CVBS/LUMA VIN_9 55 Tip VCR CVBS/LUMA VIN_10 4 Tip TV CVBS VIN_11 3 Tip AUX Y/CVBS VIN_12 56 Tip ×2 MIX_SW SYNC_ID 2 Sync Detect ×2 AUD_BIAS 18 VID_BIAS 49 VCR +5V/12V_VCCA 24 –5V_GNDA 21 +5V_DIG 14 GND_DIG Output disable ×2 8 39 VOUT_6 VCR CVBS/Y +5V_VOUT 44 GND_VID 40 37 TRAP +5V_VID 48 Bias +12V_DIG 15 Mute ×2 VIDEO SWITCH2 (VCR) 38 VOUT_7 (CVBS) RF MOD MIX_SW SDA 34 0/6/12V 11 FNC_TV SCL 35 VCR FNC_VCR 13 TV 0/6/12V Monitor 3.3V or 5V Fast Mode Compatible Interrupt Control 36 INTRUPT MICRO Logic Note) All video outputs contain 75Ω drivers, except VOUT_7 (Pin 38). –2– 33 LOGIC 22 19 LIN_1 (DIG) LIN_2 (VCR) 29 42 RIN_4 (AUX) 16 17 RIN_3 (TV/OVERLAY) LIN_4 (AUX) 20 RIN_2 (VCR) LIN_3 (TV/OVERLAY) 23 RIN_1 (DIG) (2) Audio section –6dB –6dB –6dB –6/–3/0/+3dB –6dB –6/–11dB –6dB –6/–3/0/+3dB Tone mix –16dB Overlay on/off –16dB Overlay on/off Bias Mute 2dB Limiter 2.2Vrms Limiter 2.2Vrms Volume Control +6 to –56dB ZCD 2dB AUDIO SWITCH2 (VCR) AUDIO SWITCH1 (TV) –3– Mono and R/L Switch Vol Bypass (Phono) Vol Bypass (TV) Vol Bypass (TV) Vol Bypass (Phono) Mono and R/L Switch Mono Switch MONO To RF Modulator 28 ROUT1 27 LOUT1 6dB Output Disable TV VCR 30 PHONO_L 25 LTV 26 RTV 31 PHONO_R 32 6dB 6dB 6dB 6dB 6dB 6dB CXA2161R CXA2161R RIN_4 VOUT_5 GND_VID VOUT_6 VOUT_7 TRAP INTRUPT SCL SDA LOGIC MONO PHONO_R PHONO_L LlN_4 Pin Configuration 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VOUT_4 43 28 ROUT1 +5V_VOUT 44 27 LOUT1 VOUT_3 45 26 RTV VOUT_2 46 25 LTV VOUT_1 47 24 +5V/12V_VCCA +5V_VID 48 23 RIN_1 VID_BIAS 49 22 LIN_1 VIN_1 50 21 –5V_GNDA VIN_3 51 20 RIN_2 VIN_5 52 19 LIN_2 VIN_6 53 18 AUD_BIAS VIN_8 54 17 RIN_3 VIN_9 55 16 LIN_3 15 +12V_DIG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VIN_13 SYNC_ID VIN_11 VIN_10 VIN_7 VlN_4 VIN_2 GND_DIG TV_FBLK FBLK_IN1 FNC_TV FBLK_IN2 FNC VCR +5V_DIG VIN_12 56 –4– CXA2161R Pin Description Pin No. Symbol Pin voltage [V] Equivalent circuit Description VCC 50 7 6 VIN_1 VIN_2 VIN_4 6 2.4 150 RGB signal inputs 150 RGB signal input or CVBS/Luminance signal input 7 50 VCC 2.4 51 VIN_3 51 2.35 VCC 2.4 52 5 RGB signal inputs or Chrominance signal inputs 20k VIN_5 VIN_7 150 5 3.0 52 VCC 53 1 VIN_6 VIN_13 20k 150 3.0 Chrominance signal inputs 1 53 VCC 54 55 4 3 56 VIN_8 VIN_9 VIN_10 VIN_11 VIN_12 47 46 45 43 39 VOUT_1 VOUT_2 VOUT_3 VOUT_4 VOUT_6 2.35 54 55 150 CVBS/Luminance signal inputs 43 RGB/CVBS signal outputs (See description of operation for pin voltages) 3 4 56 VCC — 45 47 12k –5– 39 46 CXA2161R Pin No. Symbol Pin voltage [V] Equivalent circuit Description VCC 41 VOUT_5 1.8 Chrominance signal output 41 12k VCC 38 VOUT_7 0.4 38 0.75mA 12k VCC VCC 40.8k 49 VID_BIAS 0.9 Typically RF modulator signal output Minimum load resistance = 20kΩ 150 49 18.3k Internal reference bias for video circuits. A capacitor is connected from this pin to GND. Typically 100nF VCC 2k 37 TRAP 2.3 200 Connects trap circuit for subcarrier 37 VCC 2 SYNC_ID 22 23 19 20 16 17 29 42 LIN_1 RIN_1 LIN_2 RIN_2 LIN_3 RIN_3 LIN_4 RIN_4 2.5 150 Sync detect circuit time constant, resistor and capacitor connection pin 2 VCC 6.0 (Single) VCC/2 22 16 23 17 0.0 (Dual) 60k 60k 29 19 42 20 –6– Audio signal inputs CXA2161R Pin No. Symbol 25 26 27 28 30 31 32 LTV RTV LOUT1 ROUT1 PHONO_L PHONO_R MONO Pin voltage [V] Equivalent circuit VCC 6.0 (Single) 25 20k 26 0.0 (Dual) 27 28 VCC 6.0 (Single) 18 Description 30 32 Capacitor connected to GND. Internal reference (Typically 22µF) bias for audio circuits. Connected directly to GND. VCC 40k 150 AUD_BIAS 18 0.0 (Dual) Audio signal outputs 31 40k VCC 10 12 FBLK_IN1 FBLK_IN2 — 150 Fast blanking signal inputs 10 12 VCC 9 TV_FBLK — 13 FNC_VCR — 9 Fast blanking signal output SCART function pin 8 input/output to VCR 13 120k VCC 11 FNC_TV — 11 –7– SCART function pin 8 output to TV CXA2161R Pin No. Symbol Pin voltage [V] Equivalent circuit Description VCC 33 36 LOGIC INTRUPT — 33 36 35 SCL — 8k Open collector logic outputs Typically connect to +5V through 10kΩ resistor. I2C bus clock line 34 35 I2C bus data line 34 SDA 14 +5V_DIG 44 +5V_VOUT 48 +5V_VID 15 +12V_DIG 12.0 21 –5V_GNDA –5.0 (Dual) 0.0 (Single) Audio supply or Audio ground 24 +5V/+12V_VCCA 5.0 (Dual) 12.0 (Single) Audio supply 8 GND_DIG 0.0 Digital ground 40 GND_VID 0.0 Video ground — Digital supply Video output supply 5.0 Video supply Digital supply –8– CXA2161R Electrical Characteristics Nominal conditions (Ta = 25°C) Item Symbol Current consumption (Single ended supply) Current consumption (Dual supply) Conditions Min. Typ. Max. Unit ICC1 +12 supply, no signal, no load — 22 45 mA ICC2 +5 supply, no signal, no load — 50 80 mA ICC3 +12 supply, no signal, no load — 2 6 mA ICC4 +5 supply, no signal, no load — 70 115 mA ICC5 –5 supply, no signal, no load — 20 45 mA Video System Nominal conditions single supply (Ta = 25°C, +5V/12V_VCCA = +12V, –5V_GNDA = 0V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V) Item Symbol Sync tip clamp voltage at input Vclmp1 Min. Typ. Max. Unit Vin3, Vin8, Vin9, Vin10, Vin11, Vin12 inputs. (Vin3 set to CVBS mode) (Fig. 1) — 2.4 — V Cbias1 Vin5, Vin7 inputs. Clamps set to Chrominance bias mode. (Fig. 1) — 3 — V Cbias2 Vin6, Vin13 inputs. (Fig. 1) — 2.35 — V RGB dc restore input voltage RGB1 Vin1, Vin2, Vin3, Vin4, Vin5, Vin7 inputs. (Vin3 & Vin5 set to RGB mode) (Fig. 1) — 2.4 — V Sync tip clamp voltage at output Vclmp2 Vout4, Vout6 outputs (Fig. 1) — 0.3 — V Chrominance bias output voltage Cbias3 Vout3, Vout5 outputs (Fig. 1) — 1.8 — V RGB dc restore output voltage RGB2 Vout1, Vout2, Vout3 outputs (Fig. 1) — 0.6 — V Gain (Vout1 to 6) GVv f = 200kHz, 0.3Vp-p input , RGB Gain = 0dB (Fig. 2) 5.5 6.0 6.5 dB GVRGB1 f = 200kHz, 0.3Vp-p input , RGB Gain = +1dB (Fig. 2) 6.5 7.0 7.5 dB GVRGB2 f = 200kHz, 0.3Vp-p input , RGB Gain = +2dB (Fig. 2) 7.5 8.0 8.5 dB GVRGB3 f = 200kHz, 0.3Vp-p input , RGB Gain = +3dB (Fig. 2) 8.5 9.0 9.5 dB Gain (Vout7) Mixer off GVYC f = 200kHz, 0.3Vp-p input (Fig. 2) 5.5 6.0 6.5 dB Gain (Vout7) Mixer on GVYC f = 200kHz, 0.3Vp-p input (Fig. 2) 5.5 5.75 6.5 dB Bandwidth (Vout1 to 6) fV3dB 0.3Vp-p input, frequency where output level is –3dB with 200kHz serving as 0dB (Fig. 2) 15 22 — MHz Bandwidth (Vout7) Mixer on – No trap components fV3dB 0.3Vp-p input, frequency where output level is –3dB with 200kHz serving as 0dB (Fig. 2) 8 18 — MHz Input dynamic range VDRVI 200kHz input applied to any video (Fig. 2) 1.4 — — Vp-p Output dynamic range VDRVO 200kHz input applied to any video (Fig. 2) 2.8 — — Vp-p Chrominance bias input voltage Gain (Vout1, 2, 3) Conditions –9– CXA2161R Item Symbol Conditions Min. Typ. Max. Unit f = 4.43MHz, 1Vp-p input (Fig. 2) — — –50 dB S/N ratio S/NV Ratio of 0.7Vp-p white video signal to black line noise. Weighted using CCIR 567. HPF@5kHz, LPF@5MHz. (Fig. 2) — 74 — dB Non-linearity Lin –3 0 3 % V1 V2 Vctv Input pin V plus Cross talk V1 = Pin voltage + 0.5V, V2 = Pin voltage + 1V V2 At output, non-linearity = –1 × 100 V1 × 2 (Fig. 2) Differential gain DG 1.7Vp-p 5-step modulated staircase. (Chrominance & Burst are 150mVp-p, 4.43MHz) (Fig. 2) –3 0 3 % Differential phase DP As above. –3 0 3 deg Audio System Unless otherwise stated: input coupling capacitor 1µF; output coupling capacitor 10µF; load 10kΩ. Nominal conditions single supply (Ta = 25°C, +5V/12V_VCCA = +12V, –5V_GNDA = 0V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V) Nominal conditions dual supply (Ta = 25°C, +5V/12V_VCCA = +5V, –5V_GNDA = –5V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V) Item Symbol Conditions Min. Typ. Max. Unit Input/output pin voltage (Single supply) VAPIN1 No signal, no load (Fig. 3) — 6 — V Input/output pin voltage (Dual supply) VAPIN2 No signal, no load (Fig. 3) — 0 — V Output pin voltage when disabled (Dual supply) VAPIN3 No signal, no load (Fig. 3) — 0 — V Gain Input Output Rin1 or Lin1 TV or Phono GVA1 f = 1kHz, 0.5Vrms input. TV volume set to –0.5 0dB, RIN_1/LIN_1 amplifier = –6dB (Fig. 4) 0 0.5 dB Rin1 or Lin1 TV or Phono GVA2 f = 1kHz, 0.5Vrms input. TV volume set to 0dB, RIN_1/LIN_1 amplifier = –3dB (Fig. 4) 2.5 3 3.5 dB Rin1 or Lin1 TV or Phono GVA3 f = 1kHz, 0.5Vrms input. TV volume set to 0dB, RIN_1/LIN_1 amplifier = 0dB (Fig. 4) 5.5 6 6.5 dB Rin1 or Lin1 TV or Phono GVA4 f = 1kHz, 0.5Vrms input. TV volume set to 0dB, RIN_1/LIN_1 amplifier = +3dB (Fig. 4) 8.5 9 9.5 dB Rin1 or Lin1 VCR GVA5 f = 1kHz, 1Vrms input. TV volume set to –0.5 0dB, RIN_1/LIN_1 amplifier = –6dB (Fig .4) 0 0.5 dB – 10 – CXA2161R Item Symbol Conditions Min. Typ. Max. Unit Rin1 + Lin1 TV GVA6 (mono mix) f = 1kHz, 0.5Vrms stereo input. TV volume set to 0dB, RIN_1/LIN_1 amplifier = –6dB. –0.5 TV mono switch on. (Fig. 4) 0 0.5 dB Rin1 + Lin1 MONO GVA7 f = 1kHz, 1Vrms stereo input. TV volume set to 0dB, RIN_1/LIN_1 amplifier = –6dB. –0.5 (Note 1) (Fig. 4) 0 0.5 dB Rin2, 3, 4 or Lin2, 3, 4 TV or Phono GVA9 f = 1kHz, 1Vrms input, TV volume set to 0dB (Fig. 4) –0.5 0 0.5 dB Rin1 + Lin1 VCR GVA8 (mono mix) f = 1kHz, 1Vrms stereo input. RIN_1/LIN_1 amplifier = –6dB. VCR mono switch on. –0.5 (Fig 4) 0 0.5 dB Rin2 + Lin2 Rin3 + Lin3 Rin4 + Lin4 MONO GVA10 f = 1kHz, 1Vrms stereo input. TV volume set to 0dB (Note 2) (Fig 4) –0.5 0 0.5 dB Rin2, 3, 4 Lin2, 3, 4 VCR GVA11 f = 1kHz, 1Vrms input (Fig 4) –0.5 0 0.5 dB Rin2 + Lin2 Rin3 + Lin3 Rin4 + Lin4 VCR GVA12 (mono mix) f = 1kHz, 1Vrms stereo input. VCR mono switch on. (Fig 4) –0.5 0 0.5 dB Rin3 RTV, ROUT1, Phono_R GVA13 f = 1kHz, 1Vrms input, Lin3 has no signal Audio overlay enabled with –11dB attenuation at input RIN_3 (Fig 4) –5.5 –5 –4.5 dB Lin3 LTV, LOUT1, Phono_L GVA14 f = 1kHz, 1Vrms input Audio overlay enabled. (Fig 4) –0.5 0 0.5 dB Audio frequency response FAF 0.3Vp-p input. Output/input gain at 30kHz with 1kHz serving as 0dB (Fig 4) –0.3 0 0.3 dB Frequency bandwidth FBWA1 0.3Vp-p input; frequency where output level is –3dB with 1kHz serving as 0dB. No load attached (Fig 4) — 1 — MHz Distortion THD f = 1kHz, 0.5Vrms, unweighted response; LPF@400Hz, HPF@80kHz (Fig 4) — 0.005 0.2 % Input dynamic range Rin1, 2, 3, 4/Lin1, 2, 3, 4 VdA1 f = 1kHz, RIN_1/LIN_1 input amplifier set to –6dB. Dual supply mode used. (Fig 4) 2.5 2.9 — Vrms Cross talk (Channel separation) VctA f = 1kHz, 1Vrms input on one input, measure on any other audio output (Fig 4) — — –76 dB DC offset Voff Offset voltage between input and output –30 0 30 mV Input impedance Rin1, 2, 3, 4/Lin1, 2, 3, 4 Zin1 (excluding any external series resistor) — 120 — kΩ Output impedance Zout (excluding any external series resistor) — 10 — Ω Phase difference Vpda f = 1kHz, 1Vrms input to two channels. Phase difference of stereo output measured — 0.05 — deg S/N ratio S/NA f = 1kHz, 1Vrms input (at 0dB volume). HPF@20Hz, LPF@20kHz. (Fig 4) 80 93 — dB Note 1) Mono switch set to mix of Rin1 & Lin1 inputs. Note 2) Mono switch set to mix of RTV & LTV after volume control. – 11 – CXA2161R Item Symbol Conditions Min. Typ. Max. Unit Electronic Volume Control Volume attenuation step AEVC f = 1kHz, 0.5Vrms input. Set by I2C (Fig 4) 1.6 2 2.4 dB Mute TV I/P MUTE or VCR I/P MUTE Amute f = 1kHz, 1Vrms input (Fig 4) — –90 –76 dB Audio limiter level Alimit f = 1kHz, 2.5Vrms input. Measure TVp-p output with limiter switched on. (Fig 4) — 6.5 — Vp-p Digital Characteristics I2C Interface The I2C interface is compliant with Philips I2C Fast Mode specification (date April 1995). The interface is also capable of interfacing to +3.3V or +5V logic levels. Item Symbol Condition Min. Typ. Max. Unit High level input voltage VIH 2.3 — 5.5 V Low level input voltage VIL 0 — 1.5 V Low level output voltage VOL With SDA, 3mA current supplied 0 — 0.4 With SDA, 6mA current supplied 0 — 0.6 Hysteresis of schmitt trigger input VHYST VIH – VIL — 0.5 — V Spike suppression tSP — — 50 ns Fall time for SDA line tF 400pF bus load — — 300 ns SCL clock frequency tSCL I2C Bus line requirement 0 — 400 kHz Bus free time between a stop and start tBUF I2C Bus line requirement 1.3 — — µs Hold time (repeated start condition) tHD;STA I2C Bus line requirement 0.6 — — µs Low period of SCL clock tLOW I2C Bus line requirement 1.3 — — µs High period of SCL clock tHIGH I2C Bus line requirement 0.6 — — µs Setup time for a repeated start condition tSU;SDA I2C Bus line requirement 0.6 — — µs Data hold time tHD;DAT I2C Bus line requirement 0 — 0.9 µs Data setup time tSU;DAT I2C Bus line requirement 100 — — ns Setup time for stop condition tSU;STO I2C Bus line requirement 0.6 — — µs tBUF tR tF tHD;STA tHD;STA P S tLOW tSU;DAT tHIGH tSU;DAT – 12 – tSU;STA tSU;STO Sr P V CXA2161R Logic/Interrupt Output These outputs are open collector type and normally connected to +5V through a 10kΩ resistor. Item Output low voltage Symbol DIGVOUTL Conditions IOL = 1mA – 13 – Min. Typ. Max. Unit — 0.15 0.4 V CXA2161R Output Measurement Point V I2C SCL SDA 42 41 40 39 38 37 36 35 34 33 32 31 30 29 +5V +5V 100nF 75Ω 100nF 75Ω 100nF 48 23 49 22 50 21 51 20 52 19 53 18 54 17 55 16 56 15 1 2 3 4 5 6 7 8 9 +12V 1µF +12V 10 11 12 13 14 +5V Input Measurement V Point 100nF 68kΩ 75Ω 100nF +5V 100nF 100nF 24 75Ω 75Ω 47 100nF 100nF 25 75Ω 75Ω 46 100nF 100nF 26 75Ω 75Ω 45 100nF 100nF 27 75Ω 75Ω 44 100nF 100nF 28 75Ω 75Ω 43 Fig. 1. Video System (DC Test) DC measured from Pins 1, 3, 4, 5, 6, 7, 38, 39, 41, 43, 45, 46, 47, 50, 51, 52, 53, 54, 55, 56 Notes) 1. All supplies de-coupled close to supply pins 14, 15, 24, 44, 48 with 10nF and 10µF capacitors. 2. All video outputs are unloaded during tests. – 14 – CXA2161R Measurement Point V 22kΩ I2C 150Ω SCL SDA 150Ω 42 41 40 39 38 37 36 35 34 33 32 31 30 29 75Ω 100nF 75Ω 100nF 75Ω 100nF 75Ω 100nF 75Ω 100nF 75Ω 100nF 75Ω 100nF 45 26 46 25 47 24 48 23 49 22 50 21 51 20 52 19 53 18 54 17 55 16 56 15 +5V 1 2 68kΩ 100nF 3 100nF 4 5 6 7 8 100nF +5V 100nF 27 100nF 150Ω 44 100nF 150Ω 28 100nF +5V 150Ω 43 100nF 150Ω 9 +12V 1µF +12V 10 11 12 13 14 +5V 75Ω 75Ω 75Ω 75Ω 75Ω 75Ω Input Signal Fig. 2. Video System (Gain, Dynamic Range, Bandwidth, Differential Gain, Differential Phase, Crosstalk, Linearity, Sync Detection) Signal applied to Pins 1, 3, 4, 5, 6, 7, 50, 51, 52, 53, 54, 55, 56 Output signal measured from Pins 38, 39, 41, 43, 45, 46, 47 Notes) 1. All supplies de-coupled close to supply pins 14, 15, 24, 44, 48 with 10nF and 10µF capacitors. 2. For tests requiring video measuring equipment with 75Ω input impedance, an external video line driver or buffer is used. 3. For video crosstalk tests all video inputs are terminated with 37.5Ω – 15 – CXA2161R Output Measurement Point V I2C SCL SDA 42 41 40 39 38 37 36 35 34 33 32 31 30 29 +5V +5V 100nF 43 28 44 27 45 26 46 25 47 24 48 23 49 22 50 21 51 20 52 19 53 18 54 17 55 16 56 15 +12V 1 2 3 4 5 6 7 8 9 +5V –5V 1µF +12V 10 11 12 13 14 +5V Input Measurement V Point Fig. 3. Audio System (DC Tests) DC measured from Pins 16, 17, 19, 20, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 42 Notes) 1. Single audio supply configuration shown. Operate switches for dual supply configuration. 2. All supplies de-coupled close to supply pins 14, 15, 21, 24, 44, 48 with 10nF and 10µF capacitors. – 16 – CXA2161R 10kΩ Measurement Point V 1kΩ 1µF 10µF 10µF 1µF I2C SCL SDA 10µF 1kΩ 42 41 40 39 38 37 36 35 34 33 32 31 30 29 +5V +5V 100nF 43 28 44 27 45 26 46 25 47 24 48 23 49 22 50 21 51 20 52 19 53 18 54 17 55 16 56 15 10µF 10µF 10µF 10µF +12V 1 2 3 4 5 6 7 8 9 1µF +5V 1kΩ 1µF 1µF 1kΩ –5V 1kΩ 1µF 1µF 1kΩ 1µF 1kΩ 1µF 1kΩ +12V 10 11 12 13 14 +5V Input Signal Fig. 4. Audio System (Single Supply — Gain, Bandwidth, Signal to Noise, Electronic Volume, Zero Cross Detection, Limiter) (Dual Supply — Distortion, Dynamic Range, Crosstalk) Signal applied to Pins 16, 17, 19, 20, 22, 23, 29, 42 Output signal measured from Pins 25, 26, 27, 28, 30, 31, 32 Notes) 1. Single audio supply configuration shown. Operate switches for dual supply configuration. 2. All supplies de-coupled close to supply pins 14, 15, 21, 24, 44, 48 with 10nF and 10µF capacitors. – 17 – CXA2161R I2C Control Data Format S Slave address A S: Start condition DATA1 A DATA2 A: Acknowledge A DATA3 A DATA4 A DATAn A P P: Stop condition Address = 90H I2C Data Structure (write mode) Address Data1 b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 0 0 0 = Write RIN1/LIN1 GAIN CONTROL TV AUD MUTE VOLUME CONTROL Data2 MONO SWITCH TV VOL BYPASS TV MONO SWITCH TV AUDIO SELECT PHONO BYPASS Data3 TV AUD MUTE OUTPUT LIMIT VCR MONO SWITCH VCR AUDIO SELECT OVERLAY ENABLE Data4 TV INPUT MUTE LOGIC LEVEL Data5 VCR INPUT MUTE Data7 ZCD FAST BLANK TV VIDEO SWITCH VIN5 CLAMP VIN7 CLAMP VIN3 CLAMP ENABLE VOUT6 ENABLE VOUT5 ENABLE VOUT4 ENABLE VOUT3 ENABLE VOUT2 ENABLE VOUT1 SYNC SEL VOUT5 0V FNC DIR RGB GAIN VCR VIDEO SWITCH Data6 FNC FOLLOW FNC LEVEL MIXER CONTROL I2C Data Structure (read mode) Address Data b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 0 0 1 = Read NOT USED NOT USED ZERO CROSS STATUS P.O.D. NOT USED SYNC DETECT Note) ZCD = Zero Cross Detect P.O.D. = Power on Detect – 18 – FNC_VCR CXA2161R Video I2C Write Structure Video Switch 1: TV Output [Data 5 Bits 0, 1, 2] Blue Vout1 Green Vout2 Encoder 0 xxxxx000 Blue VIN1 Encoder Green VIN3 Encoder Red VIN5 Encoder CVBS VIN8 Digital encoder RGB or CVBS 1 xxxxx001 Bias Bias Encoder Chrominance VIN6 Encoder Luminance VIN9 Digital encoder Y/C Switch setting R/C Vout3 CVBS/Y Vout4 Comment VCR VCR Green Chrominance/Red VIN4 VIN7 VCR CVBS/Y VCR Y/C or RGB VIN10 3 xxxxx011 Bias Bias Bias TV CVBS VIN11 TV 4 xxxxx100 Bias Bias Encoder Chrominance VIN5 Encoder Luminance VIN3 Digital encoder Y/C Encoder 5 xxxxx101 Blue VIN1 Encoder Green VIN3 Encoder Red VIN5 Aux CVBS VIN12 Encoder RGB and Aux CVBS 6 xxxxx110 Bias Bias Aux Chrominance VIN13 Aux CVBS/Y VIN12 Aux Y/C or CVBS 7 xxxxx111 Bias Bias Bias Bias Video mute (Power on default) 2 xxxxx010 VCR Blue VIN2 After power on all TV outputs are off (high impedance output) and muted. TV RGB GAIN Control [Data 5 Bits 3, 4] I2C setting RGB GAIN Extra gain/dB 0 xxx00xxx 0 (Power on default) 1 xxx01xxx +1 2 xxx10xxx +2 3 xxx11xxx +3 – 19 – CXA2161R Video Switch 2: VCR Output [Data 5 Bits 5, 6, 7] Switch setting Chrominance Vout5 CVBS/Y Vout6 Comment 0 000xxxxx Encoder Chrominance Encoder CVBS/Y VIN5 VIN8 Digital encoder Y/C 1 001xxxxx Encoder Chrominance Encoder CVBS/Y VIN6 VIN9 Digital encoder Y/C or CVBS 2 010xxxxx VCR Chrominance VIN7 VCR CVBS/Y VIN10 VCR Y/C 3 011xxxxx Bias TV CVBS VIN11 TV CVBS 4 100xxxxx Encoder Chrominance Encoder Luminance VIN5 VIN3 5 101xxxxx Bias Aux CVBS VIN12 Aux CVBS 6 110xxxxx Aux Chrominance VIN13 Aux CVBS/Y VIN12 Aux Y/C or CVBS 7 111xxxxx Bias Bias Video mute (Power on default) Encoder Y/C After power on VCR outputs are off (high impedance) and muted. MIXER CONTROL [Data 6 Bits 0, 1] I2C setting Mixer Output Vout7 0 xxxxxx00 No mix, Vout7 = Vout4 (CVBS) 1 xxxxxx01 Mix of Vout4 (Y) + Vout3 (C) 2 xxxxxx10 No mix, Vout7 = Vin8 (CVBS) 3 xxxxxx11 No mix, Vout7 = Vout4 (CVBS) (Power on default) Input Clamp Control VIN3 Clamp [Data 6 Bit 2] xxxxx0xx = GREEN input on VIN3. DC restore clamp active. (Power on default.) xxxxx1xx = CVBS input on VIN3. Sync tip clamp active. Input Clamp Control VIN7 Clamp [Data 6 Bit 3] xxxx0xxx = CHROMINANCE input on VIN7. Chrominance bias applied. (Power on default.) xxxx1xxx = RED input on VIN7. DC restore clamp applied. Input Clamp Control VIN5 Clamp [Data 6 Bit 4] xxx0xxxx = RED input on VIN5. DC restore clamp applied. (Power on default.) xxx1xxxx = CHROMINANCE input on VIN5. Chrominance bias applied. – 20 – CXA2161R Sync Select Control for RGB DC Restore Circuits SYNC_SEL [Data 6 Bits 5, 6] When the TV output is set to RGB + Y/CVBS mode. Then it is necessary to select the input that contains the sync information for the RGB signal. This will normally be the digital encoder CVBS or VCR CVBS input. I2C setting SYNC SEL Input with sync 0 x00xxxxx VIN8 (Power on default) 1 x01xxxxx VIN9 2 x10xxxxx VIN10 3 x11xxxxx VIN12 Standby Mode Control [Data 7 Bits 0, 1, 2, 3, 4, 5] The video outputs VOUT1, 2, 3, 4, 5, 6 can be individually turned off using data byte 7. 0 = Video output off. (Power on default) 1 = Video output on. Note) When switched off, the video outputs are in a high impedance state. With a normal 150Ω load, the outputs will be pulled to 0V. Bi-directional Line Control on VCR Scart. Vout5_0V [Data 7 Bit 6] x0xxxxxx = Vout5 active. Connected to input specified in VCR switch table. x1xxxxxx = Vout5 set to 0V (Power on default) I = 6mA (When set to 0V mode) VCR Scart 75Ω 6dB Vout5 0V Vout5 Chrominance out Pin 15 Red in Chrominance In Chrominance Out VIN_7 Red in Chrominance in Fig 5. Bi-directional Line to VCR As Pin 15 on the VCR scart can be bi-directional, either chrominance output or red/chrominance input, it is necessary for output Vout5 to be individually controlled. When the VCR inputs red/chrominance signals, the output Vout5 is set to 0V giving the required line impedance of 75Ω. – 21 – CXA2161R I2C Audio Signal Control Channel Select TV (Phono), VCR [Data 2, 3 Bits 1, 2] Switch setting RTV, Phono_R, ROUT1 LTV, Phono_L, LOUT1 0 xxxxx00x Rin1 Lin1 1 xxxxx01x Rin2 Lin2 2 xxxxx10x Rin3 Lin3 3 xxxxx11x Rin4 Lin4 After power on Rin4/Lin4 are selected. Mono Switch TV [Data 2 Bits 3, 4, 5] Switch setting Connection to R channel output Connection to L channel output Comment 0 xx000xxx R L Normal 1 xx001xxx (R + L mix) (R + L mix) 2 xx010xxx L R Channel swap 3 xx011xxx R R Right channel only 4 xx100xxx L L Left channel only 5 xx101xxx R L Normal 6 xx110xxx R L Normal 7 xx111xxx R L Normal (power on default) Mono mix Mono Switch VCR [Data 3 Bits 3, 4, 5] Switch setting Connection to R channel output Connection to L channel output Comment 0 xx000xxx R L 1 xx001xxx (R + L mix) (R + L mix) 2 xx010xxx L R Channel swap 3 xx011xxx R R Right channel only 4 xx100xxx L L Left channel only 5 xx101xxx R L Normal 6 xx110xxx R L Normal X All audio outputs disabled (RTV, LTV, PHONO_R, PHONO_L, MONO, ROUT1, LOUT1) (power on default) 7 xx111xxx X – 22 – Normal Mono mix CXA2161R PHONO BYPASS [Data 2 Bit 0] xxxxxxx0 = Phono outputs connected after volume control block. (Power on default) xxxxxxx1 = Phono outputs connected before volume control block. TV VOL BYPASS [Data 2 Bit 6] x0xxxxxx = TV outputs connected after volume control block. (Power on default) x1xxxxxx = TV outputs connected before volume control block. MONO SWITCH [Data 2 Bit 7] 0xxxxxxx = Mono output connected to mix of TV R + L channels. (Power on default) 1xxxxxxx = Mono output connected to mix of RIN1 + LIN1 inputs. VOLUME CONTROL [Data 1 Bits 1, 2, 3, 4, 5] Setting Volume gain 0 xx00000x +6dB 1 xx00001x +4dB 2 xx00010x +2dB 3 xx00011x 0dB (power on default) 4 xx00100x –2dB 5 xx00101x –4dB 6 xx00110x –6dB 7 xx00111x –8dB 8 xx01000x –10dB 9 xx01001x –12dB 10 xx01010x –14dB 11 xx01011x –16dB : : xx11111x –56dB 31 AUDIO RIN1/LIN1 GAIN [Data 1 Bits 6, 7] Setting Input attenuation 0 00xxxxxx –6dB (Power on default) (Note 1) 1 01xxxxxx –3dB 2 10xxxxxx +0dB 3 11xxxxxx +3dB Note 1) The power on default is –6dB. As the output amplifiers have a nominal +6dB gain the overall input to output gain is 0dB. – 23 – CXA2161R OVERLAY ENABLE [Data3 Bit 0] xxxxxxx0 = Overlay off (Power on default) xxxxxxx1 = Overlay on: Rin3 and Lin3 are mixed and added to Rin1, Lin1 channels. Rin1 and Lin1 are attenuated by 16dB before mixing with the tone. TV Mute and Zero Cross Operation When the zero cross is switched on (ZCD = 1), volume control changes are only implemented when the audio signal passes though the zero cross point. Similarly, when a mute instruction is sent, the TV outputs are only muted when the signal passes the zero cross point. This eliminates any click noise. There are two TV audio mute control bits in the bus map. By having two bits it allows the TV outputs to be muted, the TV channel changed and then un-muted all in one I2C write operation. The normal structure for a click free audio channel change is as follows: Data 1: Mute the TV audio output with the ZCD switched on. Data 2: Change the TV audio source. Data 3: Un-mute the TV audio output again with the ZCD switched on. Operation of the Mute circuit TV Aud Mute [Data 1 Bit 0] [Data 3 Bit 7] ZCD [Data 7 Bit 7] 0 0 Un-mute immediately 0 1 Un-mute on next zero cross 1 0 Mute immediately 1 1 Mute on next zero cross TV, Phono and Mono output After power on TV Audio Mute = 1 and ZCD are set to 1. TV INPUT MUTE [Data 4 Bit 7] 0xxxxxxx = The input to the TV switch is not muted. 1xxxxxxx = The input to the TV switch is muted. (power on default) VCR INPUT MUTE [Data 6 Bit 7] 0xxxxxxx = The input to the VCR switch is not muted. 1xxxxxxx = The input to the VCR switch is muted. (power on default) OUTPUT LIMIT [Data 3 Bit 6] This will limit the output level of the volume control block to 2.2Vrms maximum. 0xxxxxxx = The volume control outputs are not limited. (power on default) 1xxxxxxx = The volume control outputs are limited to 2.2Vrms. – 24 – CXA2161R Fast Blanking Operation (Pin 16 on SCART), FBLK The fast blanking signal instructs the TV to select either the external CVBS information or the external RGB information. This is used to superimpose an on screen display (OSD) presentation (normally RGB) upon a CVBS background. Fast blanking information has the same nominal phase as the RGB and CVBS signal, and is defined as follows, Fast blanking output at scart, 1. CVBS mode: Scart pin voltage = 0 to 0.4V 2. RGB mode: Scart pin voltage = 1 to 3.0V The threshold voltage is approximately 0.75V at the scart input. Fast Blanking I2C Control In the CXA2161R, there are two fast blanking inputs, one associated with the digital encoder input (FBLK_IN1) and another associated with the VCR RGB/CVBS input (FBLK_IN2). These can be selected and switched to the output using an I2C instruction. In addition, the fast blank output pin can be set to a constant 0V or +3.5V by means of the I2C control. Hence there are four possible states. These are set according to the following table. FAST_BLANK [Data 4 Bits 0, 1] I2C setting BLANK_LEVEL Fast blank output pin voltage 0 xxxxxx00 0V (Power on default) 1 xxxxxx01 Same level as Fast Blank in 1 (0/+3.5V) 2 xxxxxx10 Same level as Fast Blank in 2 (0/+3.5V) 3 xxxxxx11 +3.5V Fast Blank Output Interface The Fast Blanking output pin is connected to the scart via a 75Ω resistor. 75Ω TV_FBLK TV 0V/+3.5V 75Ω Scart line 16 CXA2161R Fig. 6. Fast Blanking Output Interface – 25 – CXA2161R Function Switching Operation (Pin 8 on scart) The function switch facility is designed to read the status of the SCART function Pin 8 from the VCR scart connector and store this in the status register. Both, VCR and TV function lines can be set to outputs and controlled by I2C. The TV function line has two modes, the first being control via I2C and secondly the follow mode where the output will follow the same state as the VCR input. Setting the Direction for the Function Lines The input and control for the function lines is set by the FNC_DIR and FNC_FOLLOW bits. FNC_FOLLOW [Data 4 Bit 3] FNC_DIR [Data 4 Bit 2] VCR Pin 8 TV Pin 8 0 0 Input (Level stored in read register) Output Controlled by FNC_LEVEL 0 1 Output Controlled by FNC_LEVEL Output Holds previous level 1 0 Input (Level stored in read register) Output Follows same level as VCR input 1 1 Output (Both set to same voltage controlled by FNC_LEVEL) FNC_LEVEL [Data 4 Bits 4, 5] These bits set the voltage at the (TV_FNC or VCR_FNC) outputs. The output is determined by the table above. I2C control FNC_LEVEL Voltage at output Mode 0 xx00xxxx < 2V Internal TV 1 xx01xxxx > 4.5V, < 7V External scart input 16:9 mode 2 xx10xxxx < 2V Internal TV 3 xx11xxxx > 9.5V External scart input 4:3 mode Note) After power on the output is internal TV mode ie. 0V at the pin. +12V_DIG > 9.5V > 4.5 < 7V < 2V FNC_VCR 10kΩ Inside TV FNC_TV Scart Pin 8 Scart Pin 8 Fig. 7. TV Function Switch Output – 26 – 10kΩ CXA2161R Logic and Interrupt Output These open collector output pins can be used for an interrupt line to a microprocessor or as a general purpose logic output. Interrupt Output The INTRUPT pin will become a current sink for approximately 2µs when the VCR input function line changes from: a) 0 to 6V, 6 to 0V b) 0 to 12V, 12 to 0V c) 6 to 12V, 12 to 6V This pin will normally be connected to +5V through a 10kΩ resistor. Logic Output The logic output level can be changed using the logic output bit in the I2C register, LOGIC_LEVEL. LOGIC LEVEL [Data 4 Bit 6] x0xxxxxx = Current sink mode resulting in < 0.4V saturation voltage on logic pin. (Power on default) x1xxxxxx = Open collector/high output impedance on logic pin. Imax during current sink = 1mA +3 to 14V 10kΩ External resistors 10kΩ To Microprocessor 2µs INTRUPT LOGIC Fig. 8. INTRUPT and Logic Line Interface – 27 – CXA2161R Read Mode Status Register The following information can be read from the status register: FNC VCR [Bits 0, 1] The status register bits 0, 1 hold the level of the input function line Input pin voltage FNC_VCR SCART mode 0 to +2V (default) Data 8 b1 b0 (Internal) 0 0 +4.5 to +7V (16:9 External) 0 1 +9.5 to +12V (4:3 External) 1 1 SYNC DETECT [Bit 2] Once a valid sync signal is detected on the input selected by SYNC_SELECT this bit is set to 1. The bit is reset to 0 every time the SYNC_SELECT is changed. It is assumed that when a video input is in-active then the input level will be 0V with minimum noise. POD (Power on Detect) [Bit 4] This bit is set to 1 after power on. It is then changed to 0 after the first I2C read. It is used to detect if the supply has been corrupted. If the POR bit is read as 1 at any time then the IC should be re-initialized to the correct I2C settings. Zero Cross Status [Bit 5] This audio function is used to determine if an input audio signal has passed the zero cross point. For dual supply operation the zero cross point is 0V. For Single supply, the zero cross point is approximately 6V. Zero cross point Input signal Bias voltage Fig. 9. Zero Cross Point 0 = No zero cross detected 1 = Signal has passed through zero cross point. – 28 – CXA2161R Description of Operation Video Section Inputs and Outputs The video section comprises of thirteen (13) high impedance inputs switched through to seven (7) video outputs. An internal +6dB amplifier is connected to each output. The amplifier is required to compensate for the 6dB attenuation that occurs at the 75Ω series output resistor. The outputs VOUT_1 to VOUT_6 are capable of driving 150Ω loads. Output VOUT_7 is designed to interface to an RF Modulator but requires an external buffer to drive a 75Ω load. Composite/Luminance Inputs The 4 composite (or luminance) inputs are ac coupled to the input pins. The signals are first sync tip clamped to a set level. These clamps are permanently active, therefore these inputs should only be used for signals with a sync. VCC = +5V VCC = +5V 1Vp-p 2Vp-p 2.4V 0.3V 0V 0V Output signal Input signal Fig. 10. CVBS/Y Waveforms RGB Inputs The RGB inputs are ac coupled to the input pins. The inputs have a dc restore circuit, which is used to set the blanking level to a fixed voltage. The clamps are controlled by the timing signal provided by the sync detect circuit. It is necessary to select the correct luma or CVBS signal associated with the RGB inputs for the sync select circuit. It is assumed that a sync signal will not be present on any of the RGB input signals. For inputs that can be either red or chrominance then the clamp can be switched between the dc restore mode (for red input) and average level bias (for chrominance). The RGB signals are fed through additional amplifiers that are controlled via I2C. These allow the nominal 0.7Vp-p signal to be increased to 0.8Vp-p, 0.9Vp-p or 1Vp-p. When the TV output is in Y/C mode, the RGB gain should be set to 0dB to prevent over amplification of the chrominance output. VCC = +5V VCC = +5V 0.7Vp-p 1.4Vp-p 2.4V 0.6V 0V 0V Output signal Input signal Fig. 11. RGB Waveforms – 29 – CXA2161R DIG CVBS/Y DIG CVBS/Y VCR CVBS/Y AUX CVBS/Y RGB input clamp timing Sync Detection Circuit The clamp signals, used to restore the RGB level, are generated from the sync detect circuit. By using the SYNC_SELECT control bits, the 4 different CVBS/Y inputs may be selected. Once selected, the clamped signal is compared with a threshold voltage 65mV above the tip level. If the signal is less than this threshold it is not passed to the next block. If greater than the threshold, it is passed to the discrimination circuit that checks that the duty cycle is greater than 91%. The discrimination block also contains a time constant which, when a sync is detected, holds the status line high for at least 11 video lines. If a valid sync signal is detected the SYNC_DETECT bit in the read register is set to 1. +5V_VID SYNC_SELECT LOGIC 68kΩ External R/C SYNC_ID Comparator 0.1µF Status register SYNC_DETECT bit Duty Discrimination I 2C Sync detect circuit GND_VID Fig. 12. Sync Detection Circuit Chrominance Inputs The chrominance signals are ac coupled to the input pins. The inputs have a fixed dc bias that sets the average level to approximately 3V for VIN_5 & VIN_7 and 2.35V for VIN_6 & VIN_13. For inputs that can also be RED signals the input circuit can be switched to the dc restore mode. Typical waveforms: VCC = +5V VCC = +5V 2.35 or 3V 0.7Vp-p 1.8V 0V 1.4Vp-p 0V Chrominance input pin voltage Chrominance output pin voltage Fig. 13. Chrominance Waveforms – 30 – CXA2161R Y/C Mixer A Y/C mixer can be used for mixing Luminance and Chrominance signals for use with an external RF modulator connected to VOUT_7. The Y/C mixer is controlled via the I2C data bus. The signal may be a mix of the TV Y/C signals or simply the TV CVBS signal. It is also possible to select the CVBS signal from the digital encoder. The circuit is shown in Fig 14. with a trap circuit used to give 6dB attenuation at 4.43MHz of the Luminance signal. The output VOUT_7 cannot drive loads higher than 20kΩ resistive. If it is necessary to drive a 75Ω load with this output then an external emitter follower arrangement should be used. R/C 0, 1, 2 or 3dB CVBS/Y 6dB VOUT_3 6dB VOUT_4 Mixer switch 2kΩ 6dB VOUT_7 VIN_8 = CVBS TRAP R For recommended values: see application circuit C L Fig. 14. Internal Y/C Mixer Circuit Switching the Video Outputs Off Each video output can be individually turned off using the I2C. When turned off, the output is set to a high impedance state and hence the current consumption and power dissipation is reduced. After power on, all the video outputs are set to the high impedance state. – 31 – CXA2161R Typical Video Interface Circuits Single or Dual Supply 100nF VIN_1 to VIN_13 75Ω Scart Fig. 15. Video Input Interface 75Ω VOUT_1 to VOUT_6 75Ω (Line C = 400pF max) Scart Fig. 16. Video Output Interface – 32 – CXA2161R Audio Section Inputs and Outputs The audio system consists of 4 stereo inputs, 2 stereo outputs and separate mono and Phono outputs. The stereo outputs can be connected to any one of the 4 stereo inputs. All audio inputs have a –6dB attenuator except RIN_1 and LIN_1. Therefore, the net gain of the audio system from input to output is 0dB, as an amplifier having +6dB of gain follows the internal switch. The stereo input RIN_1/LIN_1 has extra switchable gain as this input is typically connected to an audio DAC with full scale of 1Vrms or less. The output impedance of each audio amplifier is near zero, and may be directly coupled to the scart in the case of a dual supply but must be ac coupled through a capacitor (typically 10µF) for the single supply case. The outputs are capable of driving 600Ω loads. The user may add additional low pass filters to the outputs. TV Output Switching The TV audio section is composed of an audio switch followed by a volume control stage. The volume is adjustable from +6dB to –56dB in 2dB steps. The volume control block includes a switchable limiter function to prevent the output signals exceeding 2.2Vrms. When activated, the output signals from the volume control block will be clamped to 2.2Vrms. A mono switch that allows the mixed R + L signal to be switched to the R and L output channels follows the volume control section. The mono switch is also capable of routing the R signal onto both R and L channel and similarly the L signal to the R and L output channels. This may be used if the audio channels consist of two different languages. It is also capable of swapping the R and L channels. TV Mute This I2C mute function acts only on the TV, Phono and mono audio circuits. Audio mute will be implemented after an audio zero cross detection to reduce click noise if ZCD = 1. Zero Cross Detector (ZCD) The zero cross detector reduces the effect of click noise when implementing a volume change or an audio mute. The volume change or mute instruction sent by I2C will only be implemented when a minimal (ie zero cross) signal amplitude is detected. It can be seen from the I2C write format that the same mute bit occurs in DATA1 and DATA3. This allows the software to action a mute, then after a delay (1/Audio_freq (min)) make any suitable changes to the audio source and then un-mute the output buffer. Such a period provides ample time to allow any audio signals to pass the zero cross point before the signal source is changed. VCR Output Switching The outputs ROUT1, LOUT1 have a fixed gain of 0dB from the input. If any attenuation is required then it is possible to insert a series resistance on the input. Again, this output has a mono switching block that allows the mixed R + L to be inserted on both output channels. – 33 – CXA2161R Phono outputs There is a stereo Phono output that carries the same signal as the TV output. This is typically used for connection to a hi-fi. The signal level of the Phono outputs is normally the same as the TV outputs however it is possible to bypass the volume section and set the Phono outputs to a fixed level. If any attenuation is required then this can be done externally. Mono Output The mono output for the RF modulator has two settings. The first is a mix of the TV R + L channels. In this case, the output signal will have the same volume control as the RTV/LTV outputs. The second setting is a mix of the audio DAC inputs (RIN_1 + LIN_1). In this setting the output will always have fixed volume and if the tone overlay is used, this will appear on the output. Audio Overlay The inputs RIN_3, LIN_3 may be used for a normal stereo audio input or alternatively to overlay an external audio source onto the TV outputs. This may be a tone or voice. The R and L inputs are mixed and then added equally to the RIN_1 and LIN_1 inputs. The I2C control bit Audio overlay enable is used to switch on this facility and control the attenuator block on RIN_3 which is set to give an extra 5dB of attenuation when switched on. If two tones are used then it is up to the user to switch them individually before the A/V switch. When the tone overlay is activated, the signals RIN_1, LIN_1 are attenuated by approximately 16dB before mixing. Audio Disable All the audio outputs may be disabled using the Audio Output Disable function in the VCR mono switching block [Data Byte 3 Bits 3, 4, 5 set to 111]. This disable mode is different from the normal mute as it can be used for power reduction in stand by modes. – 34 – CXA2161R Typical Audio Interface Circuits Supply type 1: Dual supply 0.1µF RIN_1, 2, 3, 4 LIN_1, 2, 3, 4 Scart Fig. 17. Audio Input Interface RTV, LTV ROUT1, LOUT1 PHONO_R, PHONO_L Optional protection resistor Optional protection resistor MONO 600Ω to 10kΩ (Line C = 400pF max) Scart 600Ω to 10kΩ (Line C = 400pF max) To RF modulator Fig. 18. Audio Output Interface Supply type 2: Single supply 0.1µF RIN_1, 2, 3, 4 LIN_1, 2, 3, 4 Scart Fig. 19. Audio Input Interface RTV, LTV ROUT1, LOUT1 10µF 600Ω to 10kΩ (Line C = 400pF max) Scart PHONO_R, PHONO_L 10µF MONO To RF modulator 600Ω to 10kΩ (Line C = 400pF max) The user may use larger capacitors if required. Fig. 20. Audio Output Interface – 35 – CXA2161R Application in Set Top Box Inputs Outputs B G R CVBS C Y FAST BLANKING Digtal Encoder B G VCR R/C CVBS/Y FAST BLANKING FUNCTION SWITCH VIN_1 VIN_3 VIN_5 VIN_8 VIN_6 VIN_9 FBLK_IN1 VOUT_1 VOUT_2 VOUT_3 VOUT_4 TV_FBLK TV_FNC CXA2161R VIN_2 A/V switch VIN_4 VOUT_5 VIN_7 VOUT_6 VIN_10 FBLK_IN2 VCR_FNC VOUT_7 TV CVBS VIN_11 CVBS/Y VIN_12 C VIN_13 AUX B G TV R/C CVBS/Y FAST BLANKING FUNCTION SWITCH C CVBS/Y VCR CVBS RF MOD. Fig. 21. Video Application with 6 Output Digital Encoder Inputs Outputs B G/CVBS Digtal R/C Encoder CVBS/Y FAST BLANKING VIN_1 VIN_3 VIN_5 VIN_8 FBLK_IN1 C Analogue CVBS/Y Sat. VIN_6 VIN_9 B G VCR R/C CVBS/Y FAST BLANKING FUNCTION SWITCH VOUT_1 VOUT_2 VOUT_3 VOUT_4 TV_FBLK TV_FNC CXA2161R VIN_2 A/V switch VIN_4 VOUT_5 VIN_7 VOUT_6 VIN_10 FBLK_IN2 VCR_FNC VOUT_7 TV AUX CVBS B G TV R/C CVBS/Y FAST BLANKING FUNCTION SWITCH C CVBS/Y VCR CVBS RF MOD. VIN_11 CVBS/Y VIN12 C VIN13 Fig. 22. Video Application with 4 Output Digital Encoder – 36 – CXA2161R Audio Application L TV RIN_1 LIN_1 RTV LTV RIN_2 LIN_2 ROUT1 LOUT1 VCR TV or STB generated voice/ tone RIN_3 LIN_3 PHONO_R PHONO_L Hi-Fi AUX fs = 2Vrms RIN_4 LIN_4 MONO STB audio DAC full scale = 2Vrms VCR fs = 2Vrms Fig. 23. Audio Application – 37 – R L RF Modulator R TV (Mono) CXA2161R Supply Connections +5V (±0.25V) +12V (±0.6V) +5V/12V_VCCA +12V_DIG +5V_DIG +5V_VID +5V_VOUT AUD_BIAS VID_BIAS –5V_GNDA GND_DIG GND_VID 0.1µF –5V (±0.25V) Fig. 24. Dual Supply +12V (±0.6V) +5V/12V_VCCA +5V (±0.25V) +12V_DIG +5V_DIG +5V_VID AUD_BIAS 22µF +5V_VOUT VID_BIAS –5V_GNDA GND_DIG Fig. 25. Single Ended Supply – 38 – GND_VID 0.1µF GND VCR_RIN GND VCR_LIN VCR_FNC GND VCR_FBLANK GND VCR_CVBS_IN TV_RIN GND TV_LIN TV_FNC GND TV_FBLANK 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 VCR 1 3 5 7 9 11 13 15 17 19 21 1 3 5 7 9 11 13 15 17 19 GND VCR_ROUT VCR_LOUT GND VCR_BLUE GND VCR_GREEN GND VCR_RED/C GND Digital fast blank AUX video inputs Digital encoder inputs VCR_CVBS_OUT GND TV_ROUT TV_LOUT GND TV_BLUE GND TV_GREEN GND TV_RED/C GND TV_CVBS_OUT 75Ω DIG_LUMA DIG_FBLANK AUX_C 75Ω 75Ω 75Ω 75Ω DIG_CVBS AUX_Y/CVBS 75Ω 75Ω DIG_RED DIG_CHROMA 75Ω 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF +5V 75Ω 75Ω 75Ω +5V 75Ω DIG_GREEN DIG_BLUE TV_BLUE TV_GREEN TV_RED/C TV_CVBS_OUT 42 +5V 100nF 68kΩ 1 55 VIN_9 VIN_12 56 54 VIN_8 53 VIN_6 52 VIN_5 51 VIN_3 50 VIN_1 49 VID_BIAS 2 4 5 6 7 9 8 75Ω 75Ω 75Ω 75Ω 100nF 100nF 100nF 100nF 100nF 3 CXA2161R 75Ω 75Ω 11 10 LTV 25 RTV 26 LIN_1 22 RIN_1 23 14 10kΩ 100nF +5V +12V 100nF 100nF 100nF 100nF GND 100nF 100nF 10µF +12V 10µF 10µF 10µF 100nF TV_LIN TV_RIN VCR_LIN VCR_RIN 22µF DIGITAL_AUDIO_L DIGITAL_AUDIO_R Digital Audio Input TV_LOUT TV_ROUT VCR_LOUT VCR_ROUT Place close to Pin 44 10µF Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. LIN_3 16 +12V_ DIG 15 RIN_3 17 AUD_BIAS 18 LIN_2 19 RIN_2 20 –5V_GNDA 21 13 75Ω 12 28 LOUT1 27 ROUT1 29 10µF +12V Place close to Pin 14 100nF Supplies Place close to Pin 24 +5V/12V_VCCA 24 30 31 32 33 34 35 36 10kΩ 37 1.8kΩ 10kΩ AUX_L 10µF 10µF 10µF 100nF 38 100µH 39 75Ω 40 48 +5V_VID 47 VOUT_1 46 VOUT_2 45 VOUT_3 GND 75Ω 12pF 41 43 VOUT_4 44 +5V_VOUT 100nF VIN_13 SYNC_ID 18 TV_CVBS_IN 21 VIN_10 VCR_CVBS_IN 20 VIN_7 VCR_RED/C TV_CVBS_IN GND VOUT_5 VlN_4 VCR_GREEN TV GND_VID VCR_RED/C VOUT_6 VIN_11 VOUT_7 VCR_CVBS_OUT TRAP VIN_2 VCR_BLUE AUX_R GND +5V INTRUPT GND_DIG RIN_4 VOUT_7 to RF Modulator SCL SCL SDA SDA TV_FBLK TV_FBLANK LlN_4 +5V LOGIC TV_FNC FBLK_IN1 MONO VCR_FBLANK FNC_TV PHONO_R VCR_FNC FBLK_IN2 PHONO_L FNC VCR +5V_ DIG – 39 – +5V Application Circuit 1 Single Ended Supply CXA2161R VCR_RIN GND VCR_LIN VCR_FNC GND VCR_FBLANK GND VCR_CVBS_IN TV_RIN GND TV_LIN TV_FNC GND TV_FBLANK GND 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 VCR 1 3 5 7 9 11 13 15 17 19 21 1 3 5 7 9 11 13 15 17 GND GND VCR_ROUT VCR_LOUT GND VCR_BLUE GND VCR_GREEN GND VCR_RED/C GND Digital fast blank AUX video inputs Digital encoder inputs VCR_CVBS_OUT GND TV_ROUT TV_LOUT GND TV_BLUE GND TV_GREEN GND TV_RED/C 75Ω DIG_LUMA DIG_FBLANK AUX_C 75Ω 75Ω 75Ω 75Ω DIG_CVBS AUX_Y/CVBS 75Ω 75Ω DIG_RED DIG_CHROMA 75Ω 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF +5V 75Ω 75Ω 75Ω +5V 75Ω DIG_GREEN DIG_BLUE TV_BLUE TV_GREEN TV_RED/C TV_CVBS_OUT 42 +5V 100nF 68kΩ 1 55 VIN_9 VIN_12 56 54 VIN_8 53 VIN_6 52 VIN_5 51 VIN_3 50 VIN_1 49 VID_BIAS 2 4 5 6 7 75Ω 75Ω 75Ω 75Ω 75Ω 11 10 75Ω 9 8 100nF 100nF 100nF 100nF 100nF 3 CXA2161R 28 LTV 25 RTV 26 LOUT1 27 ROUT1 29 100nF AUX_L 13 75Ω 12 14 10kΩ +12V 100nF 100nF 100nF 100nF –5V 100nF 100nF +5V 100nF 100nF Place close to Pin 21 10µF 10µF TV_LIN TV_RIN VCR_LIN VCR_RIN DIGITAL_AUDIO_L DIGITAL_AUDIO_R Digital Audio Input TV_LOUT TV_ROUT VCR_LOUT VCC Place close to Pin 44 +5V Place close to Pin 14 VCR_ROUT Place close to Pin 24 –5V 100nF 10µF 100nF +12V Supplies Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. LIN_3 16 +12V_ DIG 15 RIN_3 17 AUD_BIAS 18 LIN_2 19 RIN_2 20 –5V_GNDA 21 LIN_1 22 RIN_1 23 +5V/12V_VCCA 24 30 31 32 33 34 35 36 37 10kΩ 38 1.8kΩ 10kΩ 39 75Ω 40 48 +5V_VID 47 VOUT_1 46 VOUT_2 45 VOUT_3 GND 75Ω 100µH 12pF 41 43 VOUT_4 44 +5V_VOUT 100nF VIN_13 SYNC_ID TV_CVBS_OUT TV_CVBS_IN 19 VIN_10 VCR_CVBS_IN 18 VIN_7 VCR_RED/C 20 VOUT_5 VlN_4 VCR_GREEN TV_CVBS_IN GND_VID VIN_2 VCR_BLUE 21 GND VOUT_6 VCR_RED/C VOUT_7 VIN_11 TRAP VCR_CVBS_OUT INTRUPT GND_DIG TV +5V SCL TV_FBLK RIN_4 VOUT_7 to RF Modulator SCL SDA SDA LOGIC TV_FBLANK LlN_4 AUX_R GND +5V MONO TV_FNC FBLK_IN2 VCR_FBLANK FBLK_IN1 PHONO_R VCR_FNC FNC_TV PHONO_L FNC VCR +5V_ DIG – 40 – +5V Application Circuit 2 Dual Supply CXA2161R CXA2161R Notes on operation 1) Supply de-coupling capacitors, 10nF and 10µF in parallel should be inserted as close as possible to the supply Pins 14, 15, 24 and 44. When using the dual supply configuration apply the capacitors to Pin 21 in addition to the listed supply pins. 2) For best results with dual supply configuration, two +5V supplies should be used, audio (Pin 24) and video/digital (Pins 14, 44 and 49). 3) To minimize crosstalk, attention should be given to the routing of audio and video to the IC inputs. PCB track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video. 4) Attention should be given to the electrolytic capacitors on the output pins. In single supply configuration the audio pin dc bias voltage will be approximately 6.0V, therefore the positive terminal of the capacitors should be orientated towards the device pin. 5) To minimise stray capacitance the 75Ω series resistor on video outputs VOUT_1 to VOUT_6 should be mounted as close as possible to the device Pins 47, 46, 45, 44, 41 and 39. 6) When driving video loads with impedance of 75Ω, video output VOUT_7 (Pin 38) must be connected to the load via a buffer or line driver. This buffer should be located close to the output (Pin 38). 7) In dual supply mode, series protection resistors may be added on Audio outputs which are connected Scart connectors. – 41 – CXA2161R Typical Performance Curves Gain [dB] Video gain – VOUT_1, 2, 3, 4, 5, 6 8 7 6 5 4 3 2 1 0 VOUT_1, 2, 3 VOUT_4, 5, 6 1 10 100 Frequency [MHz] Gain [dB] Video gain – VOUT_7 8 7 6 5 4 3 2 1 0 Mixer Off Mixer On 1 10 100 Frequency [MHz] Audio gain Gain [dB] 0.00 –1.00 –2.00 –3.00 –4.00 1 10 100 1000 10000 Frequency [kHz] Audio output distortion TV outputs Audio output distortion ROUT1, LOUT1 1 1 0.1 0.01 0.001 0.00 Single supply configuration THD [%] THD [%] Single supply configuration 1.00 2.00 3.00 0.1 0.01 0.001 0.00 Input level [Vrms] 1.00 2.00 Input level [Vrms] – 42 – 3.00 CXA2161R Package Outline Unit: mm 56PIN LQFP(PLASTIC) 1.7MAX 12.0 ± 0.2 ∗ 10.0 ± 0.1 0.1 42 29 28 43 B A 56 15 14 + 0.08 0.32 – 0.07 0.65 0.13 M + 0.08 0.32 – 0.07 0.25 0° to 10° 0.6 ± 0.15 (0.3) DETAIL B (0.5) (11.0) 0.1 ± 0.1 (0.125) + 0.04 0.145 – 0.025 1 DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LQFP-56P-L01 LEAD TREATMENT PALLADIUM PLATING LQFP056-P-1010 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.3g – 43 – Sony Corporation