CXD8302Q PLL for CCD Cameras For the availability of this product, please contact the sales office. Description The CXD8302Q has the functions needs to configure a PLL circuit with a timing generator and external sync signals for a CCD of 480K pixels (EIA, effective pixels) and 570K pixels (CCIR, effective pixels). 44 pin QFP (Plastic) Features • EIA and CCIR compatible • Compatible with component digital and composite digital recording format • Both SYNC and VD/HD signals can be used for external sync signals Applications CCD cameras Structure Silicon gate CMOS IC Absolute Maximum Ratings • Supply voltage VDD VSS – 0.3 to +7 V • Input voltage VI VSS – 0.3 to VDD+0.3 V • Storage temperature Tstg –40 to +125 °C Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 • Operating temperature Topr 0 to 70 V °C Block Diagram EXTSYNC 15 EXTHD 14 EXTVD 13 fH Separation of fH and fV fV 65 Clocks Delay 19 EXTfH 20 INTfH 41 HD V reset MODE1 Frequency Division EIA : 1/572 (1/568) CCIR: 1/576 (1/567) 26 H timing 2fH 31 Latch MODE2 EIA/CCIR 32 CLKI 38 Frequency Division EIA : 1/525 CCIR: 1/625 8 2 3 4 7 8 V timing Pulse Generation Circuit V latch 42 VD 43 SYNC 44 BLK 37 CLKO 9 10 11 INTfH phase setting Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94320A52-PP CXD8302Q NC EIA/CCIR MODE2 TEST6 VDD Vss TEST5 MODE1 TEST4 NC Vss Pin Configuration 33 32 31 30 29 28 27 26 25 24 23 Vss 34 22 TEST3 TEST7 35 21 TEST2 NC 36 20 INTfH CLKO 37 19 EXTfH CLKI 38 18 TEST1 VDD 39 17 VDD Vss 40 16 Vss HD 41 15 EXTSYNC VD 42 14 EXTHD SYNC 43 13 EXTVD BLK 44 DLY1 DLY2 VDD 7 8 9 10 11 DLY7 DLY0 6 DLY6 5 DLY5 4 DLY4 3 DLY3 2 Vss 1 Vss 12 Vss –2– CXD8302Q Pin Description Pin No. Symbol I/O Description 1 VSS 2 DLY0 I Pin 20 (INTfH) phase setting. (With pull-up resistor) 3 DLY1 I Pin 20 (INTfH) phase setting. (With pull-up resistor) 4 DLY2 I Pin 20 (INTfH) phase setting. (With pull-up resistor) 5 VDD — 6 VSS — 7 DLY3 I Pin 20 (INTfH) phase setting. (With pull-up resistor) 8 DLY4 I Pin 20 (INTfH) phase setting. (With pull-up resistor) 9 DLY5 I Pin 20 (INTfH) phase setting. (With pull-up resistor) 10 DLY6 I Pin 20 (INTfH) phase setting. (With pull-up resistor) 11 DLY7 I Pin 20 (INTfH) phase setting (MSB). (With pull-up resistor) 12 VSS 13 EXTVD I External VD input. (With pull-up resistor) 14 EXTHD I External HD input. (With pull-up resistor) 15 EXTSYNC I External SYNC input. (With pull-up resistor) 16 VSS — 17 VDD — 18 TEST1 O Test output (normally OPEN). 19 EXTfH O External fH output. 20 INTfH O Internal fH output. 21 TEST2 O Test output (normally OPEN). 22 TEST3 O Test output (normally OPEN). 23 VSS — 24 NC — 25 TEST4 I Test input (normally High). (With pull-up resistor) 26 MODE I High: SYNC sync mode, Low: VD/HD sync mode. (With pull-up resistor) 27 TEST5 I Test input (normally Low). (With pull-down resistor) 28 VSS — 29 VDD — 30 TEST6 I Test input (normally High). (With pull-up resistor) 31 MODE2 I High: Component digital mode, Low: Composite digital mode. (With pull-up resistor) 32 EIA/CCIR I High: EIA mode, Low: CCIR mode. 33 NC — 34 VSS — 35 TEST7 O 36 NC — 37 CLKO O — — Test output (normally OPEN). Inversed output of CLKI. –3– (With pull-up resistor) CXD8302Q Pin No. Symbol I/O Description 38 CLKI I 39 VDD — 40 VSS — 41 HD O Horizontal sync signal output. 42 VD O Vertical sync signal output. 43 SYNC O Sync signal output. 44 BLK O Blanking pulse output. Clock input (from timing generator). Electrical Characteristics 1) DC characteristics Item Input voltage (VDD = 5V±0.25V, Topr = 0 to 70°C, VSS = 0V) Symbol High VIH Low VIL Conditions Min. Typ. Max. 0.7VDD Input current 1 IIN1 (Input pins other than those below) Unit V 0.3VDD V –10 ±1 10 µA Input current 2 (Input pins with pull-up resistor) IIN2 VI = VDD 10 35 120 µA Input current 3 (Input pins with pull-down resistor) IIN3 VI = VSS –8 –30 –100 µA High VOH IOH = –2mA 2.4 4.5 Low VOL IOL = 4mA Output voltage 0.2 V 0.4 V 2) AC characteristics Vertical reset in VD/HD sync mode The phase of EXTVD should be input as shown in the diagram below against the first equivalent pulse during vertical blanking period. (Take care as the following conditions might not be satisfied depending on the phase setting of INTfH if the phases are locked when the falling phase shifts a lot between EXTfH and INTfH.) SYNC EXTVD 81 clocks 81 clocks The EXTVD should fall at the timing shown with the slashes. –4– CXD8302Q 3) I/O pin capacitance (VDD = 5V±0.25V, Topr = 0 to 70°C, VSS = 0V) Item Symbol Input pin capacitance Min. Typ. CIN Output pin capacitance COUT Max. Unit 2.0 pF 4.0 pF Description of Operation 1) Operation overview • Functions as sync signal generator Each of fH (INTfH), VD, HD, SYNC, and BLK pulses is generated from clocks input by the timing generator. These pulses are generated by free running if external sync signals are not input. • External synchronization function (PLL) When the SYNC (EXTSYNC) or VD/HD (EXTVD/EXTHD) external sync signal is input, the vertical reset is compulsorily triggered on each of the fH (INTfH), VD, HD, SYNC, and BLK pulses, and fH (EXTfH) is simultaneously generated according to the external sync signal. Phase comparison is done externally between INTfH and EXTfH and a PLL circuit is configured, then the timing generator is synchronized with an external sync signal. 2) Mode setting Symbol Pin No. L H EIA/CCIR 32 CCIR EIA MODE1 MODE2 26 VD/HD sync mode: EXTVD/EXTHD is used as the external sync signal, and the EXTHD signal becomes EXTfH. SYNC sync mode: EXTSYNC is used as the external sync signal, and the EXTfH is obtained by separating it from EXTSYNC 31 Composite digital mode; Clock frequency input by timing generator EIA 17.897725MHz (1137.5fH = 5fsc) CCIR 17.734475MHz (1135 + 4/625fH = 4fsc) Component digital mode: Clock frequency input by timing generator EIA 18MHz (1144fH) CCIR 18MHz (1152fH) The phase relationship between external sync and EXTfH in each sync mode is shown below. • VD/HD sync mode The rise and fall timings of EXTHD signal are directly reflected on EXTfH. EXTHD EXTfH • SYNC synchronous mode The fall timing of EXTSYNC is the fall timing EXTfH, but the rise timing of EXTfH is generated by counting the number of clocks input by the timing generator. Therefore, make sure to compare phases of fall timing of between EXTfH and INTfH for PLL configuration in the SYNC synchronous mode. EXTSYNC (HSYNC) EXTfH 42 clocks 42 clocks –5– CXD8302Q 3) INTfH phase setting In either VD/HD or SYNC sync mode, the INTfH phase should be adjusted in line with the phase variance of EXTfH, which forms the reference for phase comparison. The INTfH phase may be adjusted against VD, HD, SYNC and BLK pulses using DLY0 to DLY7, respectively. (The state of INTfH and EXTfH phases fixed by PLL leads to phase adjustment of VD, HD, SYNC, and BLK pulse against the external sync signal.) The INTfH is set to the phase being delayed (DELAY-64) clocks from that of HD. DELAY = 0 to 255: to be set in 8-bit binary with DLY7 as MSB. High: 1, low: 0. (DELAY – 64) clocks INTfH 128 clocks HD 128 clocks Example of System Configuration Phase Comparator EXTfH External sync signal SYNC fH 15 HD 14 VD 13 MODE1 19 LPF VCO 36MHz (Component digital) 35.79545MHz (Composite digital, EIA) 35.56895MHz (Composite digital, CCIR) INTfH Electronic shutter serial data 33 20 Separation of fH and fv fV XH1, 2 1/2 Frequency Division CLK 38 XSUB Pulse Generation Circuit 26 Frequency Division/ Pulse Generation Circuit XRG 7 XSG1, 2 HCLP1, 2 6 VD VCLP 5 42 XV1 to 4 SHP, SHD HD 41 To each driver To signal processing circuit PBLK CXD8302Q CXD2422R (TG) Note) 1. Either SYNC or VD/HD is used as the external sync signal.When SYNC is used (SYNC synchronous mode), fix MODE1 to High; when VD/HD is used (VD/HD synchronous mode), fix MODE1 to Low. 2. Be sure to do phase comparison of the falling edge of EXTfH and INTfH for SYNC synchronous mode. –6– –7– BLK SYNC VD HD BLK SYNC VD HD Timing Chart (1) EIA vertical direction 9H Even Field 9H Odd Field 20H 20H CXD8302Q –8– BLK SYNC VD HD BLK SYNC VD HD Timing Chart (1) EIA vertical direction 9H Even Field 9H Odd Field 20H 20H CXD8302Q –9– H BLK VSYNC EQ HSYNC HD Number of clocks CCIR H BLK VSYNC EQ HSYNC HD Number of clocks EIA –50 –55 –50 –57 Timing Chart (2) CCIR vertical direction 0 0 0 0 0 0 29 29 29 27 27 27 50 50 71 69 100 100 113 111 128 128 150 150 200 217 (Component digital mode) 214 (Composite digital mode) 196 (Component digital mode) 195 (Composite digital mode) 200 Clock frequency 18MHz (Component digital mode) 17.897725MHz (Composite digital mode, EIA) 17.734475MHz (Composite digital mode, CCIR) CXD8302Q CXD8302Q Package Outline Unit: mm 44PIN QFP (PLASTIC) 12.4 ± 0.4 0.8 ± 0.05 0.8 ± 0.05 10.0 ± 0.1 23 A 12 1 0.3 ± 0.1 11 MAX 0.53 0.35 ± 0.15 0.15 ± 0.05 MIN MAX 0.8 ± 0.15 – 0.15 0.15 C 0. 6 44 11.24 ± 0.2 5° 22 10.76 34 13° 33 0.58 ± 0.2 1.75 + 2° 5° – 5° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-44P-L221 LEAD TREATMENT EIAJ CODE ∗QFP044-P-1010-B LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.4g JEDEC CODE – 10 –