CXD2422R CCD Camera Timing Generator Description The CXD2422R generates the timing pulses required for driving and signal processing CCDs with 480,000 pixels (EIA, effective pixels) and CCDs with 570,000 pixels (CCIR, effective pixels). 64 pin LQFP (Plastic) Features • EIA and CCIR compatible • Compatible with component digital and composite digital recording format • Compatible with field/frame accumulation modes Absolute Maximum Ratings • Supply voltage VDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Applications CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX062/063AL Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 • Operating temperature Topr –20 to +75 SD 30 VD HD 2 D2 51 1 D3 D0 D1 SDO Block Diagram 3 4 5 6 39 Shift Register SC 31 LD 32 Latch 9 °C XSG1 38 XSG2 V latch 13 V 44 XV1 4 43 XV2 Shutter data 42 XV3 HTSG 58 Output F.F. Pulse Generation Circuit Latch FLD/FRM 61 41 XV4 35 XSUB 26 HCLP1 EIA/CCIR 62 22 HCLP2 MODE 63 21 VCLP Reset Internal clock High-speed Pulse Generation Circuit 28 PBLK Delay 27 PBLKON SHP SHD XRG XH1 XH2 CLK BCO 7 BCI 37 36 BBO 54 53 52 BBI 18 19 20 BAI 14 15 16 BAO 34 CLKO Delay CLKI 33 XH gate Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94Y30-ST CXD2422R TEST11 TEST10 TEST9 TEST8 XV1 XV2 XV3 XV4 VSS XSG1 XSG2 XH1 XH2 XSUB CLKO CLKI Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 BCI 53 28 PBLK XRG 54 27 PBLKON VSS 55 26 HCLP1 VDD 56 25 TEST6 NC 57 24 VDD HTSG 58 23 VSS RST 59 22 HCLP2 TEST12 60 21 VCLP FLD/FRM 61 20 BBO EIA/CCIR 62 19 BBI MODE 63 18 SHD 64 17 NC TEST13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BAO TEST7 BAI 29 SHP 52 TEST5 BCO TEST4 SD TEST3 30 TEST2 51 TEST1 SDO VSS SC CLK 31 HD 50 VD NC D3 LD D2 32 D1 49 D0 NC –2– CXD2422R Pin Description Pin No. Symbol I/O Description 1 D0 O Extended I/O output. 2 D1 O Extended I/O output. 3 D2 O Extended I/O output. 4 D3 O Extended I/O output. 5 VD I Vertical sync signal input. (With pull-up resistor) 6 HD I Horizontal sync signal input. (With pull-up resistor) 7 CLK O Two frequency divider output of Pin 33. 8 VSS — 9 TEST1 I Test input (normally Low). (With pull-down resistor) 10 TEST2 I Test input (normally Low). (With pull-down resistor) 11 TEST3 I Test input (normally Low). (With pull-down resistor) 12 TEST4 I Test input (normally Low). (With pull-down resistor) 13 TEST5 I Test input (normally Low). (With pull-down resistor) 14 SHP O CCD output precharge level sampling pulse output. 15 BAI I Buffer input (for phase adjustment of SHP). (With pull-up resistor) 16 BAO O Non-inversed output of BAI. 17 (NC) — 18 SHD O CCD output signal level sampling pulse output. 19 BBI I Buffer input (for phase adjustment of SHD). (With pull-up resistor) 20 BBO O Non-inversed output of BBI. 21 VCLP O Vertical clamp pulse output. 22 HCLP2 O Horizontal (dummy bit block) clamp pulse output. 23 VSS — 24 VDD — 25 TEST6 I Test input (normally High). (With pull-up resistor) 26 HCLP1 O Horizontal (OPB block) clamp pulse output. 27 PBLKON I Output ON/OFF of PBLK. (High: ON) (With pull-up resistor). 28 PBLK O Preblanking pulse output. 29 TEST7 I Test input (normally High). (With pull-up resistor) 30 SD I Serial data input for electronic shutter control. (With pull-up resistor) 31 SC I Clock input for electronic shutter control. (With pull-up resistor) 32 LD I Latch pulse input for electronic shutter control. (With pull-up resistor) 33 CLKI I Clock input. 34 CLKO O Inversed output of CLKI. 35 XSUB O Substrate pulse output for electronic shutter. 36 XH2 O Clock output for horizontal register drive. 37 XH1 O Clock output for horizontal register drive. –3– CXD2422R Pin No. Symbol I/O Description 38 XSG2 O Sensor charge readout pulse output. 39 XSG1 O Sensor charge readout pulse output. 40 VSS — 41 XV4 O Clock output for vertical register drive. 42 XV3 O Clock output for vertical register drive. 43 XV2 O Clock output for vertical register drive. 44 XV1 O Clock output for vertical register drive. 45 TEST8 O Test output (normally open). 46 TEST9 O Test output (normally open). 47 TEST10 O Test output (normally open). 48 TEST11 O Test output (normally open). 49 (NC) — 50 (NC) — 51 SDO O Serial data output for electronic shutter control. 52 BCO O Non-inversed output of BCI. 53 BCI I Buffer input (for phase adjustment of XRG). (With pull-up resistor) 54 XRG O Reset gate pulse output of output block. 55 VSS — 56 VDD — 57 (NC) — 58 HTSG I Readout pulse (XSG1, 2) ON/OFF. (High: OFF) (With pull-down resistor) 59 RST I Test input (normally High). (With pull-up resistor) 60 TEST12 I Test input (normally Low). (With pull-up resistor) 61 FLD/FRM I High: Field accumulation mode, Low: Frame accumulation mode. (With pull-up resistor) 62 EIA/CCIR I High: EIA, Low: CCIR. (With pull-up resistor) 63 MODE I High: Component digital mode, Low: Composite digital mode. (With pull-up resistor) 64 TEST13 I Test input (normally Low). (With pull-up resistor) Note) TEST12 and TEST13 have a built-in pull-up resistor. Be sure to fix them at Low. –4– CXD2422R Electrical Characteristics 1) DC characteristics Item (VDD = 4.5 to 5.5V, Topr = –20 to +75°C) Conditions Symbol Supply voltage VDD Input/Output voltages VI, VO Typ. Max. Unit 4.5 5.0 5.5 V VDD V VSS VIH Input voltage Min. 0.7VDD VIL Output voltage Pull-up/ Pull-down resistors 0.3VDD VOH IOH = –2mA VOL IOL = 4mA RPU, RPD VIL = 0V, VIH = VDD VDD – 0.8 40k 2) AC characteristics 2)-1. Pulses for electronic shutter control (SD, SC, LD) SD ts1 SC tH1 tw1 ts2 LD Symbol ts1 tH1 tw1 ts2 tH2 tw2 V t H2 tw2 Item Min. SD set-up time, activated by the rising edge of SC 20ns SD hold time, activated by the rising edge of SC 20ns SC pulse width 20ns SC set-up time, activated by the rising edge of LD 20ns SC hold time, activated by the rising edge of LD 20ns LD pulse width 20ns –5– V V 100k 0.4 V 250k Ω CXD2422R 2)-2. HD/VD take-in characteristics HD, VD 1.6V 1.6V 0.7VDD CLK ts3 th3 (VDD = 4.5 to 5.5V, Topr = –20 to +75°C) Symbol ts3 th3 Definition Min. Typ. Max. Unit HD/VD set-up time, activated by CLK 4 ns HD/VD hold time, activated by CLK 0 ns 2)-3. Field discrimination characteristics VD 1.6V VD 1.6V tpd1 tpd1 HD HD When the HD logic level is Low tpd1 after VD falls, the field is discriminated as an ODD (EVEN with CCIR) field. When the HD logic level is High tpd1 after VD falls, the field is discriminated as an EVEN (ODD with CCIR) field. (VDD = 4.5 to 5.5V, Topr = –20 to +75°C) Symbol tpd1 Definition Min. Field discriminating clock phase, activated by the falling edge of VD 890 –6– Typ. Max. Unit ns CXD2422R 2)-4. CLKO, CLK, XH1, XH2, XRG, SHP, SHD phase characteristics CLKI tpd3 CLKO tpd2 tpd5 CLK tpd4 tpd7 XH1 XH2 tpd6 tpd8 tpd9 tpd11 XRG tpd10 tpd12 SHP tpd13 tpd15 SHD tpd14 (VDD = 4.5 to 5.5V, Topr = –20 to +75°C, load capacitance = 10pF) Symbol tpd2 tpd3 tpd4 tpd5 tpd6 tpd7 tpd8 tpd9 tpd10 tpd11 tpd12 tpd13 tpd14 tpd15 Definition Min. Typ. Max. Unit CLKO falling delay time against CLKI 3.5 6.2 12.1 ns CLKO rising delay time against CLKI 4.0 7.2 14.1 ns CLK2 falling delay time against CLKI 5.2 9.3 18.3 ns CLK2 rising delay time against CLKI 6.5 11.6 22.8 ns XH1 falling delay time against CLKI 5.2 8.8 17.2 ns XH1 rising delay time against CLKI 6.4 11.4 22.4 ns XH2 rising delay time against CLKI 5.7 10.2 20.3 ns XH2 falling delay time against CLKI 5.3 9.4 18.5 ns XRG falling delay time against CLKI 4.7 8.4 16.5 ns XRG rising delay time against CLKI 5.2 9.2 18.1 ns SHP rising delay time against CLKI 8.1 14.4 28.3 ns SHP falling delay time against CLKI 7.9 14.1 27.6 ns SHD falling delay time against CLKI 7.9 14.1 27.6 ns SHD rising delay time against CLKI 8.6 15.2 29.8 ns –7– CXD2422R Phases of SHP, SHD, and XRG pulses can be adjusted using on-chip buffers. Internal CXD2422R R SHP 15 C BAI 16 BAO 17 SHP Delay times of SHP, SHD, and XRG can be adjusted with C and R. Delay characteristics of on-chip buffers (VDD = 4.5 to 5.5V, Topr = –20 to +75°C, load capacitance = 10pF) Symbol tpd16 tpd17 tpd18 tpd19 tpd20 tpd21 Definition Min. Typ. Max. Unit Rising delay time from BAI to BAO 4.0 7.1 13.9 ns Falling delay time from BAI to BAO 2.8 5.5 10.7 ns Rising delay time from BBI to BBO 4.0 7.0 13.8 ns Falling delay time from BBI to BBO 3.0 5.4 10.7 ns Rising delay time from BCI to BCO 4.3 7.6 15.0 ns Falling delay time from BCI to BCO 3.4 6.0 11.7 ns 3) I/O pin capacitances Item (VDD = VI = 0V, f = 1MHz) Symbol Min. Typ. Max. Unit Input pin capacitance CIN 9 pF Output pin capacitance COUT 11 pF –8– CXD2422R Description of Operation 1) Mode setting Symbol EIA/CCIR Pin No. Low High 62 CCIR EIA Composite digital mode Component digital mode MODE 63 FLD/FRM 61 HTSG 58 PBLKON 27 Clock (CLKI) input EIA 35.79545MHz (2275fH = 10fsc) CCIR 35.46895MHz (2270+8/625fH = 8fsc) Frame accumulation Clock (CLKI) input EIA 36MHz (2288fH) CCIR 36MHz (2304fH) Field accumulation XSG1 and XSG2 pulses are output. XSG1 and XSG2 pulses are fixed at High. (Readout suspended) PBLK is fixed at High. PBLK pulse is output. –9– CXD2422R 2) Inputting serial data The accumulation time of the electronic shutter is controlled by external serial data. Input pins (SD, SC, and LD) are used to input serial data. SD: Serial data input SC: Clock input LD: Latch pulse input The following is the serial data timing chart. SD D3 D2 D1 D0 S8 S7 S6 S5 S4 S3 S2 S1 S0 SC LD D3 to D0: Not related to the accumulation time of the electronic shutter. Data are output to D3 to D0 pins after converted into parallel data and being latched at LD. S8 to S0: Sdata is set in 9-bit binary with S8 as MSB (High: 1, Low: 0). ON/OFF of the electronic shutter and the accumulation time are determined by Sdata. The calculation on the next page is for the accumulation time in each mode. The data for SD are input to the internal 13-bit shift register, and the data can be retrieved as serial data at SDO pin. Note) The electronic shutter might operate from turning power on to inputting serial data. To prevent this operation, process RST and LD pins as shown in the following figures. Be careful, however, as serial data cannot be received before the voltage at RST rises. VDD RST 59 (with pull-up resistor) LD 32 (with pull-up resistor) 4.7k 1000p – 10 – CXD2422R Accumulation time of electronic shutter EIA/ CCIR EIA CCIR Accumulation time (s) Sdata 0 to 261 {(261 – Sdata)/15734} + 1/25678 (Component digital mode) {(261 – Sdata)/15734} + 1/25532 (Composite digital mode) 262 Input prohibited 263 to 511 Electronic shutter OFF 0 to 311 {(311 – Sdata)/15625} + 1/25678 (Component digital mode) {(311 – Sdata)/15625} + 1/25299 (Composite digital mode) 312 Input prohibited 313 to 511 Electronic shutter OFF The Sdata values corresponding to representative shutter speeds are listed below. Shutter speed Sdata EIA CCIR 1/100 104 (068h) 155 (09Bh) 1/125 136 (088h) 187 (0BBh) 1/250 199 (0C7h) 249 (0F9h) 1/500 230 (0E6h) 280 (118h) 1/1000 246 (0F6h) 296 (128h) 1/2000 254 (0FEh) 304 (130h) – 11 – CXD2422R 3) Latch pulse timing Various mode switchings and shutter data are taken in by field. The latch pulse timing is as follows (The broken lines show timing in the EVEN FIELD.): EIA VD HD VLT1 VLT2 IT VLT3 XSG1,2 CCIR VD HD VLT1 VLT2 IT VLT3 XSG1,2 Latch pulse Latched data VLT1 EIA/CCIR, MODE, HTSG VLT2 Shutter data (S8 to S0) VLT3 FLD/FRM – 12 – CXD2422R Example of System Configuration Phase Comparator SYNC fH 15 HD 14 VD 13 MODE1 19 VCO INTfH EXTfH External sync signal LPF 36MHz (Component digital) 35.79545MHz (Composite digital, EIA) 35.56895MHz (Composite digital, CCIR) Electronic shutter serial data 33 20 Separation of fV fH and fV XH1, 2 1/2 Frequency Division 26 CLK 38 Frequency Division/ Pulse Generation Circuit 7 XRG XSUB Pulse Generation Circuit VCLP 5 CXD8302Q XSG1, 2 HCLP1, 2 6 VD 42 XV1 to 4 SHP, SHD HD 41 To each driver To signal processing circuit PBLK CXD2422R (TG) Note) 1. Either SYNC or VD/HD is used as external sync signal. When SYNC is used (SYNC synchronous mode), fix MODE1 to High; when VD/HD is used (VD/HD Synchronous mode), fix MODE1 to Low. 2. Be sure to do phase comparison of the falling edge of EXTfH and INTfH for SYNC synchronous mode. – 13 – – 14 – 491 493 494 492 10 (525) 0 520 ∗1 ∗2 These pulses are output at the position determined by shutter data. ∗1 These pulses are not output during frame accumulation. CCD OUT PBLK HCLP2 HCLP1 VCLP XSUB XSG2 XSG1 XV4 XV3 XV2 XV1 HD BLK VD 5 Timing Chart (1) EIA vertical direction 20 2 4 6 8 1 3 5 7 9 ∗2 494 493 275 ∗1 280 1 3 5 7 2 4 6 8 ∗2 CXD2422R 285 270 265 260 15 – 15 – 5 580 582 581 15 (625) 0 1 620 ∗1 These pulses are not output during frame accumulation. ∗2 These pulses are output at the position determined by shutter data. CCD OUT PBLK HCLP2 HCLP1 VCLP XSUB XSG2 XSG1 XV4 XV3 XV2 XV1 HD BLK VD 10 Timing Chart (2) CCIR vertical direction ∗1 25 1 3 5 7 2 4 6 8 ∗2 581 582 330 ∗1 335 2 4 6 8 1 3 5 7 9 ∗2 CXD2422R 325 320 315 310 20 HD – 16 – SHD SHP XRG XH2 XH1 PBLK HCLP2 HCLP1 VCLP XSUB XV4 XV3 XV2 XV1 CLK 0 0 0 (1144) BLK 2 15 50 55 53 47 60 55 60 65 70 70 75 80 80 85 90 90 95 130 130 128 136 140 138 160 160 164 164 fH = 1144 170 40 30 20 10 Timing Chart (3) EIA horizontal direction, Component digital mode CXD2422R 150 120 110 100 0 – 17 – SHD SHP XRG XH2 XH1 PBLK HCLP2 HCLP1 VCLP XSUB XV4 XV3 XV2 XV1 CLK 0 HD BLK 0 (1137.5) 2 15 50 55 53 47 60 55 60 65 70 70 75 80 80 85 90 90 95 129 128 130 131 130 150.5 153.5 157.5 160.5 157.5 fH = 1137.5 170.5 40 30 20 10 Timing Chart (4) EIA horizontal direction, Composite digital mode CXD2422R 140.5 120 110 100 – 18 – SHD SHP XRG XH2 XH1 PBLK HCLP2 HCLP1 VCLP XSUB XV4 XV3 XV2 XV1 CLK BLK HD 0 0 0 (1152) 2 15 55 53 50 47 60 55 60 65 70 70 75 80 80 85 90 90 95 130 130 128 140 144 150 146 168 fH = 1152 172 172 170 40 30 20 10 Timing Chart (5) CCIR horizontal direction, Component digital mode CXD2422R 160 120 110 100 HD – 19 – SHD SHP XRG XH2 XH1 PBLK HCLP2 HCLP1 VCLP XSUB XV4 XV3 XV2 XV1 CLK 0 0 0 (1135) BLK 2 15 55 53 50 47 60 55 60 65 70 70 75 80 80 85 90 90 95 127 128 129 130 150 151 160 155 155 fH = 1135 170 40 30 20 10 Timing Chart (6) CCIR horizontal direction, Composite digital mode CXD2422R 140 130 120 110 100 – 20 – EIA: EVEN CCIR: ODD EIA: ODD CCIR: EVEN XV4 XV3 XV2 XV1 XV4 XV3 XV2 XV1 XSG2 XSG1 HD CLK 0 Timing Chart (7) Readout interval 65 55 65 60 55 60 50 70 70 75 75 80 80 85 90 100 128 750 759 759 759 759 786 800 831 850 876 921 900 966 966 950 100 (EIA, Component digital) 50 65 70 80 85 90 90 85 80 75 (CCIR, Composite digital) 1135 60 (CCIR, Component digital) 1152 1137.5 (EIA, Composite digital) = 1144 0 128 CXD2422R CXD2422R Timing Chart (8) High-speed pulse timing CLK XH1 XH2 XRG SHP SHD – 21 – CXD2422R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 16 + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY / PHENOL RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP064-P-1010-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.3g JEDEC CODE – 22 –