L6363 PRML READ/WRITE CHANNEL PRODUCT PREVIEW SIGNAL PROCESSING – PR4 signal equalization and loops ■ – 8th order optimized low pass filter with programmable cut-off frequency and boost – single flash 6-bit ADC – 5-TAP programmable/self-adaptive digital FIR for signal equalization – Programmable/self-adaptive Offset and MR Head Asymmetry compensation for signal equalization TQFP100 ORDERING NUMBER: L6363 – Timing and Gain loops for optimum data recovery – Encoder scheme: – Rate 304/338 with Local ECC (16/17 without Local ECC) – Detector scheme: – Media Noise TerminatorTM Detector – Optional Local ECC Post Processing scheme – 8-bit NRZ interface to disk controller – Thermal Asperity detection/compensation and Erasure Flag WRITE – 2 level Write Precomp for Non Linear Transition Shift compensation ■ – Asynchronous and Synchronous Direct Write for disk/head characterization SERVO – Digital Synchronous Servo with data rates up to 75MHz (8x Ovsersampling) ■ CHANNEL QUALITY MONITOR – Fast read parameters optimization for minimum BER ■ – Advanced Disk Surface Defect Scan QUALITY AND RELIABILITY – BIST for analog front-end and digital back-end ■ – Iddq and I/O pins mapping POWER SUPPLY AND CONTROL – 2.5V Analog and 1.8V Digital supply; 1.8V to 3.3V supply for I/O pins ■ – Advanced Power Management features DESCRIPTION L6363 is a 0.18µm CMOS PRML R/W channel supporting data rates up to 750Mb/sec with Servo Demodulation, Clock Synthesis, Channel Quality Monitor for channel optimization and Disk Surface Defect Scan capability – Internal Burst and Grey Code detection – Repeatable Run Out Support June 2001 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/4 2/4 REFCLK EXTCLK IREF INM INP DIAG0 Bandgap Ctrl Zin ODAC OFF FIR FCA LPFCA Digital Test Block Zero Phase & Gain Restart Generator Clock Asymm. Loop ADC Control Block FDAC Low Pass Filter BDAC Thermal Asp. Detection & Control HPF Data Freq. Synthesizer MDAC MRA Servo Freq. Synthesizer GDAC VGA Analog Test Point MUX DIAG1 Gain Loop Offset Loop Timing Loop SRC Servo Burst Demod. Servo Detector Servo Interface Encoder Decoder Interface ECC Interface Data Detector SMD Write Precomp SDATA SDEN SCLK SVO[1:0] SVOCLK TA_OUT ER_FLAG SBD* NRZ[7:0] WCLK WOM WOP L6363 Figure 1. Block Diagram TI-[5:0] TESTBUS[7:0] TBUSCLK RRCLK MODE[1:0] RESET* PWD RG WG SG L6363 mm DIM. MIN. inch TYP. A MAX. MIN. TYP. 1.60 A1 0.05 A2 1.35 B 0.17 C 0.09 0.063 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.22 0.27 0.007 0.009 0.011 0.20 0.003 0.008 D 16.00 0.630 D1 14.00 0.551 D3 12.00 0.472 e 0.50 0.019 E 16.00 0.630 E1 14.00 0.551 E3 12.00 0.472 L 0.45 L1 0.60 0.75 0.018 1.00 K OUTLINE AND MECHANICAL DATA MAX. 0.024 0.030 0.0393 TQFP100 3.5°(min.), 7°(max.) D A D1 A2 D3 A1 75 51 76 50 0.076mm .003 inch Seating Plane e E3 E1 E B PIN 1 IDENTIFICATION 26 100 1 25 K TQFP100M C L L1 3/4 L6363 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 4/4