CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003 D D D D D CD54HC373 . . . F PACKAGE CD74HC373 . . . E OR M PACKAGE (TOP VIEW) 2-V to 6-V VCC Operation Wide Operating Temperature Range of –55°C to 125°C Balanced Propagation Delays and Transition Times Standard Outputs Drive up to 15 LS-TTL Loads Significant Power Reduction Compared to LS-TTL Logic ICs OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND description/ordering information The ’HC373 devices are octal transparent D-type latches designed for 2-V to 6-V VCC operation. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PDIP – E –55°C 55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA SOIC – M CDIP – F Tube CD74HC373E Tube CD74HC373M Tape and reel CD74HC373M96 Tube CD54HC373F3A TOP-SIDE MARKING CD74HC373E HC373M CD54HC373F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003 FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 3 2 1D 1Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output drain current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous output source or sink current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V MIN MAX 2 6 UNIT V 1.5 V 3.15 4.2 VCC = 2 V VCC = 4.5 V 0.5 VIL Low-level input voltage VI VO Input voltage 0 Output voltage 0 tt Input transition (rise and fall) time 1.35 VCC = 6 V V 1.8 VCC = 2 V VCC = 4.5 V VCC = 6 V VCC VCC V V 1000 500 ns 400 TA Operating free-air temperature –55 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS ICC Ci VI = VCC or 0, TA = –55°C TO 125°C TA = –40°C TO 85°C MIN MIN MIN MAX MAX 2V 1.9 1.9 1.9 4.5 V 4.4 4.4 4.4 6V 5.9 5.9 5.9 IOH = –6 mA IOH = –7.8 mA 4.5 V 3.98 3.7 3.84 6V 5.48 5.2 UNIT MAX V 5.34 2V 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.1 0.1 0.1 6V 0.1 0.1 0.1 IOL = 6 mA IOL = 7.8 mA 4.5 V 0.26 0.4 0.33 6V 0.26 0.4 0.33 6V ±0.1 ±1 ±1 µA 6V ±0.5 ±10 ±5 µA VI = VIH or VIL VI = VCC or 0 VO = VCC or 0 TA = 25°C IOH = –20 µA VI = VIH or VIL II IOZ VCC IO = 0 6V Co POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 8 160 80 µA 10 10 10 pF 20 20 20 pF 3 CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC tw Pulse duration, LE high Setup time, data before LE↓ ↓ tsu Hold time, data after LE↓ ↓ th TA = 25°C TA = –55°C TO 125°C TA = –40°C TO 85°C MIN MIN MIN MAX MAX 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 50 75 65 4.5 V 10 15 13 6V 9 13 11 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 UNIT MAX ns ns ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) D Q LOAD CAPACITANCE CL = 50 pF tpd d LE ten tdis OE OE tt Q Q Q Q CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF VCC TA = 25°C TA = –55°C TO 125°C TA = –40°C TO 85°C MIN MIN MIN MAX MAX UNIT MAX 2V 150 225 190 4.5 V 30 45 38 6V 26 38 33 2V 175 265 220 4.5 V 35 53 44 6V 30 45 37 2V 150 225 190 4.5 V 30 45 38 6V 26 38 33 2V 150 225 190 4.5 V 30 45 38 6V 26 38 33 2V 60 90 75 4.5 V 12 18 15 6V 10 15 13 ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TYP Power dissipation capacitance 51 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT pF CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd or tt tw LOAD CIRCUIT VCC Input 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input VCC Reference Input VCC 50% VCC 50% VCC 0V 0V tsu trec Data 50% Input 10% VCC 50% VCC CLK 90% VOLTAGE WAVEFORMS RECOVERY TIME 50% VCC 50% VCC tPLH tPHL 50% 10% 90% 90% tr tPHL Out-of-Phase Output 90% tf tf VCC VOH 50% VCC 10% VOL tf 50% 10% 90% tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% VCC 50% VCC 0V tPLZ tPZL ≈VCC Output Waveform 1 (see Note B) 50% VCC Output Waveform 2 (see Note B) 10% VOL tPHZ tPZH VOH VOL VCC Output Control tPLH 50% VCC 10% VCC 50% VCC 10% 0 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 0V In-Phase Output 90% tr 0V Input th 50% VCC 90% VOH ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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