TI SN74AVCA406GQCR

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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
D Transceiver for Memory Card Interface
D
D
D
[MultiMediaCard (MMC), Secure Digital
(SD), Memory StickE Compliant Products,
SmartMedia Card, and xD-Picture CardE]
Configurable I/O Switching Levels With
Dual-Supply Pins Operating Over Full 1.4-V
to 3.6-V Power-Supply Range
For Low Power Operation, A Ports Are
Placed in High-Impedance State When
Card-Side Supply Voltage Is Switched Off
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D D
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description/ordering information
The SN74AVCA406 is a transceiver for interfacing microprocessors with MultiMediaCards (MMCs), secure digital
(SD) cards, Memory Stick compliant products, SmartMedia cards, or xD-Picture Cards. It integrates high ESD
protection, which eliminates the need for external ESD diodes. Two supply-voltage pins allow the A-port and B-port
input switching thresholds to be configured separately. The A port is designed to track VCCA, while the B port is
designed to track VCCB0 and VCCB1. VCCA ,VCCB0 and VCCB1 can accept any supply voltage from 1.4 V to 3.6 V.
Memory card standards recommend high ESD protection for devices that connect directly to the external memory
card. To meet this need, the SN74AVCA406 incorporates ±15-kV air gap discharge and ±8-kV contact discharge
protection on the card side. If VCCB0 and VCCB1 are switched off (no card inserted), the A-port outputs are placed
in the high-impedance state to conserve power.
The SN74AVCA406 enables system designers to easily interface low-voltage microprocessors to different memory
cards operating at higher voltages. The mode (MODE0 and MODE1) pins are used to configure the device to
interface with different types of cards.
The SN74AVCA406 is offered in the 48-ball MicroStar Jr. ball grid array (BGA) package. This package has
dimensions of 4 × 4 mm, with a 0.5-mm ball pitch for effective board-space savings. Memory cards are widely used
in mobile phones, PDAs, digital cameras, personal media players, camcorders, set-top boxes, etc. Low static power
consumption and small package size make the SN74AVCA406 an ideal choice for these applications.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
-40°C to 85°C
VFBGA - GQC
Tape and reel SN74AVCA406GQCR
WM406
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the propertry of their respective owners.
Copyright  2004, Texas Instruments Incorporated
!&"%! " '(' ) ' ) ( *+,' ) '( )*(') * . ) ( ") %')')
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
terminal assignments
GQC PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
1
2
3
4
5
6
7
VCCA
10A1
2A
4DIR
2DIR
MODE1
10B1
B
3A
1A
1DIR
MODE0
9B1
VCCB0
1B
C
9A
10A2
3DIR
GND
2B
3B
D
9DIR
4A
56DIR
GND
4B
11B
12B
E
78DIR
6A
GND
CS0
GND
10B2
9B2
7A
8A
12A
13A
7B
5B
14B
6B
VCCB1
A
A
B
C
D
F
E
G
VCCA
5A
11A
CS1
8B
VCCA powers all A-port I/Os and control inputs.
VCCB0 powers 1B, 2B, 3B, 4B, 9B1, and 10B1.
VCCB1 powers 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B, and 14B.
F
G
device operation
The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B port is designed
to track VCCB0 and VCCB1. VCCB0 and VCCB1 can accept any supply voltage from 1.4 V to 3.6 V, however, VCCB0,
VCCB1, or both must be greater than or equal to VCCA during normal operation. If VCCB0 and VCCB1 are both at GND,
the A port is in the high-impedance state. The control pins are supplied by VCCA. The microprocessor is connected
to the A port, and the memory card(s) are connected to the B port. The device can be configured using MODE0,
MODE1, CS0, and CS1 pins to interface with 1-bit, 4-bit, or 8-bit memory cards. Outputs 12A and 14B are push-pull
and open drain (OD), respectively, except for NAND flash (XD) mode, where they are open drain and push-pull,
respectively.
Table 1. Interface With Different Memory Cards
2
MODE0
MODE1
MEMORY CARD INTERFACE
0
X
SD/SDIO/MMC/Memory Stick/Memory Stick PRO
1
0
8-bit MMC/4-bit + GPIO translation
1
1
SmartMedia/xD-Picture Card
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
configuration 1a – interfacing with SD or SDIO card
(SD mode or SD 4-bit mode)
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 2. SD or SDIO Card
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
A1
VCCA
VCCA
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
B1
10A1
CLK.h
Clock signal from host
C1
9A
CMD.h
Command signal connected to host
D1
9DIR
CMD-dir.h
Direction control for 9A/9B connected to host
Input
E1
78DIR
(tie-high)
Direction control for 7A/7B and 8A/8B. Not used in this mode. Tie to VCCA.
Input
F1
7A
(tie-low)
I/O pin not used in this mode. Tie to GND.
G1
VCCA
VCCA
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
A2
2A
DAT1.h
Data bit 2 connected to host. Referenced to VCCA.
I/O
B2
3A
DAT2.h
Data bit 3 connected to host. Referenced to VCCA.
I/O
C2
10A2
CLK-f.h
Clock feedback to host for resynchronizing data. Used in OMAP processors. Optional on
other processors. Leave unconnected if not used.
D2
4A
DAT3.h
Data bit 4 connected to host. Referenced to VCCA.
I/O
E2
6A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
F2
8A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
I/O pin not used in this mode. Tie to GND.
PIN FUNCTION
4
Power
Input
G2
5A
(tie-low)
A3
4DIR
DAT3-dir.h
B3
1A
DAT0.h
D3
56DIR
(tie-high)
E3
GND
GND
Ground
Output pin not used in this mode. Do not use. Leave unconnected.
Direction control for 4A/4B
I/O
I/O
Power
Output
I/O
Input
Data bit 1 connected to host. Referenced to VCCA.
C3
PIN
TYPE
I/O
Depopulated ball
Direction control for 5A/5B and 6A/6B. Not used in this mode. Tie to VCCA.
Input
F3
12A
DNU
G3
11A
(tie-low)
Input pin not used in this mode. Tie to GND.
Output
Input
A4
2DIR
DAT1-dir.h
Direction control for 2A/2B connected to host
Input
B4
1DIR
DAT0-dir.h
Direction control for 1A/1B connected to host
Input
C4
3DIR
DAT2-dir.h
Direction control for 3A/3B connected to host
Input
D4
GND
GND
Ground
E4
CS0
CS0.h
Card select from host. Active low. When CS0/ = high, 1A, 2A, 3A, 4A, 1B, 2B, 3B, 4B, 9A,
9B1, and 10A2 are placed in Hi Z and 10B1 is low.
Input
F4
13A
(tie-low)
Input pin not used in this mode. Tie to GND.
Input
G4
CS1
(tie-high)
Card select. Not used in this mode. Tie to VCCA for proper operation.
Input
A5
MODE1
(tie-low)
Input
MODE1, MODE0 determine mode of operation (see Table 1). Tie to GND in this mode.
B5
MODE0
(tie-low)
C5
GND
GND
Ground
D5
4B
DAT3
Data bit 4 connected to card. Referenced to VCCB0.
E5
GND
GND
Ground
F5
7B
DNU
I/O pin not used in this mode. Leave unconnected.
G5
8B
DNU
I/O pin not used in this mode. Leave unconnected.
A6
10B1
CLK
Clock signal connected to card
Output
B6
9B1
CMD
Command signal connected to card
Output
C6
2B
DAT1
Data bit 2 connected to card. Referenced to VCCB0.
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Input
I/O
I/O
I/O
I/O
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 2. SD or SDIO Card (Continued)
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
D6
11B
E6
F6
PIN FUNCTION
PIN
TYPE
DNU
Output pin not used in this mode. Leave unconnected.
Output
10B2
DNU
Output pin not used in this mode. Leave unconnected.
Output
5B
DNU
I/O pin not used in this mode. Leave unconnected.
I/O pin not used in this mode. Leave unconnected.
G6
6B
DNU
A7
VCCB0
VCCB0
B7
1B
DAT0
Data bit 1 connected to card. Referenced to VCCB0.
Data bit 3 connected to card. Referenced to VCCB0.
B-port supply voltage. VCCB0 powers 1B, 2B, 3B, 4B, 9B1, and 10B1.
I/O
I/O
Power
I/O
C7
3B
DAT2
D7
12B
(tie-low)
E7
9B2
DNU
I/O pin not used in this mode. Leave unconnected.
F7
14B
DNU
Open-drain output not used in this mode. Leave unconnected.
Output
B-port supply voltage. VCCB1 powers 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B, and 14B. Not
used in this mode. Tie to GND.
Power
G7
VCCB1
(tie-low)
Input pin not used in this mode. Tie to GND.
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I/O
Input
I/O
5
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
configuration 1b – interfacing with SD card or MMC
(SD 1-bit mode or MMC mode)
6
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 3. SD Card or MMC
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
A1
VCCA
10A1
VCCA
CLK.h
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
Command signal connected to host
B1
PIN FUNCTION
Clock signal from host
PIN
TYPE
Power
Input
C1
9A
CMD.h
D1
9DIR
CMD-dir.h
Direction control for 9A/9B
Input
I/O
E1
78DIR
(tie-high)
Direction control for 7A/7B and 8A/8B. Not used in this mode. Tie to VCCA.
Input
F1
7A
(tie-low)
I/O pin not used in this mode. Tie to GND.
G1
VCCA
(tie-low)
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
A2
VCCA
2A
I/O pin not used in this mode. Tie to GND.
I/O
B2
3A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
I/O
Power
C2
10A2
CLK-f.h
Clock feedback to host for resynchronizing data. Used in OMAP processors. Optional on
other processors. Leave unconnected if not used.
D2
4A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
E2
6A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
F2
8A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
Output
G2
5A
(tie-low)
I/O pin not used in this mode. Tie to GND.
A3
4DIR
(tie-high)
Direction control for 4A/4B. Not used in this mode. Tie to VCCA.
B3
1A
DAT0.h
D3
56DIR
(tie-high)
E3
GND
GND
Ground
F3
12A
DNU
Output pin not used in this mode. Do not use. Leave unconnected.
G3
11A
(tie-low)
Input pin not used in this mode. Tie to GND.
Input
A4
2DIR
(tie-high)
Direction control for 2A/2B. Not used in this mode. Tie to VCCA.
Input
B4
1DIR
DAT0-dir.h
Direction control for 1A/1B
Input
C4
3DIR
(tie-high)
Direction control for 3A/3B. Not used in this mode. Tie to VCCA.
Input
D4
GND
GND
Ground
E4
CS0
CS0.h
Card select from host. Active low. When CS0 = high, 1A, 2A, 3A, 4A, 1B, 2B, 3B, 4B, and 9B1
are placed in Hi Z.
Input
F4
13A
(tie-low)
Input pin not used in this mode. Tie to GND.
Input
G4
CS1
(tie-high)
Card select. Not used in this mode. For proper operation tie to VCCA.
Input
A5
MODE1
(tie-low)
B5
MODE0
(tie-low)
C5
GND
GND
Ground
D5
4B
DNU
I/O pin not used in this mode. Leave unconnected.
E5
GND
GND
Ground
F5
7B
DNU
I/O pin not used in this mode. Leave unconnected.
I/O
G5
8B
DNU
I/O pin not used in this mode. Leave unconnected.
I/O
A6
10B1
CLK
Clock signal connected to card
Output
B6
9B1
CMD
Command signal connected to card
Output
C6
2B
DNU
I/O pin not used in this mode. Leave unconnected.
D6
11B
DNU
Output pin not used in this mode. Leave unconnected.
Output
E6
10B2
DNU
Output pin not used in this mode. Leave unconnected.
Output
F6
5B
DNU
I/O pin not used in this mode. Leave unconnected.
Data bit 1 connected to host. Referenced to VCCA.
C3
I/O
Input
I/O
Depopulated ball
Direction control for 5A/5B and 6A/6B. Not used in this mode. Tie to VCCA.
Input
Output
Input
MODE1, MODE0 determine mode of operation (see Table 1). Tie to GND in this mode.
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Input
I/O
I/O
I/O
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 3. SD Card or MMC (Continued)
PIN
NO.
8
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
PIN FUNCTION
I/O pin not used in this mode. Leave unconnected.
PIN
TYPE
G6
6B
DNU
A7
B7
VCCB0
1B
VCCB0
DAT0
C7
3B
DNU
D7
12B
(tie-low)
E7
9B2
DNU
I/O pin not used in this mode. Leave unconnected.
F7
14B
DNU
Open-drain output not used in this mode. Leave unconnected.
Output
G7
VCCB1
(tie-low)
B-port supply voltage. VCCB1 powers 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B, and 14B. Not
used in this mode. Tie to GND.
Power
B-port supply voltage. VCCB0 powers 1B, 2B, 3B, 4B, 9B1, and 10B1.
Data bit 1 connected to card. Referenced to VCCB0.
I/O pin not used in this mode. Leave unconnected.
Input pin not used in this mode. Tie to GND.
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I/O
Power
I/O
I/O
Input
I/O
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
configuration 1c – interfacing with SD/SDIO card or MMC
(SPI mode)
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 4. SD/SDIO Card or MMC
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
A1
B1
VCCA
10A1
VCCA
SCLK.h
C1
9A
DI.h
D1
9DIR
(tie-high)
Direction control for 9A/9B. Tie high to make 9A an input and 9B an output.
Input
E1
78DIR
(tie-high)
Direction control for 7A/7B and 8A/8B. Not used in this mode. Tie to VCCA.
Input
F1
7A
(tie-low)
I/O pin not used in this mode. Tie to GND.
G1
VCCA
2A
VCCA
CS.h
A2
PIN FUNCTION
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
Serial clock signal from host
Serial data in (master out slave in) connected to host. Connect 9DIR to VCCA to make 9A an
input.
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
Card select connected to host. Connect 2DIR to VCCA to make 2A an input.
I/O pin not used in this mode. Tie to GND.
Power
Input
I/O
I/O
Power
I/O
B2
3A
(tie-low)
C2
10A2
DNU
D2
4A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
E2
6A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
F2
8A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
Clock feedback to host. Not used in this mode. Leave unconnected.
G2
5A
(tie-low)
I/O pin not used in this mode. Tie to GND.
A3
4DIR
(tie-high)
Direction control for 4A/4B. Not used in this mode. Tie to VCCA.
B3
1A
DO.h
Serial data out (master in slave out) connected to host. Connect 1DIR to GND to make 1A an
output.
C3
10
PIN
TYPE
I/O
Output
I/O
Input
I/O
Depopulated ball
D3
56DIR
(tie-high)
E3
GND
GND
Direction control for 5A/5B and 6A/6B. Not used in this mode. Tie to VCCA.
Ground
Output pin not used in this mode. Do not use. Leave unconnected.
Input
F3
12A
DNU
G3
11A
(tie-low)
Input pin not used in this mode. Tie to GND.
Output
Input
A4
2DIR
(tie-high)
Direction control for 2A/2B. Tie to VCCA to make 2A an input and 2B an output.
Input
B4
1DIR
(tie-low)
Direction control for 1A/1B. Tie to GND to make 1B an input and 1A an output.
Input
C4
3DIR
(tie-high)
Direction control for 3A/3B. Not used in this mode. Tie to VCCA.
Input
D4
GND
GND
E4
CS0
(tie-low)
Card select signal. Not used in this mode. For proper operation, tie to GND.
Input
F4
13A
(tie-low)
Input pin not used in this mode. Tie to GND.
Input
G4
CS1
(tie-high)
Card select. Not used in this mode. For proper operation, tie to VCCA.
Input
A5
MODE1
(tie-low)
B5
MODE0
(tie-low)
C5
GND
GND
Ground
D5
4B
DNU
Card select connected to card. Connect 2DIR to VCCA to make 2B an output.
E5
GND
GND
Ground
F5
7B
DNU
I/O pin not used in this mode. Leave unconnected.
I/O
G5
8B
DNU
I/O pin not used in this mode. Leave unconnected.
I/O
A6
10B1
SCLK
Serial clock signal connected to card
Output
B6
9B1
DI
Serial data in (master out slave in) connected to card
Output
I/O pin not used in this mode. Leave unconnected.
Ground
Input
MODE1, MODE0 determine mode of operation (see Table 1). Tie to GND in this mode.
Input
I/O
C6
2B
CS
D6
11B
DNU
Output pin not used in this mode. Leave unconnected.
Output
E6
10B2
DNU
Output pin not used in this mode. Leave unconnected.
Output
F6
5B
DNU
I/O pin not used in this mode. Leave unconnected.
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I/O
I/O
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 4. SD/SDIO Card or MMC (Continued)
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
G6
6B
DNU
A7
VCCB0
VCCB0
B7
1B
DO
PIN FUNCTION
I/O pin not used in this mode. Leave unconnected.
B-port supply voltage. VCCB0 powers 1B, 2B, 3B, 4B, 9B1, and 10B1.
Serial data out (master in slave out) connected to host. Connect 1DIR to GND to make 1B an
input.
I/O
Power
I/O
C7
3B
DNU
D7
12B
(tie-low)
E7
9B2
DNU
I/O pin not used in this mode. Leave unconnected.
F7
14B
DNU
Open-drain output not used in this mode. Leave unconnected.
Output
B-port supply voltage. VCCB1 powers 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B, and 14B. Not
used in this mode. Tie to GND.
Power
G7
VCCB1
(tie-low)
I/O pin not used in this mode. Leave unconnected.
PIN
TYPE
Input pin not used in this mode. Tie to GND.
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I/O
Input
I/O
11
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
configuration 1d – interfacing with SDIO card in slot 0 and SD card (4-bit mode) in slot 1
12
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 5. SDIO Card (Slot 0) and SD Card (Slot 1)
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
A1
VCCA
10A1
VCCA
CLK.h
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
Command signal connected to host
B1
PIN FUNCTION
Clock signal from host
PIN
TYPE
Power
Input
C1
9A
CMD.h
D1
9DIR
CMD-dir.h
Direction control for 9A/9B connected to host
Input
I/O
E1
78DIR
(tie-high)
Direction control for 7A/7B and 8A/8B. Not used in this mode. Tie to VCCA.
Input
F1
7A
(tie-low)
I/O pin not used in this mode. Tie to GND.
G1
VCCA
DAT1.h
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
A2
VCCA
2A
Data bit 2 connected to host. Referenced to VCCA.
I/O
B2
3A
DAT2.h
Data bit 3 connected to host. Referenced to VCCA.
I/O
I/O
Power
C2
10A2
CLK-f.h
Clock feedback to host for resynchronizing data. Used in OMAP processors. Optional on
other processors. Leave unconnected if not used.
D2
4A
DAT3.h
Data bit 4 connected to host. Referenced to VCCA.
I/O
E2
6A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
F2
8A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
I/O pin not used in this mode. Tie to GND.
Output
G2
5A
(tie-low)
A3
4DIR
DAT3-dir.h
B3
1A
DAT0.h
D3
56DIR
(tie-high)
E3
GND
GND
Ground
F3
12A
DNU
Output pin not used in this mode. Do not use. Leave unconnected.
G3
11A
(tie-low)
Input pin not used in this mode. Tie to GND.
Input
A4
2DIR
DAT1-dir.h
Direction control for 2A/2B connected to host
Input
B4
1DIR
DAT0-dir.h
Direction control for 1A/1B connected to host
Input
C4
3DIR
DAT2-dir.h
Direction control for 3A/3B connected to host
Input
D4
GND
GND
Ground
E4
CS0
CS0.h
Card select from host. Active low. When CS0 = high, 1A, 2A, 3A, 4A, 1B, 2B, 3B, 4B, and 9B1
are placed in Hi Z, and 10B1 is low.
Input
F4
13A
(tie-low)
Input pin not used in this mode. Tie to GND.
Input
G4
CS1
CS1.h
Card select from host. Active low. When CS1 = high, 5A, 6A, 7A, 8A, 5B, 6B, 7B, 8B, 7B, and
9B2 are placed in Hi Z, and 10B2 is low.
Input
A5
MODE1
(tie-low)
B5
MODE0
(tie-low)
C5
GND
GND
D5
4B
DAT3.0
E5
GND
GND
Direction control for 4A/4B
Data bit 1 connected to host. Referenced to VCCA.
C3
I/O
Input
I/O
Depopulated ball
Direction control for 5A/5B and 6A/6B. Not used in this mode. Tie to VCCA.
Input
Output
Input
MODE1, MODE0 determine mode of operation (see Table 1). Tie to GND in this mode.
Input
Ground
Data bit 4 connected to card in slot 0. Referenced to VCCB0.
I/O
Ground
F5
7B
DAT2.1
Data bit 3 connected to card in slot 1. Referenced to VCCB1.
G5
8B
DAT3.1
Data bit 4 connected to card in slot 1. Referenced to VCCB1.
I/O
A6
10B1
CLK.0
Clock signal connected to card in slot 0
Output
B6
9B1
CMD.0
Command signal connected to card in slot 0
Output
C6
2B
DAT1.0
Data bit 2 connected to card in slot 0. Referenced to VCCB0.
I/O
I/O
D6
11B
DNU
Output pin not used in this mode. Leave unconnected.
Output
E6
10B2
CLK.1
Clock signal connected to card in slot 1
Output
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 5. SDIO Card (Slot 0) and SD Card (Slot 1) (Continued)
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
14
PIN FUNCTION
PIN
TYPE
F6
5B
DAT0.1
Data bit 1 connected to card in slot 1. Referenced to VCCB1.
I/O
G6
6B
DAT1.1
Data bit 2 connected to card in slot 1. Referenced to VCCB1.
I/O
A7
VCCB0
1B
VCCB0
DAT0.0
B-port supply voltage. VCCB0 powers 1B, 2B, 3B, 4B, 9B1, and 10B1.
B7
Data bit 1 connected to card in slot 0. Referenced to VCCB0.
I/O
C7
3B
DAT2.0
Data bit 3 connected to card in slot 0. Referenced to VCCB0.
I/O
D7
12B
(tie-low)
Input pin not used in this mode. Tie to GND.
Input
E7
9B2
CMD.1
Command signal connected to card in slot 1
I/O
Power
F7
14B
/IRQ.h
Open-drain interrupt output for dual SDIO cards configuration. DAT1 is the input for interrupt.
Output
G7
VCCB1
VCCB1
B-port supply voltage. VCCB1 powers 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B, and 14B.
Power
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
configuration 1e – alternate method of interfacing with SD/SDIO card
(SD mode or SD 4-bit mode)
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 6. Alternate SD/SDIO Card
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
A1
VCCA
VCCA
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
B1
10A1
CLK.h
Clock signal from host
C1
9A
CMD.h
Command signal connected to host
D1
9DIR
CMD-dir.h
Direction control for 9A/9B connected to host
Input
E1
78DIR
(tie-high)
Direction control for 7A/7B and 8A/8B. Not used in this mode. Tie to VCCA.
Input
F1
7A
(tie-low)
I/O pin not used in this mode. Tie to GND.
G1
VCCA
VCCA
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
A2
2A
DAT1.h
Data bit 2 connected to host. Referenced to VCCA.
I/O
B2
3A
DAT2.h
Data bit 3 connected to host. Referenced to VCCA.
I/O
C2
10A2
CLK-f.h
Clock feedback to host for resynchronizing data. Used in OMAP processors. Optional on
other processors. Leave unconnected if not used.
D2
4A
DAT3.h
Data bit 4 connected to host. Referenced to VCCA.
I/O
E2
6A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
F2
8A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
I/O pin not used in this mode. Tie to GND.
PIN FUNCTION
16
Power
Input
G2
5A
(tie-low)
A3
4DIR
DAT3-dir.h
B3
1A
DAT0.h
D3
56DIR
(tie-high)
E3
GND
GND
Ground
Output pin not used in this mode. Do not use. Leave unconnected.
Direction control for 4A/4B
I/O
I/O
Power
Output
I/O
Input
Data bit 1 connected to host. Referenced to VCCA.
C3
PIN
TYPE
I/O
Depopulated ball
Direction control for 5A/5B and 6A/6B. Not used in this mode. Tie to VCCA.
Input
F3
12A
DNU
G3
11A
(tie-low)
Input pin not used in this mode. Tie to GND.
Output
Input
A4
2DIR
DAT1-dir.h
Direction control for 2A/2B connected to host
Input
B4
1DIR
DAT0-dir.h
Direction control for 1A/1B connected to host
Input
C4
3DIR
DAT2-dir.h
Direction control for 3A/3B connected to host
Input
D4
GND
GND
E4
CS0
(tie-high)
Card select signal. Not used in this mode. Tie to VCCA for proper operation.
Input
F4
13A
(tie-low)
Input pin not used in this mode. Tie to GND.
Input
G4
CS1
CS1
Card select from host. Active low. When CS1 = high, 1A, 2A, 3A, 4A, 5B, 6B, 7B, 8B, 9A,
9B2, and 10A2 are placed in Hi Z and 10B1 is low.
Input
A5
MODE1
(tie-low)
Ground
Input
MODE1, MODE0 determine mode of operation (see Table 1). Tie to GND in this mode.
B5
MODE0
(tie-low)
C5
GND
GND
Ground
D5
4B
DNU
I/O pin not used in this mode. Leave unconnected.
E5
GND
GND
Ground
F5
7B
DAT2
Data bit 3 connected to card. Referenced to VCCB1.
G5
8B
DAT3
Data bit 4 connected to card. Referenced to VCCB1.
A6
10B1
DNU
Output pin not used in this mode. Leave unconnected.
Output
B6
9B1
DNU
Output pin not used in this mode. Leave unconnected.
Output
C6
2B
DNU
I/O pin not used in this mode. Leave unconnected.
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Input
I/O
I/O
I/O
I/O
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 6. Alternate SD/SDIO Card (Continued)
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
D6
11B
E6
F6
G6
PIN FUNCTION
PIN
TYPE
DNU
Output pin not used in this mode. Leave unconnected.
Output
10B2
CLK
Clock signal connected to card
Output
5B
DAT0
Data bit 1 connected to card. Referenced to VCCB1.
I/O
6B
DAT1
Data bit 2 connected to card. Referenced to VCCB1.
I/O
A7
VCCB0
(tie-low)
B-port supply voltage. VCCB0 powers 1B, 2B, 3B, 4B, 9B1, and 10B1. Not used in this mode.
Tie to GND.
Power
B7
1B
DNU
I/O pin not used in this mode. Leave unconnected.
I/O
C7
3B
DNU
I/O pin not used in this mode. Leave unconnected.
I/O
D7
12B
(tie-low)
E7
9B2
CMD
Command signal connected to card
F7
14B
DNU
Open-drain output not used in this mode. Leave unconnected.
Output
G7
VCCB1
VCCB1
B-port supply voltage. VCCB1 powers 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B, and 14B.
Power
Input pin not used in this mode. Tie to GND.
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Input
I/O
17
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
configuration 1f – interfacing with Memory Stick
18
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 7. Memory Stick
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
A1
VCCA
VCCA
B1
10A1
SCLK.h
C1
9A
BS.h
D1
9DIR
(tie-high)
Direction control for 9A/9B connected to host. Tie high to make 9A an input, 9B an output.
Input
E1
78DIR
(tie-high)
Direction control for 7A/7B and 8A/8B. Not used in this mode. Tie to VCCA.
Input
F1
7A
(tie-low)
I/O pin not used in this mode. Tie to GND.
G1
VCCA
VCCA
A2
2A
DATA1.h
Data bit 2 connected to host. Referenced to VCCA.
I/O
B2
3A
DATA2.h
Data bit 3 connected to host. Referenced to VCCA.
I/O
C2
10A2
SCLK-f.h
Clock feedback to host for resynchronizing data. Used in OMAP processors. Optional on
other processors. Leave unconnected if not used.
D2
4A
DATA3.h
Data bit 4 connected to host. Referenced to VCCA.
I/O
E2
6A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
F2
8A
(tie-low)
I/O pin not used in this mode. Tie to GND.
I/O
I/O pin not used in this mode. Tie to GND.
PIN FUNCTION
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
Clock signal from host
Power
Input
Bus state connected to host
I/O
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
G2
5A
(tie-low)
A3
4DIR
DATU-dir.h
B3
1A
DATA0.h
Data bit 1 connected to host. Referenced to VCCA.
D3
56DIR
(tie-high)
Direction control for 5A/5B and 6A/6B. Not used in this mode. Tie to VCCA.
E3
GND
GND
Ground
Output pin not used in this mode. Do not use. Leave unconnected.
Direction control for 4A/4B
C3
PIN
TYPE
I/O
Power
Output
I/O
Input
I/O
Depopulated ball
Input
F3
12A
DNU
G3
11A
(tie-low)
Input pin not used in this mode. Tie to GND.
Output
Input
A4
2DIR
DATU-dir.h
Direction control for 2A/2B connected to host
Input
B4
1DIR
DAT0-dir.h
Direction control for 1A/1B connected to host
Input
C4
3DIR
DATU-dir.h
Direction control for 3A/3B connected to host
Input
D4
GND
GND
Ground
E4
CS0
CS0.h
Card select from host. Active low. When CS0 = high, 1A, 2A, 3A, 4A, 1B, 2B, 3B, 4B, 9A,
9B1, and 10A2 are placed in Hi Z and 10B1 is low.
Input
F4
13A
(tie-low)
Input pin not used in this mode. Tie to GND.
Input
G4
CS1
(tie-high)
Card select signal. Not used in this mode. Tie to VCCA for proper operation.
Input
A5
MODE1
(tie-low)
Input
MODE1, MODE0 determine mode of operation (see Table 1). Tie to GND in this mode.
B5
MODE0
(tie-low)
C5
GND
GND
D5
4B
DATA3
E5
GND
GND
Ground
F5
7B
DNU
I/O pin not used in this mode. Leave unconnected.
Input
Ground
Data bit 4 connected to card. Referenced to VCCB0.
I/O
I/O
G5
8B
DNU
I/O pin not used in this mode. Leave unconnected.
A6
10B1
SCLK
Clock signal connected to card
Output
B6
9B1
BS
Bus state signal connected to card
Output
C6
2B
DATA1
Data bit 2 connected to card. Referenced to VCCB0.
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I/O
I/O
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 7. Memory Stick (Continued)
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
D6
11B
E6
F6
PIN
TYPE
DNU
Output pin not used in this mode. Leave unconnected.
Output
10B2
DNU
Output pin not used in this mode. Leave unconnected.
Output
5B
DNU
I/O pin not used in this mode. Leave unconnected.
I/O pin not used in this mode. Leave unconnected.
G6
6B
DNU
A7
VCCB0
VCCB0
B-port supply voltage. VCCB0 powers 1B, 2B, 3B, 4B, 9B1, and 10B1.
B7
1B
DATA0
Data bit 1 connected to card. Referenced to VCCB0.
I/O
I/O
Power
I/O
C7
3B
DATA2
Data bit 3 connected to card. Referenced to VCCB0.
D7
12B
(tie-low)
Input pin not used in this mode. Tie to GND.
E7
9B2
DNU
I/O pin not used in this mode. Leave unconnected.
F7
14B
DNU
Open-drain output not used in this mode. Leave unconnected.
Output
B-port supply voltage. VCCB1 powers 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B, and 14B. Not
used in this mode. Tie to GND.
Power
G7
20
PIN FUNCTION
VCCB1
(tie-low)
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I/O
Input
I/O
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
CONFIGURATION 1 FUNCTION TABLE
(MODE0 = L, MODE1 = L)
INPUTS
SIGNAL
Clock
OPERATION
CS1
9DIR
(1-4)DIR
H
H
X
X
CLK.0 and CLK.1 forced low,
CLK-f.h forced Hi Z
SCLK.0 and SCLK.1 forced low,
SCLK-f.h forced Hi Z
L
L
X
X
CLK.h to CLK.0 and
CLK.1, CLK.0 to CLK-f.h
SCLK.h to SCLK.0 and
SCLK.1, SCLK.0 to SCLK-f.h
L
H
X
X
CLK.h to CLK.0,
CLK.0 to CLK-f.h,
CLK.1 forced low
SCLK.h to SCLK.0,
SCLK.0 to SCLK-f.h,
SCLK.1 forced low
H
L
X
X
CLK.h to CLK.1,
CLK.1 to CLK-f.h,
CLK.0 forced low
SCLK.h to SCLK.1,
SCLK.1 to SCLK-f.h,
SCLK.0 forced low
H
H
X
X
All data I/Os are Hi Z (isolation mode).
All data I/Os are Hi Z (isolation mode).
L
DAT0.0 and DAT0.1 to DAT0.h,
DAT1.0 and DAT1.1 to DAT1.h,
DAT2.0 and DAT2.1 to DAT2.h,
DAT3.0 and DAT3.1 to DAT3.h
DATA0.0 and DATA0.1 to DATA0.h,
DATA1.0 and DATA1.1 to DATA1.h,
DATA2.0 and DATA2.1 to DATA2.h,
DATA3.0 and DATA3.1 to DATA3.h
H
DAT0.h to DAT0.0 and to DAT0.1,
DAT1.h to DAT1.0 and to DAT1.1,
DAT2.h to DAT2.0 and to DAT2.1,
DAT3.h to DAT3.0 and to DAT3.1
DATA0.h to DATA0.0 and to DATA0.1,
DATA1.h to DATA1.0 and to DATA1.1,
DATA2.h to DATA2.0 and to DATA2.1,
DATA3.h to DATA3.0 and to DATA3.1
DATA0.0 to DATA0.h,
DATA1.0 to DATA1.h,
DATA2.0 to DATA2.h,
DATA3.0 to DATA3.h
L†
L†
L†
L†
X
X
MMC/SD
L
H
X
L
DAT0.0 to DAT0.h,
DAT1.0 to DAT1.h,
DAT2.0 to DAT2.h,
DAT3.0 to DAT3.h
L
H
X
H
DAT0.h to DAT0.0,
DAT1.h to DAT1.0,
DAT2.h to DAT2.0,
DAT3.h to DAT3.0
DATA0.h to DATA0.0,
DATA1.h to DATA1.0,
DATA2.h to DATA2.0,
DATA3.h to DATA3.0
L
DAT0.1 to DAT0.h,
DAT1.1 to DAT1.h,
DAT2.1 to DAT2.h,
DAT3.1 to DAT3.h
DATA0.1 to DATA0.h,
DATA1.1 to DATA1.h,
DATA2.1 to DATA2.h,
DATA3.1 to DATA3.h
DATA0.h to DATA0.1,
DATA1.h to DATA1.1,
DATA2.h to DATA2.1,
DATA3.h to DATA3.1
Data
H
Command
Memory Stick/
Memory Stick PRO
CS0
L
X
H
L
X
H
DAT0.h to DAT0.1,
DAT1.h to DAT1.1,
DAT2.h to DAT2.1,
DAT3.h to DAT3.1
H
H
X
X
CMD.h, CMD.0, and CMD.1 are Hi Z
(isolation mode).
BS.h, BS.0, and BS.1 are Hi Z
(isolation mode).
L
L
H
X
CMD.h to CMD.0 and CMD.1
BS.h to BS.0 and BS.1
L
L
L
X
CMD.0 and CMD.1 to CMD.h
BS.0 and BS.1 to BS.h
L
H
H
X
CMD.h to CMD.0
BS.h to BS.0
L
H
L
X
CMD.0 to CMD.h
BS.0 to BS.h
H
L
H
X
CMD.h to CMD.1
BS.h to BS.1
H
L
L
X
CMD.1 to CMD.h
† Broadcast mode in which the host writes to or reads from both cards in parallel
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BS.1 to BS.h
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
CONFIGURATION 1 FUNCTION TABLE (continued)
(MODE0 = L, MODE1 = L)
INPUTS
SIGNAL
Interrupt request
OPERATION
MMC/SD
CS1
9DIR
(1-4)DIR
H
H
X
X
DAT1.0 and DAT1.1 to IRQ.
IRQ is an open-drain output.
DATA1.0 and DATA1.1 to IRQ.
IRQ is an open-drain output.
L
H
X
X
DAT1.1 to IRQ.
IRQ is an open-drain output.
DATA1.1 to IRQ.
IRQ is an open-drain output.
H
L
X
X
DAT1.0 to IRQ.
IRQ is an open-drain output.
DATA1.0 to IRQ.
IRQ is an open-drain output.
L
L
X
X
IRQ is Hi Z.
† Broadcast mode in which the host writes to or reads from both cards in parallel.
22
Memory Stick/
Memory Stick PRO
CS0
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IRQ is Hi Z.
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
configuration 2 – interfacing with SD/SDIO card and using GPIOs for level shifting
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 8. SD/SDIO Card Using GPIOs for Level Shifting
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
A1
VCCA
VCCA
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
B1
10A1
CLK.h
Clock signal from host
C1
9A
CMD.h
Command signal connected to host
PIN FUNCTION
Power
Input
I/O
D1
9DIR
CMD-dir.h
Direction control for 9A/9B connected to host
Input
E1
78DIR
I/O23-dir.h
Direction control for 7A/7B and 8A/8B. Connected to host. Tie to VCCA if unused.
Input
F1
7A
I/O2.h
General-purpose I/O. Referenced to VCCA. Tie to VCCA or GND if unused.
G1
VCCA
VCCA
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
A2
2A
DAT1.h
Data bit 2 connected to host. Referenced to VCCA.
I/O
B2
3A
DAT2.h
Data bit 3 connected to host. Referenced to VCCA.
I/O
C2
10A2
CLK-f.h
Clock feedback to host for resynchronizing data. Used in OMAP processors. Optional on
other processors. Leave unconnected if not used.
D2
4A
DAT3.h
Data bit 4 connected to host. Referenced to VCCA.
I/O
E2
6A
I/O1.h
General-purpose I/O. Referenced to VCCA. Tie to VCCA or GND if unused.
I/O
F2
8A
I/O3.h
General-purpose I/O. Referenced to VCCA. Tie to VCCA or GND if unused.
I/O
General-purpose I/O. Referenced to VCCA. Tie to VCCA or GND if unused.
G2
5A
I/O0.h
A3
4DIR
DAT3-dir.h
B3
1A
DAT0.h
D3
56DIR
I/O01-dir.h
E3
GND
GND
Ground
Direction control for 4A/4B
I/O
Power
Output
I/O
Input
Data bit 1 connected to host. Referenced to VCCA.
C3
24
PIN
TYPE
I/O
Depopulated ball
Direction control for 5A/5B and 6A/6B. Referenced to VCCA. Tie to VCCA if unused.
Input
F3
12A
O5.h
General-purpose output connected to host. Referenced to VCCA.
G3
11A
I4.h
General-purpose input connected to host. Referenced to VCCA.
Output
Input
A4
2DIR
DAT1-dir.h
Direction control for 2A/2B connected to host
Input
B4
1DIR
DAT0-dir.h
Direction control for 1A/1B connected to host
Input
C4
3DIR
DAT2-dir.h
Direction control for 3A/3B connected to host
Input
D4
GND
GND
Ground
E4
CS0
CS0.h
Card select from host. Active low. When CS0 = high, 1A, 2A, 3A, 4A, 1B, 2B, 3B, 4B, 9A, 9B,
and 10A2 are placed in Hi Z and 10B1 is low.
Input
F4
13A
I6.h
General-purpose input connected to host. Referenced to VCCA.
Input
G4
CS1
(tie-low)
Card select. Tie to GND for proper operation.
Input
A5
MODE1
(tie-low)
MODE1, MODE0 determine mode of operation (see Table 1). Tie MODE0 to VCCA. Tie
MODE1 to GND.
Input
B5
MODE0
(tie-high)
C5
GND
GND
Ground
D5
4B
DAT3
Data bit 4 connected to card. Referenced to VCCB0.
E5
GND
GND
Ground
F5
7B
I/O2
General-purpose I/O. Referenced to VCCB1.
Input
I/O
I/O
G5
8B
I/O3
General-purpose I/O. Referenced to VCCB1.
A6
10B1
CLK
Clock signal connected to card
Output
B6
9B1
CMD
Command signal connected to card
Output
C6
2B
DAT1
Data bit 2 connected to card. Referenced to VCCB0.
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 8. SD/SDIO Card Using GPIOs for Level Shifting (Continued)
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
D6
11B
O4
General-purpose output. Referenced to VCCB1.
Output
E6
10B2
O6
General-purpose output. Referenced to VCCB1.
Output
F6
5B
I/O0
General-purpose I/O. Referenced to VCCB1.
General-purpose I/O. Referenced to VCCB1.
PIN FUNCTION
PIN
TYPE
I/O
G6
6B
I/O1
A7
VCCB0
VCCB0
B7
1B
DAT0
Data bit 1 connected to card. Referenced to VCCB0.
C7
3B
DAT2
Data bit 3 connected to card. Referenced to VCCCB0.
D7
12B
I5
E7
9B2
DNU
I/O pin not used in this mode. Leave unconnected.
Open-drain output not used in this mode. Leave unconnected.
Output
B-port supply voltage. VCCB1 powers 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B, and 14B.
Power
F7
14B
DNU
G7
VCCB1
VCCB1
B-port supply voltage. VCCB0 powers 1B, 2B, 3B, 4B, 9B1, and 10B1.
General-purpose Input. Referenced to VCCB1.
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I/O
Power
I/O
I/O
Input
I/O
25
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
CONFIGURATION 2 FUNCTION TABLE
(MODE0 = H, MODE1 = L)
INPUTS
SIGNAL
OPERATION
CS1
9DIR
(1-4)DIR
56DIR
78DIR
H
H
X
X
X
X
CLK forced low,
CLK-f.h forced Hi Z
SCLK forced low,
SCLK-f.h forced Hi Z
L
L
X
X
X
X
CLK.h to CLK,
CLK to CLK-f.h
SCLK.h to SCLK,
SCLK to SCLK-f.h
H
H
X
X
X
X
All data I/Os are Hi Z
(isolation mode).
All data I/Os are Hi Z
(isolation mode).
X
DAT0 to DAT0.h,
DAT1 to DAT1.h,
DAT2 to DAT2.h,
DAT3 to DAT3.h
DATA0 to DATA0.h,
DATA1 to DATA1.h,
DATA2 to DATA2.h,
DATA3 to DATA3.h
DATA0.h to DATA0,
DATA1.h to DATA1,
DATA2.h to DATA2,
DATA3.h to DATA3
Clock
L
L
X
L
X
Data
Command
L
L
X
H
X
X
DAT0.h to DAT0,
DAT1.h to DAT1,
DAT2.h to DAT2,
DAT3.h to DAT3
H
H
X
X
X
X
CMD.h and CMD are Hi Z
(isolation mode).
BS.h and BS are Hi Z
(isolation mode).
L
L
L
X
X
X
CMD to CMD.h
BS to BS.h
L
L
H
X
X
X
CMD.h to CMD
BS.h to BS
H
H
X
X
X
X
All GPIOs are Hi Z.
All GPIOs are Hi Z.
L
L
X
X
X
X
I4 to O4,
I5 to O5,
I6 to O6
I4 to O4,
I5 to O5,
I6 to O6
L
L
X
X
L
X
I/O0 to I/O0.h,
I/O1 to I/O1.h
I/O0 to I/O0.h,
I/O1 to I/O1.h
L
L
X
X
H
X
I/O0.h to I/O0,
I/O1.h to I/O1
I/O0.h to I/O0,
I/O1.h to I/O1
L
L
X
X
X
L
I/O2 to I/O2.h,
I/O3 to I/O3.h
I/O2 to I/O2.h,
I/O3 to I/O3.h
L
L
X
X
X
H
I/O2.h to I/O2,
I/O3.h to I/O3
I/O2.h to I/O2,
I/O3.h to I/O3
GPIO
26
MMC/SD
Memory Stick/
Memory Stick PRO
CS0
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
configuration 3 – interfacing with 8-bit MMC
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 9. 8-Bit MMC
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
A1
VCCA
VCCA
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
B1
10A1
CLK.h
Clock signal from host
C1
9A
CMD.h
Command signal connected to host
PIN FUNCTION
Power
Input
I/O
D1
9DIR
CMD-dir.h
Direction control for 9A/9B connected to host
Input
E1
78DIR
DATU-dir.h
Direction control for 7A/7B and 8A/8B. Connected to host.
Input
F1
7A
DAT6.h
General-purpose I/O. Referenced to VCCA.
G1
VCCA
VCCA
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
A2
2A
DAT1.h
Data bit 2 connected to host. Referenced to VCCA.
I/O
B2
3A
DAT2.h
Data bit 3 connected to host. Referenced to VCCA.
I/O
C2
10A2
CLK-f.h
Clock feedback to host for resynchronizing data. Used in OMAP processors. Optional on
other processors. Leave unconnected if not used.
D2
4A
DAT3.h
Data bit 4 connected to host. Referenced to VCCA.
I/O
E2
6A
DAT5.h
General-purpose I/O. Referenced to VCCA.
I/O
F2
8A
DAT7.h
General-purpose I/O. Referenced to VCCA.
I/O
General-purpose I/O. Referenced to VCCA.
G2
5A
DAT4.h
A3
4DIR
DAT3-dir.h
B3
1A
DAT0.h
D3
56DIR
DATU-dir.h
E3
GND
GND
Ground
Output pin not used in this mode. Do not use. Leave unconnected.
Direction control for 4A/4B
I/O
Power
Output
I/O
Input
Data bit 1 connected to host. Referenced to VCCA.
C3
28
PIN
TYPE
I/O
Depopulated ball
Direction control for 5A/5B and 6A/6B. Referenced to VCCA.
Input
F3
12A
DNU
G3
11A
(tie-low)
Input pin not used in this mode. Tie to GND.
Output
Input
A4
2DIR
DAT1-dir.h
Direction control for 2A/2B connected to host
Input
B4
1DIR
DAT0-dir.h
Direction control for 1A/1B connected to host
Input
C4
3DIR
DAT2-dir.h
Direction control for 3A/3B connected to host
Input
D4
GND
GND
Ground
E4
CS0
CS0.h
Card select from host. Active low. When CS0 = high, 1A, 2A, 3A, 4A, 1B, 2B, 3B, 4B, and 9B1
are placed in Hi Z, and 10B1 is low.
Input
F4
13A
(tie-low)
Input pin not used in this mode. Tie to GND.
Input
G4
CS1
(tie-low)
Card select signal. For proper operation, tie to GND.
Input
A5
MODE1
(tie-low)
MODE1, MODE0 determine mode of operation (see Table 1). Tie MODE0 to VCCA. Tie
MODE1 to GND.
Input
B5
MODE0
(tie-high)
C5
GND
GND
Ground
D5
4B
DAT3
Data bit 4 connected to card. Referenced to VCCB.
E5
GND
GND
Ground
F5
7B
DAT6
Data bit 6 connected to card. Referenced to VCCB.
G5
8B
DAT7
Data bit 7 connected to card. Referenced to VCCB.
A6
10B1
CLK
Clock signal connected to card
Output
B6
9B1
CMD
Command signal connected to card
Output
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Input
I/O
I/O
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 9. 8-Bit MMC (Continued)
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
C6
2B
DAT1
Data bit 2 connected to card. Referenced to VCCB0.
D6
11B
DNU
Output pin not used in this mode. Leave unconnected.
Output
E6
10B2
DNU
Output pin not used in this mode. Leave unconnected.
Output
PIN FUNCTION
PIN
TYPE
I/O
F6
5B
DAT4
Data bit 4 connected to card. Referenced to VCCB.
I/O
G6
6B
DAT5
Data bit 5 connected to card. Referenced to VCCB.
I/O
A7
VCCB0
VCCB0
B-port supply voltage. VCCB0 powers 1B, 2B, 3B, 4B, 9B1, and 10B1.
Power
B7
1B
DAT0
Data bit 1 connected to card. Referenced to VCCB0.
I/O
C7
3B
DAT2
Data bit 3 connected to card. Referenced to VCCB0.
I/O
D7
12B
(tie-low)
E7
9B2
DNU
I/O pin not used in this mode. Leave unconnected.
F7
14B
DNU
Open-drain output not used in this mode. Leave unconnected.
Output
G7
VCCB1
VCCB1
B-port supply voltage. VCCB1 powers 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B and 14B. Not used
in this mode. Tie to GND.
Power
Input pin not used in this mode. Tie to GND.
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Input
I/O
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
CONFIGURATION 3 FUNCTION TABLE
(MODE0 = H, MODE1 = L, 8-bit MMC)
INPUTS
SIGNAL
Clock
CS1
9DIR
(1-4)DIR
56DIR
78DIR
L
X
X
X
X
X
CLK.h to CLK, CLK to CLK-f.h
H
X
X
X
X
X
DAT0.h, DAT1.h, DAT2.h, DAT3.h, DAT0, DAT1, DAT2,
and DAT3 are Hi Z.
X
H
X
X
X
X
DAT4.h, DAT5.h, DAT6.h, DAT7.h, DAT4, DAT5, DAT6,
and DAT7 are Hi Z.
L
DAT0 to DAT0.h,
DAT1 to DAT1.h,
DAT2 to DAT2.h,
DAT3 to DAT3.h,
DAT4 to DAT4.h,
DAT5 to DAT5.h,
DAT6 to DAT6.h,
DAT7 to DAT7.h
L
L
X
L
L
Data
Command
30
OPERATION
CS0
L
L
X
H
H
H
DAT0.h to DAT0,
DAT1.h to DAT1,
DAT2.h to DAT2,
DAT3.h to DAT3,
DAT4.h to DAT4,
DAT5.h to DAT5,
DAT6.h to DAT6,
DAT7.h to DAT7
H
X
X
X
X
X
CMD.h and CMD are Hi Z (isolation mode).
L
X
L
X
X
X
CMD to CMD.h
L
X
H
X
X
X
CMD.h to CMD
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
configuration 4 – interfacing with SmartMedia or xD-Picture Card
A Side
B Side
VCCA
VCCB
AVCA406
Host
SmartMedia/
xD-Picture
Card
Table 10. SmartMedia or xD-Picture Card
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
A1
VCCA
VCCA
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
B1
10A1
/RE.h
Read enable connected to host
Input
C1
9A
CLE.h
Command latch enable connected to host
Input
D1
9DIR
(tie-low)
Input pin not used in this mode. Tie to GND.
Input
E1
78DIR
I/O-dir.h
Data direction control from host
Input
PIN FUNCTION
PIN
TYPE
Power
F1
7A
I/O7.h
Data I/O 7 connected to host. Referenced to VCCA.
G1
VCCA
VCCA
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
I/O
A2
2A
I/O2.h
Data I/O 2 connected to host. Referenced to VCCA.
I/O
B2
3A
I/O3.h
Data I/O 3 connected to host. Referenced to VCCA.
I/O
Power
C2
10A2
/RE-f.h
Read enable feedback to host. Used with OMAP processors. Use with other processors is
optional. Leave unconnected if not used.
D2
4A
I/O4.h
Data I/O 4 connected to host. Referenced to VCCA.
I/O
E2
6A
I/O6.h
Data I/O 6 connected to host. Referenced to VCCA.
I/O
F2
8A
I/O8.h
Data I/O 8 connected to host. Referenced to VCCA.
I/O
Data I/O 5 connected to host. Referenced to VCCA.
G2
5A
I/O5.h
A3
4DIR
I/O-dir.h
B3
1A
I/O1.h
Data direction control connected to host
Data I/O 1 connected to host. Referenced to VCCA.
C3
Output
I/O
Input
I/O
Depopulated ball
D3
56DIR
I/O-dir.h
Data direction control connected to host
E3
GND
GND
Ground
F3
12A
R/B.h
Read/busy connected to host. Open-drain output.
G3
11A
/WP.h
Write protect connected to host
Input
A4
2DIR
I/O-dir.h
Data direction control connected to host
Input
B4
1DIR
I/O-dir.h
Data direction control connected to host
Input
C4
3DIR
I/O-dir.h
Data direction control connected to host
Input
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Input
Output
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
Table 10. SmartMedia or xD-Picture Card (Continued)
PIN
NO.
PIN
NAME
SIGNAL NAME
OR
(CONNECTION)
D4
GND
GND
Ground
E4
CS0
/CE.h
Chip enable from host
Input
F4
13A
/WE.h
Write enable from host
Input
Address latch enable connected to host
Input
32
G4
CS1
ALE.h
A5
MODE1
(tie-high)
PIN FUNCTION
PIN
TYPE
Input
MODE1, MODE0 determine mode of operation (see Table 1). Tie to VCCA.
B5
MODE0
(tie-high)
C5
GND
GND
Ground
D5
4B
I/O4
Data I/O 4 connected to card. Referenced to VCCB.
E5
GND
GND
Ground
Input
I/O
F5
7B
I/O7
Data I/O 7 connected to card. Referenced to VCCB.
I/O
G5
8B
I/O8
Data I/O 8 connected to card. Referenced to VCCB.
I/O
A6
10B1
/RE
Read enable connected to card
Output
B6
9B1
CLE
Command latch enable connected to card
Output
C6
2B
I/O2
Data I/O 2 connected to card. Referenced to VCCB.
D6
11B
/WP
Write protect connected to card
Output
E6
10B2
/WE
Write enable connected to card
Output
F6
5B
I/O5
Data I/O 5 connected to card. Referenced to VCCB.
Data I/O 6 connected to card. Referenced to VCCB.
I/O
I/O
G6
6B
I/O6
A7
VCCB0
VCCB
B7
1B
I/O1
Data I/O 1 connected to card. Referenced to VCCB.
C7
3B
I/O3
Data I/O 3 connected to card. Referenced to VCCB.
D7
12B
R/B
Read/busy connected to card
E7
9B2
ALE
Address latch enable connected to host
F7
14B
/CE
Chip enable connected to card
Output
G7
VCCB1
VCCB
B-port supply voltage. VCCB1 powers 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B, and 14B.
Power
B-port supply voltage. VCCB0 powers 1B, 2B, 3B, 4B, 9B1, and 10B1.
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I/O
Power
I/O
I/O
Input
I/O
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
CONFIGURATION 4 FUNCTION TABLE
(MODE0 = H, MODE1 = H, 8-bit SmartMedia/xD-Picture Card)
INPUTS
SIGNAL
OPERATION
CS0
CS1
9DIR
(1−4)DIR
56DIR
78DIR
X
X
X
X
X
X
WE.h to WE
L
X
X
X
X
X
RE.h to RE, RE to RE-f.h
H
X
X
X
X
X
All data I/Os are Hi Z (isolation mode).
L
X
X
L
L
L
I/O(1−8) to I/O(1−8).h
L
X
X
H
H
H
I/O(1−8).h to I/O(1−8)
Command
X
X
X
X
X
X
CLE.h to CLE, ALE.h to ALE
Interrupt request
X
X
X
X
X
X
CE.h to CE
Others
X
X
X
X
X
X
WP.h to WP, R/B to R/B.h (R/B.h is an open-drain output)
Clock
Data
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
logic diagrams (positive logic)
CLK Path
CTRL†
TP‡
10A1
CTRL†
10B1
CTRL†
TP‡
13A
CTRL†
CTRL†
TP‡
10A2
TP‡
† CTRL represents a decoded MODE0, MODE1, CS0, and CS1 state.
‡ Translation point
34
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10B2
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
logic diagrams (positive logic) (continued)
Data Path
DIR
(1, 2, 3, 4)
TP‡
CTRL†
CTRL†
A
(1, 2, 3, 4)
CTRL†
TP‡
CTRL†
DIR
(5, 6, 7, 8)
CTRL†
B
(1, 2, 3, 4)
TP‡
TP‡
TP‡
B
(5, 6, 7, 8)
CTRL†
CTRL†
TP‡
A
(5, 6, 7, 8)
TP‡
† CTRL represents a decoded MODE0, MODE1, CS0, and CS1 state.
‡ Translation point
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
logic diagrams (positive logic) (continued)
CMD Path
9DIR
TP‡
CTRL†
CTRL†
TP‡
CTRL†
TP‡
9A
CTRL†
9B1
TP‡
TP‡
CTRL†
TP‡
CS1
† CTRL represents a decoded MODE0, MODE1, CS0, and CS1 state.
‡ Translation point
WP and R/B Paths
11A
TP‡
11B
TP‡
12B
CTRL†
12A
§
† CTRL represents a decoded MODE0, MODE1, CS0, and CS1 state.
‡ Translation point
§ 12A is open drain in NAND (XD) mode and push-pull in other modes.
36
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9B2
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
logic diagrams (positive logic) (continued)
IRQ and CEout Paths
CTRL†
2B
CTRL†
‡
6B
14B
CS0
† CTRL represents a decoded MODE0, MODE1, CS0, and CS1 state.
‡ Push-pull in NAND flash (XD) mode and open drain in other modes
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCCA and VCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1): I/O ports (A port) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCA + 0.5 V
I/O ports (B port) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCB + 0.5 V
Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCA + 0.5 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCB + 0.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCA + 0.5 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCB + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCCA, VCCB, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
recommended operating conditions (see Notes 4 through 7)
VCCI
VCCA
VCCB
VCCO
MIN
MAX
UNIT
Supply voltage
1.4
1.4
VCCB
3.6
V
Supply voltage
VCCI × 0.65
1.7
1.4 V to 1.95 V
VIH
High-level input voltage
All inputs†
1.95 V to 2.7 V
2.7 V to 3.6 V
Low-level input voltage
All inputs†
VCCI × 0.35
0.7
1.95 V to 2.7 V
2.7 V to 3.6 V
VI
VO
IOH
IOL
IOH
0
Active state
0
3-state
0
High-level output current (A port)
Low-level output current (A port)
High-level output current (B port)
IOL
Low-level output current (B port)
∆t/∆v
Input transition rise or fall rate
V
0.8
Input voltage
Output voltage
V
2
1.4 V to 1.95 V
VIL
V
VCCI
VCCO
VCCO
1.4 V to 1.6 V
−1
1.65 V to 1.95 V
−2
2.3 V to 2.7 V
−4
3 V to 3.6 V
−8
1.4 V to 1.6 V
1
1.65 V to 1.95 V
2
2.3 V to 2.7 V
4
3 V to 3.6 V
8
1.4 V to 1.6 V
−2
1.65 V to 1.95 V
−4
2.3 V to 2.7 V
−8
3 V to 3.6 V
−16
1.4 V to 1.6 V
2
1.65 V to 1.95 V
4
2.3 V to 2.7 V
8
3 V to 3.6 V
16
5
V
V
mA
mA
mA
mA
ns/V
TA
Operating free-air temperature
−40
85
°C
† All A-port I/Os and control inputs are powered by VCCA.
1B, 2B, 3B, 4B, 9B1, and 10B1 are powered by VCCB0. 5B, 6B, 7B, 8B, 9B2, 10B2, 11B, 12B, and 14B are powered by VCCB1.
NOTES: 4. VCCI is the VCC associated with the data input port.
5. VCCO is the VCC associated with the output port.
6. VCCB must be greater than or equal to VCCA, except when VCCB = 0 V.
7. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted) (see Notes 8 and 9)
PARAMETER
TEST CONDITIONS
VOL (B port)
1.4 V to 3.6 V
1.4 V
1.65 V
1.65 V
1.2
2.3 V
2.3 V
1.75
3V
3V
2.3
1.4 V to 3.6 V
1.4 V to 3.6 V
0.2
1.4 V
1.4 V
0.35
1.65 V
1.65 V
0.45
2.3 V
2.3 V
0.55
3V
3V
0.7
3V
3V
0.45
1.4 V to 3.6 V
1.4 V to 3.6 V
1.4 V
1.4 V
1.65 V
1.65 V
1.2
IOH = −8 mA
IOH = −16 mA
2.3 V
2.3 V
1.75
3V
3V
2.3
IOL = 100 µA
IOL = 2 mA
1.4 V to 3.6 V
1.4 V to 3.6 V
0.2
1.4 V
1.4 V
0.35
1.65 V
1.65 V
0.45
2.3 V
2.3 V
0.55
3V
3V
0.7
3V
3V
0.45
1.4 V to 3.6 V
3.6 V
±2.5
µA
0 to 3.6 V
0V
±10
µA
3.6 V
±10
0V
±10
1.6 V
1.6 V
4.5
1.95 V
1.95 V
5
1.95 V
0V
2.7 V
2.7 V
5.5
3.6 V
0V
10
3.6 V
3.6 V
10
1.6 V
1.6 V
6.5
1.95 V
1.95 V
1.95 V
0V
0.5
2.7 V
2.7 V
7.5
IOH = −2 mA
IOH = −4 mA
IOL = 1 mA
IOL = 2 mA
VI = VIH
Control inputs
14B
A or B ports
IOZ‡
ICCA
ICCB
A port
VI = VIL
IOL = 4 mA
IOL = 8 mA
IOH = −2 mA
IOH = −4 mA
IOL = 4 mA
IOL = 8 mA
IOL = 16 mA
IOL = 2 mA
II
Ioff
Open-drain output (12A)
VI = VIH
VI = VIL
Open-drain output (14B)
VI = VCCA or GND
VO = VCCA
VO = VCCO or GND, See function table for
input states when
VI = VIH or VIL
outputs are Hi Z
VI = VCCI or GND,
VI = VCCI or GND,
IO = 0
IO = 0
3.6 V
POST OFFICE BOX 655303
VCCO − 0.2 V
1.05
V
V
5
V
µA
A
µA
A
7
0V
1
3.6 V
3.6 V
10
• DALLAS, TEXAS 75265
V
VCCO − 0.2 V
1.05
3.6 V
† All typical values are at TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
NOTES: 8. VCCO is the VCC associated with the output port.
9. VCCI is the VCC associated with the data input port.
40
UNIT
1.4 V
IOL = 2 mA
IOH = −100 µA
VOH (B port)
MAX
1.4 V to 3.6 V
IOH = −8 mA
IOL = 100 µA
VOL (A port)
TYP†
VCCB
IOH = −100 µA
IOH = −1 mA
VOH (A port)
MIN
VCCA
µA
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted) (see Notes 8 and 9) (continued)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
VI = VCCA or GND
1.8 V
3V
VO = VCCB or GND
VO = VCCA or GND
1.8 V
3V
A port
B port
VO = VCCB or GND
Control inputs
Ci
Clock input
Co
14B
Cio
MIN
TYP†
MAX
UNIT
3.5
pF
4
17.5
pF
4.5
1.8 V
3V
pF
11
† All typical values are at TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
NOTES: 8. VCCO is the VCC associated with the output port.
9. VCCI is the VCC associated with the data input port.
output slew rates over recommended operating free-air temperature range (unless otherwise noted§
PARAMETER
FROM
TO
tr
20%
80%
VCCA = 1.8 V
± 0.15 V,
VCCB = 3 V
± 0.3 V
MIN
tf
80%
20%
§ Values are characterized but not production tested.
¶ Using CL = 15 pF on the B side and CL = 7 pF on the A side. See derating curves for other load conditions.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
3¶
ns
3¶
ns
41
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
switching characteristics over recommended operating free-air temperature range,
VCCA = 1.5 V ± 0.1 V (see Figure 5)
PARAMETER
tpd
ten
tdis
FROM
(INPUT)
TO
(OUTPUT)
A
B
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3 V
± 0.3 V
VCCB = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1
7.7
1
4.9
1
4.7
1
4.4
A
1
6.3
1
5
1
5
1
5
CLK.h or SCLK.h
CLK.0 or SCLK.0
1
7.7
1
5
1
4.9
1
4.9
CLK.h or SCLK.h
CLK-f.h or SCLK-f.h
2
19
2
12
2
10
2
9.7
CMD.h
CMD.0
1
7.1
1
4.1
1
3.9
1
3.6
CMD.h
CMD.1
1
7
1
4.6
1
4.1
1
4.2
CMD.0
CMD.h
1
6.2
1
4.9
1
4.8
1
4.7
CS0
B
1
6
1
4.2
1
4.2
1
3.9
R/B
R/B.h
1
5.7
1
4.8
1
4.7
1
4.8
WE
WE.h
1
7.4
1
4.3
1
4.3
1
4.2
WP
WP.h
1
6.6
1
4.5
1
4.4
1
4.3
DAT1.0 or DATA1.0
IRQ
1
4.8
1
3.3
1
3.3
1
3.3
DAT1.1 or DATA1.1
IRQ
1
4.9
1
3.4
1
3.3
1
3.3
DIR
B
1
6.7
1
4.5
1
4.4
1
4.6
DIR
A
1
10.3
1
9.6
1
9.6
1
9.5
R/B
R/B.h (open drain)
1
5.9
1
5.4
1
5.4
1
5.4
DAT1.0 or DATA1.0
IRQ
1
6.7
1
4.9
1
5.5
1
5.5
DAT1.1 or DATA1.1
IRQ
1
6.5
1
4.7
1
5.4
1
5.4
DIR
B
1
6.9
1
6.4
1
6.4
1
6.3
DIR
A
1
5.3
1
5.3
1
5.3
1
5.2
R/B
R/B.h (open drain)
1
16.9
1
17.4
1
5.3
1
4.1
UNIT
ns
ns
ns
maximum frequency and output skew over recommended operating free-air temperature range,
VCCA = 1.5 V ± 0.1 V (see Figure 5)
PARAMETER
Clock
fmax
Data
tsk(o)
42
VCCB = 3 V
± 0.3 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
52
52
B
A
52
52
A
B
26
26
B
A
26
A
B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
MIN
UNIT
MAX
MHz
26
1.5
1.5
ns
E E
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
switching characteristics over recommended operating free-air temperature range,
VCCA = 1.8 V ± 0.15 V (see Figure 5)
PARAMETER
tpd
ten
tdis
FROM
(INPUT)
TO
(OUTPUT)
A
B
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3 V
± 0.3 V
VCCB = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1
7.5
1
4.6
1
4.1
1
3.7
A
1
4.6
1
4.2
1
4.1
1
4
CLK.h or SCLK.h
CLK.0 or SCLK.0
1
8
1
4.8
1
4.3
1
4.2
CLK.h or SCLK.h
CLK-f.h or SCLK-f.h
2
17.9
2
9.4
2
8.7
2
8.3
CMD.h
CMD.0
1
7.4
1
3.7
1
3.3
1
3.3
CMD.h
CMD.1
1
6.2
1
4.4
1
3.7
1
3.5
CMD.0
CMD.h
1
4.5
1
4
1
3.8
1
3.8
CS0
B
1
6.6
1
4
1
4
1
3.8
R/B
R/B.h
1
4.4
1
4
1
3.8
1
3.8
WE
WE.h
1
7.3
1
3.9
1
3.8
1
3.7
WP
WP.h
1
5.6
1
4
1
3.6
1
3.8
DAT1.0 or DATA1.0
IRQ
1
5
1
3.3
1
3.3
1
3.3
DAT1.1 or DATA1.1
IRQ
1
4.6
1
3.1
1
3.1
1
3.1
DIR
B
1
6.4
1
3.8
1
3.6
1
3.6
DIR
A
1
7.7
1
6.9
1
6.9
1
6.9
R/B
R/B.h (open drain)
1
4.4
1
4.1
1
4.1
1
4.1
DAT1.0 or DATA1.0
IRQ
1
6.5
1
4.8
1
5.5
1
5.5
DAT1.1 or DATA1.1
IRQ
1
6.6
1
4.8
1
5.3
1
5.3
DIR
B
1
6.3
1
5.4
1
5.7
1
5.7
DIR
A
1
5.2
1
5.3
1
5.2
1
5.2
R/B
R/B.h (open drain)
1
15.9
1
19.5
1
5.6
1
3.8
UNIT
ns
ns
ns
maximum frequency and output skew over recommended operating free-air temperature range,
VCCA = 1.8 V ± 0.15 V (see Figure 5)
PARAMETER
Clock
fmax
Data
tsk(o)
VCCB = 3 V
± 0.3 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
52
52
B
A
52
52
A
B
26
26
B
A
26
A
B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
MIN
UNIT
MAX
MHz
26
0.8
0.8
ns
43
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
switching characteristics over recommended operating free-air temperature range,
VCCA = 2.5 V ± 0.2 V (see Figure 5)
PARAMETER
tpd
ten
tdis
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
CLK.h or SCLK.h
CLK.h or SCLK.h
CMD.h
VCCB = 2.5 V
± 0.2 V
MIN
VCCB = 3 V
± 0.3 V
VCCB = 3.3 V
± 0.3 V
MAX
MIN
MAX
MIN
MAX
1
4
1
3.4
1
3.1
1
3.7
1
3.5
1
3.6
CLK.0 or SCLK.0
1
3.9
1
3.5
1
3.5
CLK-f.h or SCLK-f.h
2
8.3
2
7.3
2
7
CMD.0
1
3.2
1
3.1
1
2.7
CMD.h
CMD.1
1
3.6
1
3
1
2.8
CMD.0
CMD.h
1
3
1
3
1
3
CS0
B
1
4.2
1
3.7
1
3.3
R/B
R/B.h
1
3.1
1
3
1
2.9
WE
WE.h
1
3.6
1
3.4
1
3
WP
WP.h
1
3.5
1
3.1
1
2.9
DAT1.0 or DATA1.0
IRQ
1
3.3
1
3.3
1
3.2
DAT1.1 or DATA1.1
IRQ
1
3.6
1
3.4
1
3.2
DIR
B
1
4.7
1
4.4
1
3.6
DIR
A
1
5.3
1
5.3
1
5.1
R/B
R/B.h (open drain)
1
3.2
1
3.1
1
3
DAT1.0 or DATA1.0
IRQ
1
7.2
1
5.4
1
5.4
DAT1.1 or DATA1.1
IRQ
1
7
1
5.4
1
5.4
DIR
B
1
4.5
1
5.1
1
5.1
DIR
A
1
3.7
1
3.7
1
3.7
R/B
R/B.h (open drain)
1
3.2
1
3.9
1
3.9
UNIT
ns
ns
ns
maximum frequency and output skew over recommended operating free-air temperature range,
VCCA = 2.5 V ± 0.2 V (see Figure 5)
PARAMETER
Clock
fmax
Data
tsk(o)
44
VCCB = 3 V
± 0.3 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
52
52
B
A
52
52
A
B
26
26
B
A
26
A
B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
MIN
UNIT
MAX
MHz
26
0.7
0.7
ns
E E
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
switching characteristics over recommended operating free-air temperature range,
VCCA = 3.3 V ± 0.3 V (see Figure 5)
PARAMETER
tpd
ten
tdis
FROM
(INPUT)
TO
(OUTPUT)
A
B
VCCB = 3.3 V
± 0.3 V
MIN
MAX
B
1
2.9
A
1
3.8
CLK.h or SCLK.h
CLK.0 or SCLK.0
1
3.3
CLK.h or SCLK.h
CLK-f.h or SCLK-f.h
2
6.1
CMD.h
CMD.0
1
2.7
CMD.h
CMD.1
1
2.7
CMD.0
CMD.h
1
2.6
CS0
B
1
3.7
R/B
R/B.h
1
2.5
WE
WE.h
1
3
WP
WP.h
1
2.8
DAT1.0 or DATA1.0
IRQ
1
3.2
DAT1.1 or DATA1.1
IRQ
1
3.2
DIR
B
1
3.7
DIR
A
1
4.7
R/B
R/B.h (open drain)
1
4.9
DAT1.0 or DATA1.0
IRQ
1
5.3
DAT1.1 or DATA1.1
IRQ
1
5.2
DIR
B
1
5
DIR
A
1
4.7
R/B
R/B.h (open drain)
1
6
UNIT
ns
ns
ns
maximum frequency and output skew over recommended operating free-air temperature range,
VCCA = 3.3 V ± 0.3 V (see Figure 5)
PARAMETER
Clock
fmax
Data
tsk(o)
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
52
B
A
52
A
B
26
B
A
26
A
B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
UNIT
MAX
MHz
0.7
ns
45
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SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
operating characteristics, VCCA = 1.8 V, VCCB = 3 V, TA = 25°C
PARAMETER
CpdA
CpdB0
CpdB1
46
TEST CONDITIONS
TYP
Power dissipation capacitance per transceiver,
A-port input, B-port output
Outputs enabled
9
Outputs disabled
0.1
Power dissipation capacitance per transceiver,
B-port input, A-port output
Outputs enabled
Outputs disabled
7.5
Power dissipation capacitance per transceiver,
A-port input, B-port output
Outputs enabled
16.5
Power dissipation capacitance per transceiver,
B-port input, A-port output
Outputs enabled
Outputs disabled
2
Power dissipation capacitance per transceiver,
A-port input, B-port output
Outputs enabled
18
Power dissipation capacitance per transceiver,
B-port input, A-port output
Outputs enabled
POST OFFICE BOX 655303
CL = 0,
f = 10 MHz
Outputs disabled
• DALLAS, TEXAS 75265
pF
0.1
CL = 0,
f = 10 MHz
Outputs disabled
Outputs disabled
16
UNIT
4
pF
0.1
CL = 0,
f = 10 MHz
6
3
pF
E E
+ !"" !#"$"#"%! "%
SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
2 × VCCO
RL
From Output
Under Test
S1
Open
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
tPLZ/tPZL (OD)
Open
2 × VCCO
GND
2 × VCCO
VCCO
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
LOAD CIRCUIT
CL
RL
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
VCCA
Output
Control
(low-level
enabling)
VCCA/2
Input
VCCI/2
VCCI/2
0V
tPLH
tPLZ
Output
VOH
VCCO/2
VOL
VCCO/2
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
tPHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCA/2
0V
tPZL
VCCI
VTP
0.1 V
0.15 V
0.15 V
0.3 V
VCCO/2
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VTP
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
E E
+ !"" !#"$"#"%! "%
SCES615B – OCTOBER 2004 – REVISED DECEMBER 2004
MECHANICAL DATA
GQC (S-PBGA-N48)
PLASTIC BALL GRID ARRAY
4,10
3,90
SQ
3,00 TYP
0,50
G
F
0,50
E
D
3,00 TYP
C
B
A
1
A1 Corner
2
3
4
5
6
7
Bottom View
0,77
0,71
1,00 MAX
Seating Plane
0,35
0,25
0,25
0,05 M
0,08
0,15
4200460/E 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar Jr.  BGA configuration
Falls within JEDEC MO-225
MicroStar Jr. is a trademark of Texas Instruments.
48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPLG008D – APRIL 2000 – REVISED FEBRUARY 2002
GQC (S-PBGA-N48)
PLASTIC BALL GRID ARRAY
4,10
3,90
SQ
3,00 TYP
0,50
G
F
0,50
E
D
3,00 TYP
C
B
A
1
A1 Corner
2
3
4
5
6
7
Bottom View
0,77
0,71
1,00 MAX
Seating Plane
0,35
0,25
0,25
0,05 M
0,08
0,15
4200460/E 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar Junior  BGA configuration
Falls within JEDEC MO-225
MicroStar Junior is a trademark of Texas Instruments.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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